MOS OPERATING

MODES &
REGIONS
By- Bhushan
M
AGENDA

Introduction To Operating Modes

o Accumulation
o Depletion
o Inversion

Introduction To Operating Regions

o Cut-off Region
o Linear Region
o Saturation Region
MOS OPERATING MODES
To understand the different bias modes of an MOS we consider 3 different bias
voltages.

(1) below the flatband voltage, VFB

(2) between the flatband voltage and the threshold voltage, VT, and
(3) larger than the threshold voltage.

Depending on the polarity and the magnitude of VG , three different operating

regions can be observed for the MOS system:

 Accumulation

 Depletion

 Inversion
FLAT BAND
 Flatband conditions exist when no
charge is present in the
semiconductor so that the Si
energy band is flat.

The voltage separating the

accumulation and depletion regime
is referred to as the flatband
voltage, VFB.
The flatband voltage is obtained
when the applied gate voltage
equals the work function
difference between the gate metal
and the semiconductor.
 If there is a fixed charge in the oxide and/or at the
oxide-silicon interface, the expression for the flatband
voltage must be modified accordingly.

NMOS junction (Vertical Cross-Section)

ACCUMULATION S
G = -Vg
D
 Accumulation mode refers to the
accumulation of majority carriers
under the gate.

 Achieved by applying Negative

Voltage is applied to the gate
electrode.

 Holes accumulate near the gate.

 Electric field is directed towards

the gate electrode.

 Negative surface potential causes

the energy bands to bend
downward near the surface.
NMOS junction (Vertical Cross-Section)
DEPLETION
 Depletion mode refers to the depletion of e t i on
pl
De ion
majority carriers under the gate. Reg

 A small positive gate voltage is applied.

 Since substrate bias is zero, the oxide
electric field will be directed towards the
substrate.
 Majority carriers will be repelled back
into the substrate.
 Depletion region is formed
 The small positive bias applied causes the
semiconductor band bends upward.

 No channel for conduction. NMOS junction (Vertical Cross-Section)

INVERSION MODE

 Inversion mode refers to the accumulation of minority carriers under

the gate.
 A more positive voltage also attracts electrons (the minority carriers)
to the surface, which form the so-called inversion layer.
 Inversion occurs at voltages beyond the threshold voltage.
 NMOS junction (Vertical Cross-Section)
 In inversion, there exists a negatively charged inversion layer at the oxide-semiconductor
interface in addition to the depletion-layer.

 This inversion layer is due to minority carriers, which are attracted to the interface by the
positive gate voltage.

 The large positive surface potential causes the energy bands to bend further upward.

 Accumulation of minority electrons near the oxide.

Different Operating
Regions Of
MOSFET Device
Operation with Zero Gate Voltage
 With zero voltage applied to gate, two back-to-back
diodes exist in series between drain and source.
 “They” prevent current conduction from drain to
source when a voltage vDS is applied. yielding very
high resistance (1012ohms)
 Device is off.
 No current even if vDS is applied.
Cutoff Region
VGS < VT , VGD < VT
ID = 0A
 Channel is off at both Source and Drain.
 No conduction and no current flow between Source
and Drain
Creating a Channel for
Current Flow
 source and drain are grounded and
positive voltage is applied to gate
 step #1: GS is applied to the gate
terminal, causing a positive build up of
positive charge along metal electrode.

The enhancement-type NMOS transistor with a

 step #2: This “build up” causes free positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate
holes to be repelled from region of p-
type substrate under gate.
 step #3: This “migration” results in
the uncovering of negative bound
charges, originally neutralized by
the free holes

 step #4: The positive gate voltage

also attracts electrons from the n+
source and drain regions into the The enhancement-type NMOS transistor with a
channel. positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate
 this induced channel is
also known as an
inversion layer

 step #5: Once a sufficient number of

“these” electrons accumulate, an n-
region is created and connecting the
source and drain region.

 step #6: This provides path for current

flow between Drain and Source.

The enhancement-type NMOS transistor with a

positive voltage applied to the gate. An n channel is
induced at the top of the substrate beneath the gate
LINEAR REGION
 when the gate voltage exceeds the threshold G
the MOS can conduct and therefore turns on. S D
Linear Region
VDS < VGS – VT n+ n+ +
The drain current is given by:
p _

ID = K [2(VGS – VT)VDS – VDS2]

Bulk (substrate)
K is known as the conductance parameter, and is
defined as:  W  C 
K    ox  Cox = ox ε
 L  2 
C ox = Gate Oxide Capacitance
t
ox

tox = thickness of the oxide

εox = Dielectric constant of Silicon di-oxide

µm = Electron mobility from Source to Drain

W = Width and Length of the MOSFET
L
SATURATION REGION +
G - VGG
S D
 While the MOS is still on, if we continue to
increase VDS without increasing VGS, there
n+ p n+ +
VDD
will come a point when the voltage near the -
drain becomes less than the threshold (VGD < Bulk (substrate)
VT). This is known as the saturation region.
VD ≥V GS - VT
The drain current is given by:
ID = K (VGS – VT)2

 Current is nearly independent of VDS, depending only on VGS.

 One might expect the MOS to operate like in cutoff under these
bias conditions but it does not.
 The channel in saturation mode is typically Pin
c h-O
represented as tapered or wedged Large ff
currents still conduct via the channel due to
the large voltage drop across drain and
source, but changes little with increasing
VDS.

Pinch-off (going from triode to saturation)

 The channel near the drain begins for fall below the
threshold condition when VGD = VT
 In terms of the drain-source voltage, this corresponds
to:
VDS(pinch-off) = VGS - VT
Summary of operating modes

 Cut-Off:
VGS < VT
 Linear:
VGS > VT
 Saturation:
VGS >> VT

For n-channel
enhancement MOS
References:

i. Microelectronic Circuits by Adel S. Sedra and

Kenneth C. Smith.

ii. Basic VLSI Design by Douglas A.Pucknell and

Kamran Eshraghian, 3rd Edition.
Queries??
Thank You