Chapter 3:

The Intel 8086 Micro- Processor

Architecture
Introduction
 This chapter presents the microprocessor as a programmable device by first
looking at its internal programming model and then how its memory space is
addressed.
 The architecture of Intel microprocessors is presented, as are the ways that the
family members address the memory system.
 Addressing modes for this powerful family of microprocessors are described for
the real, protected, and flat modes of operation.
INTERNAL MICROPROCESSOR
ARCHITECTURE
 Before a program is written or instruction investigated, internal configuration of
the microprocessor must be known.
 In a multiple core microprocessor each core contains the same programming
model.
 Each core runs a separate task(process) or thread simultaneously.
A thread consists of a program counter, a register set, and a stack space.
A task shares with peer threads its code section, data section, and operating
system resources
The Programming Model
 8086 through Core2 considered program visible.
 registers are used during programming and are specified by the instructions
 Other registers considered to be program invisible.
 not addressable directly during applications programming
 80286 and above contain program-invisible registers to control and operate
protected memory.
 and other features of the microprocessor
 80386 through Core2 microprocessors contain full 32-bit internal architectures.
 8086 through the 80286 are fully upward-compatible to the 80386 through
Core2.
 Figure 1 illustrates the programming model 8086 through Core2 microprocessor.
 including the 64-bit extensions
Figure 1  The programming model of the 8086 through the Core2
microprocessor including the 64-bit extensions.
Multipurpose Registers
 RAX - a 64-bit register (RAX), a 32-bit register (accumulator) (EAX), a 16-bit
register (AX), or as either of two 8-bit registers (AH and AL).

 The accumulator is used for instructions such as multiplication, division, and

some of the adjustment instructions.

 Intel plans to expand the address bus to 52 bits to address 4P (252~1015 =peta)
bytes of memory.
Address Space (Main Memory: RAM)
 Address bus:16 bit Address Space:64 KBytes
 Address bus:20 bit Address Space:1 MBytes Address bus:32 bit Address
Space:4 GBytes Address bus:34 bit Address Space:16GBytes
 Address bus:36 bit Address Space:64GBytes
 Address bus:38 bit Address Space:256GBytes
 Address bus:52 bit Address Space:1015 Bytes
 RBX, addressable as RBX, EBX, BX, BH, BL.
 BX register (base index) sometimes holds offset address of a location in the memory
system in all versions of the microprocessor
 RCX, as RCX, ECX, CX, CH, or CL.
 a (count) general-purpose register that also holds the count for various instructions
 RDX, as RDX, EDX, DX, DH, or DL.
 a (data) general-purpose register
 holds a part of the result from a multiplication
or part of dividend before a division
 RBP, as RBP, EBP, or BP.
 points to a memory (base pointer) location
for memory data transfers
 RDI addressable as RDI, EDI, or DI.
 often addresses (destination index) string destination data for the string instructions
 RSI used as RSI, ESI, or SI.
 the (source index) register addresses source string data for the string instructions
 like RDI, RSI also functions as a general-
purpose register
 R8 - R15 found in the Pentium 4 and Core2 if 64-bit extensions are enabled.
 data are addressed as 64-, 32-, 16-, or 8-bit
sizes and are of general purpose
 Most applications will not use these registers until 64-bit processors are
common.
 the 8-bit portion is the rightmost 8-bit only
 bits 8 to 15 are not directly addressable as
a byte
Special-Purpose Registers
 Include RIP, RSP, and RFLAGS
 segment registers include CS, DS, ES, SS, FS, and GS
 RIP addresses the next instruction in a section of memory.
 defined as (instruction pointer) a code segment
 RSP addresses an area of memory called
the stack.
 the (stack pointer) stores data through this pointer
 RFLAGS indicate the condition of the microprocessor and control its operation.
 Figure 2 shows the flag registers of all versions of the microprocessor.
 Flags are upward-compatible from the 8086/8088 through Core2 .
 The rightmost five and the overflow flag are changed by most arithmetic and
logic operations.
 although data transfers do not affect them
Figure 2  The EFLAG and FLAG register counts for the entire 8086 and Pentium
microprocessor family.

• Flags never change for any data transfer or

program control operation.
• Some of the flags are also used to control
features found in the microprocessor.
List of Each Flag bit, with a brief description
of function.
 C (carry) holds the carry after addition or borrow after subtraction.
 also indicates error conditions
 P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for
odd parity; logic 1 for even parity.
 if a number contains three binary one bits, it has odd parity; If a number contains no
one bits, it
has even parity
 A (auxiliary carry) holds the carry (half-carry) after addition or the borrow after
subtraction between bit positions 3 and 4 of the result.
 Z (zero) shows that the result of an arithmetic or logic operation is zero.
 S (sign) flag holds the arithmetic sign of the result after an arithmetic or logic
instruction executes.
 T (trap) The trap flag enables trapping through an on-chip debugging feature.
 I (interrupt) controls operation of the INTR (interrupt request) input pin.
 D (direction) selects increment or decrement mode for the DI and/or SI
registers.
 O (overflow) occurs when signed numbers are added or subtracted.
 an overflow indicates the result has exceeded
the capacity of the machine
Segment Registers
 Generate memory addresses when combined with other registers in the
microprocessor.
 Four or six segment registers in various versions of the microprocessor.
 A segment register functions differently in real mode than in protected mode.
 Following is a list of each segment register, along with its function in the system.
 CS (code) segment holds code (programs and procedures) used by the
microprocessor.
 DS (data) contains most data used by a program.
 Data are accessed by an offset address or contents of other registers that hold the
offset address
 ES (extra) an additional data segment used by some instructions to hold
destination data.
 SS (stack) defines the area of memory used for the stack.
 stack entry point is determined by the stack segment and stack pointer registers
 the BP register also addresses data within
the stack segment
 FS and GS segments are supplemental segment registers available in 80386–
Core2 microprocessors.
 allow two additional memory segments for
access by programs
 Windows uses these segments for internal operations, but no definition of their
usage
is available.
REAL MODE MEMORY
ADDRESSING
 80286 and above operate in either the real or protected mode.
 Real mode operation allows addressing of only the first 1M byte of memory
space—even in Pentium 4 or Core2 microprocessor.
 the first 1M byte of memory is called the real memory, conventional memory, or
DOS memory system
Segments and Offsets
 All real mode memory addresses must consist of a segment address plus an offset
address.
 segment address defines the beginning address of any 64K-byte memory segment
 offset address selects any location within the
64K byte memory segment
 Figure 3 shows how the segment plus offset addressing scheme selects a memory
location.
Figure 3  The real mode memory-addressing scheme, using a segment
address plus an offset.

– this shows a memory

segment beginning at
10000H, ending at
location IFFFFH
• 64K bytes in length

– also shows how an

offset address, called a
displacement, of
F000H selects location
1F000H in the memory
 Once the beginning address is known, the ending address is found by adding
FFFFH.
 because a real mode segment of memory is 64K in length
 The offset address is always added to the segment starting address to locate the
data.
 Segment and offset address is sometimes written as 1000:2000.
 a segment address of 1000H; an offset of 2000H
Default Segment and Offset Registers

 The microprocessor has rules that apply to segments whenever memory is

addressed.
 these define the segment and offset register combination
 The code segment register defines the start of the code segment.
 The instruction pointer locates the next instruction within the code segment.
 Another of the default combinations is the stack.
 stack data are referenced through the stack segment at the memory location addressed
by either the stack pointer (SP/ESP) or the pointer (BP/EBP)
 Figure 4 shows a system that contains four memory segments.
 a memory segment can touch or overlap if 64K bytes of memory are not required for
a segment
Figure 4  A memory system showing the placement of four memory
segments.
– think of segments as
Windows that can be
moved over any area
of memory to access
data or code
– a program can have
more than four or six
segments,
• but only access four or
six segments at a time
Figure 5  An application program containing a code, data, and stack segment loaded
into a DOS system memory.

– a program placed in
memory by DOS is loaded
in the TPA at the first
available area of memory
above drivers and other
TPA programs
– area is indicated by a free-
pointer maintained by DOS
– program loading is handled
automatically by the
program loader within DOS
TPA

 The transient program area (TPA) holds the DOS (disk

operating system) operating system; other programs that
control the computer system.
Segment and Offset Addressing Scheme
Allows Relocation
 Segment plus offset addressing allows DOS programs to be relocated in memory.
 A relocatable program is one that can be placed into any area of memory and
executed without change.
 Relocatable data are data that can be placed in any area of memory and used
without any change to the program.
 Because memory is addressed within a segment by an offset address, the
memory segment can be moved to any place in the memory system without
changing any of the offset addresses.
 Only the contents of the segment register must be changed to address the
program
in the new area of memory.
 Windows programs are written assuming that the first 2G of memory are
available for code and data.
Addressing Modes
Introduction
 Efficient software development for the microprocessor requires a complete
familiarity with the addressing modes employed by each instruction.
Objectives (cont.)
Upon completion of this topic, you will be able to:
 Explain the operation of each data-addressing mode.
 Use the data-addressing modes to form assembly language statements.
 Select the appropriate addressing mode to accomplish a given task.
 Detail the difference between addressing memory data using real mode and
protected mode operation.
2–1  DATA ADDRESSING MODES
 MOV instruction is a common and flexible instruction.
 provides a basis for explanation of data-addressing modes
 Figure 2–1 illustrates the MOV instruction and defines the direction of data flow.
 Source is to the right and destination the left, next to the opcode MOV.
 an opcode, or operation code, tells the microprocessor which operation to perform
Figure 2–1  The MOV instruction showing the source, destination,
and direction of data flow.
 Figure 2–2 shows all possible variations of the data-addressing modes using
MOV.
 These data-addressing modes are found with all versions of the Intel
microprocessor.
 except for the scaled-index-addressing mode, found only in 80386 through Core2
 RIP relative addressing mode is not illustrated.
 only available on the Pentium 4 and Core2
in the 64-bit mode
Figure 2–2  8086–Core2 data-addressing modes.
Register Addressing
 The most common form of data addressing.
 once register names learned, easiest to apply.
 The microprocessor contains these 8-bit register names used with register
addressing: AH, AL, BH, BL, CH, CL, DH, and DL.
 16-bit register names: AX, BX, CX, DX, SP, BP, SI, and DI.
 In 80386 & above, extended 32-bit register names are: EAX, EBX, ECX, EDX,
ESP, EBP, EDI, and ESI.
 64-bit mode register names are: RAX, RBX, RCX, RDX, RSP, RBP, RDI, RSI,
and R8 through R15.
 Important for instructions to use registers that are the same size.
 never mix an 8-bit \with a 16-bit register, an 8- or a 16-bit register with a 32-bit
register
 this is not allowed by the microprocessor and results in an error when assembled
Figure 2–3  The effect of executing the MOV BX, CX instruction at the point just before the
BX register changes. Note that only the rightmost 16 bits of register EBX change.
 Figure 2–3 shows the operation of the MOV BX, CX instruction.
 The source register’s contents do not change.
 the destination register’s contents do change
 The contents of the destination register or destination memory location change
for all instructions except the CMP and TEST instructions.
 The MOV BX, CX instruction does not affect the leftmost 16 bits of register
EBX.
Immediate Addressing
 Term immediate implies that data immediately follow the hexadecimal opcode in
the memory.
 immediate data are constant data
 data transferred from a register or memory location are variable data
 Immediate addressing operates upon a byte or word of data.
 Figure 2–4 shows the operation of a MOV EAX,13456H instruction.
Figure 2–4  The operation of the MOV EAX,13456H instruction. This
instruction copies the immediate data (13456H) into EAX.

• As with the MOV instruction illustrated in

Figure 2–3, the source data overwrites the
destination data.
 In symbolic assembly language, the symbol # precedes immediate data in some
assemblers.
 MOV AX,#3456H instruction is an example
 Most assemblers do not use the # symbol,
but represent immediate data as in the MOV AX,3456H instruction.
 an older assembler used with some Hewlett-Packard logic development does, as may
others
 in this course, the # is not used for immediate data
 The symbolic assembler portrays immediate data in many ways.
 The letter H appends hexadecimal data.
 If hexadecimal data begin with a letter, the assembler requires the data start with
a 0.
 to represent a hexadecimal F2, 0F2H is used
in assembly language
 Decimal data are represented as is and require no special codes or adjustments.
 an example is the 100 decimal in the
MOV AL,100 instruction
 An ASCII-coded character or characters may be depicted in the immediate form
if the ASCII data are enclosed in apostrophes.
 be careful to use the apostrophe (‘) for ASCII
data and not the single quotation mark (‘)
 Binary data are represented if the binary number is followed by the letter B.
 in some assemblers, the letter Y
 Each statement in an assembly language program consists of four parts or fields.
 The leftmost field is called the label.
 used to store a symbolic name for the memory location it represents
 All labels must begin with a letter or one of the following special characters: @,
$, -, or ?.
 a label can be any length from 1 to 35 characters
 The label appears in a program to identify the name of a memory location for
storing data and for other purposes.
 The next field to the right is the opcode field.
 designed to hold the instruction, or opcode
 the MOV part of the move data instruction is an example of an opcode
 Right of the opcode field is the operand field.
 contains information used by the opcode
 the MOV AL,BL instruction has the opcode MOV and operands AL and BL
 The comment field, the final field, contains a comment about the instruction(s).
 comments always begin with a semicolon (;)
Direct Data Addressing
 Applied to many instructions in a typical program.
 Two basic forms of direct data addressing:
 direct addressing, which applies to a MOV between a memory location and AL, AX,
or EAX
 displacement addressing, which applies to almost any instruction in the instruction set
 Address is formed by adding the displacement to the default data segment address
or an alternate segment address.
Direct Addressing
 Direct addressing with a MOV instruction transfers data between a memory
location, located within the data segment, and the AL (8-bit), AX (16-bit), or
EAX (32-bit) register.
 usually a 3-byte long instruction
 MOV AL,DATA loads AL from the data segment memory location DATA
(1234H).
 DATA is a symbolic memory location, while
1234H is the actual hexadecimal location
Figure 2–5  The operation of the MOV AL,[1234H] instruction when DS=1000H .

• This instruction transfers a copy contents of

memory location 11234H into AL.
– the effective address is formed by adding
1234H (the offset address) and 10000H
(the data segment address of 1000H times
10H) in a system operating in the real mode
Displacement Addressing
 Almost identical to direct addressing, except the instruction is 4 bytes wide
instead of 3.
 In 80386 through Pentium 4, this instruction can be up to 7 bytes wide if a 32-bit
register and a 32-bit displacement are specified.
 This type of direct data addressing is much more flexible because most
instructions use it.
Register Indirect Addressing
 Allows data to be addressed at any memory location through an offset address
held in any of the following registers: BP, BX, DI, and SI.
 In addition, 80386 and above allow register indirect addressing with any extended
register except ESP.
 In the 64-bit mode, the segment registers serve no purpose in addressing a
location
in the flat model.
Figure 2–6  The operation of the MOV AX, [BX] instruction when BX = 1000H and DS = 0100H. Note
that this instruction is shown after the contents of memory are transferred to AX.
 The data segment is used by default with register indirect addressing or any
other mode that uses BX, DI, or SI to address memory.
 If the BP register addresses memory, the stack segment is used by default.
 these settings are considered the default for
these four index and base registers
 For the 80386 and above, EBP addresses memory in the stack segment by
default.
 EAX, EBX, ECX, EDX, EDI, and ESI address memory in the data segment by
default.
 When using a 32-bit register to address memory in the real mode, contents of the
register must never exceed 0000FFFFH.
 In the protected mode, any value can be used in a 32-bit register that is used to
indirectly address memory.
 as long as it does not access a location outside
the segment, dictated by the access rights byte
 In the 64-bit mode, segment registers are
not used in address calculation; the register contains the actual linear memory
address.
 In some cases, indirect addressing requires specifying the size of the data by the
special assembler directive BYTE PTR, WORD PTR, DWORD PTR, or
QWORD PTR.
 these directives indicate the size of the memory data addressed by the memory
pointer (PTR)
 The directives are with instructions that address a memory location through a
pointer or index register with immediate data.
 Indirect addressing often allows a program to refer to tabular data located in
memory.
 Figure 2–7 shows the table and the BX register used to sequentially address each
location in the table.
 To accomplish this task, load the starting location of the table into the BX
register
with a MOV immediate instruction.
 After initializing the starting address of the table, use register indirect addressing
to
store the 50 samples sequentially.
Figure 2–7  An array (TABLE) containing 50 bytes that are
indirectly addressed through register BX.
Base-Plus-Index Addressing
 Similar to indirect addressing because it indirectly addresses memory data.
 The base register often holds the beginning location of a memory array.
 the index register holds the relative position
of an element in the array
 whenever BP addresses memory data, both the stack segment register and BP generate
the effective address
Locating Data with Base-Plus-Index
Addressing
 Figure 2–8 shows how data are addressed by the MOV DX, [BX + DI] instruction
when the microprocessor operates in the real mode.
 The Intel assembler requires this addressing mode appear as [BX][DI] instead of
[BX + DI].
 The MOV DX, [BX + DI] instruction is MOV DX,[BX][DI] for a program
written for the Intel ASM assembler.
Figure 2–8  An example showing how the base-plus-index addressing mode functions for the
MOV DX, [BX + DI] instruction. Notice that memory address 02010H is accessed because
DS=0100H, BX=1000H and DI=0010H.
Locating Array Data Using Base-Plus-Index
Addressing
 A major use is to address elements in a memory array.
 To accomplish this, load the BX register (base) with the beginning address of the
array and the DI register (index) with the element number to be accessed.
 Figure 2–9 shows the use of BX and DI to access an element in an array of data.
Figure 2–9  An example of the base-plus-index addressing mode. Here an
element (DI) of an ARRAY (BX) is addressed.
Register Relative Addressing
 Similar to base-plus-index addressing and displacement addressing.
 data in a segment of memory are addressed by adding the displacement to the contents
of a base or an index register (BP, BX, DI, or SI)
 Figure 2–10 shows the operation of the MOV AX,[BX+1000H] instruction.
 A real mode segment is 64K bytes long.
Figure 2–10  The operation of the MOV AX, [BX+1000H] instruction,
when BX=0100H and DS=0200H .
Addressing Array Data with Register Relative

 It is possible to address array data with register relative addressing.

 such as with base-plus-index addressing
 In Figure 2–11, register relative addressing is illustrated with the same example as
for base-plus-index addressing.
 this shows how the displacement ARRAY adds
to index register DI to generate a reference to
an array element
Figure 2–11  Register relative addressing used to address an element of
ARRAY. The displacement addresses the start of ARRAY, and DI accesses
an element.
Base Relative-Plus-Index Addressing

 Similar to base-plus-index addressing.

 adds a displacement
 uses a base register and an index register to
form the memory address
 This type of addressing mode often addresses a two-dimensional array of memory
data.
Addressing Data with Base Relative-Plus-
Index
 Least-used addressing mode.
 Figure 2–12 shows how data are referenced if the instruction executed by the
microprocessor is MOV AX, [BX + SI + 100H].
 displacement of 100H adds to BX and SI to form the offset address within the data
segment
 This addressing mode is too complex for frequent use in programming.
Figure 2–12  An example of base relative-plus-index addressing using a MOV AX,
[BX+SI+100H] instruction. Note: DS=1000H
Addressing Arrays with Base Relative-Plus-
Index
 Suppose a file of many records exists in memory, each record with many
elements.
 displacement addresses the file, base register addresses a record, the index register
addresses an element of a record
 Figure 2–13 illustrates this very complex form of addressing.
Figure 2–13  Base relative-plus-index addressing used to access a
FILE that contains multiple records (REC).