CHAPTER FOUR

COUNTERS & REGISTERS

Prepared by Praches Acharya Lalitpur Engineering College

Combinational & Sequential Circuits

Prepared by Praches Acharya Lalitpur Engineering College

Prepared by Praches Acharya Lalitpur Engineering College
Prepared by Praches Acharya Lalitpur Engineering College
Comparisons

Prepared by Praches Acharya Lalitpur Engineering College

 Flip-Flops

• Flip – Flop is a one bit memory as storing a logic 0 and when its
element. It acts as basic building block output is set at + 5 V dc, as storing a
of a sequential circuit that forms a logic 1.
feedback path. • The flip-flop is often called a latch,
• Flip-flops are used in the construction since it will hold, or latch, in either
of registers and counters, and in stable state.
numerous other applications.
• A flip-flop is a bi stable electronic
circuit that has two stable states - that
is, its output is either 0 or +5V dc as
shown in Fig. 8.1 b.
• For instance, when the flip-flop has its
output set at 0 V dc, it can be regarded
Prepared by Praches Acharya Lalitpur Engineering College
RS NOR-Gate latch/Flip-Flop

• The SR NOR Gate flip-flop actually has two outputs Q and Q’. There are
two inputs to the flip-flop defined as R and S. The Circuit diagram and its
truth table is shown below.

Prepared by Praches Acharya Lalitpur Engineering College

• The first input condition in the truth table is R = 0 and S = 0. The flip-flop
simply remains in its present state; that is, Q remains unchanged.
• The second input condition R = 0 and S = 1 is said to SET the flip-flop, and
it switches to the stable state where Q = 1.
• The third input condition R = 1 and S = 0 is said to RESET the flip-flop and
it switches to the stable state where Q = 0 (or Q’ = 1). and S = 0.
• The last input condition R = 1 and S = 1 is forbidden, as it forces the
outputs of both NOR gates to the low state. In other words, both Q = 0
and Q’ = 0 at the same time. so it is generally agreed never to impose this
input condition.

Prepared by Praches Acharya Lalitpur Engineering College

RS NAND - Gate latch/Flip-Flop

Prepared by Praches Acharya Lalitpur Engineering College

• We will call this latch an flip-flop.
• A low on the input will set the latch (Q = 1 and Q’ = 0).
• A low on the input will reset it (Q = 0).
• If both and are high, the flip-flop will remain in its previous state.
• Setting both and low simultaneously is forbidden since this forces
both Q and Q’ high.

Prepared by Praches Acharya Lalitpur Engineering College

Clocked RS Flip-Flops/ Gated RS Flipflop

Prepared by Praches Acharya Lalitpur Engineering College

• A clocked RS flip-flop can be enabled or disabled. A clocked RS flipflop is
obtained by adding two AND gates at inputs R and S of a basic NOR gate
flipflop.
• When the ENABLE input is low, the AND gate outputs must both be low and
changes in neither R nor S will have any effect on the flip-flop output Q. The
latch is said to be disabled.
• When the ENABLE input is high, the latch is said to be enabled. The output
will change in response to input changes as long as the ENABLE is high.
• When the ENABLE input goes low, the output will retain the information that
was present on the input when the high-to-low transition took place.
• It is possible to strobe or clock the flip-flop in order to store information (set
it or reset it) at any time, and then hold the stored information for any
desired period of time. This flip-flop is called a gated or clocked RS flipflop.

Prepared by Praches Acharya Lalitpur Engineering College

Clocked RS flipflop using NAND Gate

Prepared by Praches Acharya Lalitpur Engineering College

Prepared by Praches Acharya Lalitpur Engineering College
 Clocked D Flip-Flops

• D flip-flop is a circuit that needs only a single data input.

• D flip-flop is a bistable circuit whose D input is transferred to the output
when EN is high.
• When EN is low, Q will remain latched in its last state.

Prepared by Praches Acharya Lalitpur Engineering College

Positive-Edge-Triggered RS Flip-flops

• The clock (C) is applied to a positive

pulse-forming circuit and the
Positive Transitions developed are
then applied to a gated RS flip-flop.
• In positive edge – triggered RS
flipflop, the changes of state (Q)
occur according to the R and S
levels, but only during Positive
Transitions of the clock.
• In other words, S and R inputs
affect Q only while the positive
pulse is high, and they need to be
static only during this very short
time.
Prepared by Praches Acharya Lalitpur Engineering College
Negative-Edge-Triggered RS Flip-Flops
• In Negative edge – triggered RS flipflop, the changes of state (Q) occur according
to the R and S levels, but only during Negative Transitions of the clock.
• This flip-flop behaves exactly like the positive-edge-triggered RS flip-flop,except
that changes in output Q are synchronized with negative transitions of the clock
(C).
Prepared by Praches Acharya Lalitpur Engineering College
Prepared by Praches Acharya Lalitpur Engineering College
EDGE-TRIGGERED D FLIP-FLOPS

• Figure 8.21 shows a positive pulse-forming circuit at the input of a D latch.

The positive transition pulse (PT) enables the AND gates and at this
unique point in time, D and its complement hit the flip-flop inputs, forcing
Q to set or reset (unless Q equals D).
• This operation is called edge triggering because the flip-flop responds
only when the clock is in transition between its two voltage states.
• The triggering in Fig. 8.21 occurs on the positive-going edge of the clock;
this is why it's referred to as positive-edge triggering.
• When the clock is low, Q is latched in its last state. On the leading edge of
the clock (PT), the data bit is loaded into the flip-flop and Q takes on the
value of D.
• RESET and CLEAR functions can be inserted in D Flipflop. A high PRESET
forces Q to equal 1 and a high CLEAR forces Q to 0.
Prepared by Praches Acharya Lalitpur Engineering College
 Flipflop. A high PRESET forces Q to
equal 1 and a high CLEAR resets Q to
0. The PRESET and CLEAR are called
asynchronous inputs because they
activate the flip-flop independently of
• Depressing the RESET button will set the clock.
Q to 1 with the first (positive
Transition) PT of the clock. Q will
remain high as long as the button is
held closed. The first PT of the clock
after releasing the button will set Q
according to the D input.
• Furthermore, PRESET and CLEAR
functions can be inserted in D
Prepared by Praches Acharya Lalitpur Engineering College
• EDGE-TRIGGERED JK- FLIP-FLOPS
• A JK flipflop is the modified version of RS flipflop in which the intermediate
state of RS flipflop is more refined and precise.
• J stands for SET (as S in RS flipflop) and K stands for CLEAR (as R in RS flipflop).
• When both inputs J and K have 1, the flipflop switches to complement State.
Prepared by Praches Acharya Lalitpur Engineering College
• The basic circuit is identical to the previous positive-edge-triggered RS
flip-flop, with two important additions:
1. The Q output is connected back to the input of the lower AND gate.
2. The Q’ output is connected back to the input of the upper AND gate.
• This cross-coupling from outputs to inputs changes the RS flip-flop into a JK flip-
flop. The previous S input is now labeled J, and the previous R input is labeled K.
• When J and K are both low, Q retains its last value.
• When J is low and K is high, the flipflop is Reset.
• When J is high and K is low, the flipflop is Set.
• When both inputs J and K is High, the flipflop switches to Toggle/ complement
State.
Prepared by Praches Acharya Lalitpur Engineering College
Prepared by Praches Acharya Lalitpur Engineering College
T (Toggle) Flipflop

• T flip flop is called as Toggle flip flop.

• It is the simpler version of JK flipflop which can be obtained by
connecting both inputs J and K together.
• In T flip flop, toggling is the control change of output from 0 to 1 and 1 to
0.
• When T = 0, there is no change in the output and when T =1, then output
toggles.

Prepared by Praches Acharya Lalitpur Engineering College

JK MASTER-SLAVE FLIP-FLOPS

Prepared by Praches Acharya Lalitpur Engineering College

Prepared by Praches Acharya Lalitpur Engineering College
• Characteristic Equations of Flip-flops
The characteristic equations of flip-flops are useful in analyzing circuits. Here,
next output Qn+1 is expressed as a function of present output Qn and input to
flip-flops. Karnaugh Map can be used to get the optimized expression and truth
table of each flip-flop is mapped into it.

Prepared by Praches Acharya Lalitpur Engineering College

 •

Prepared by Praches Acharya Lalitpur Engineering College

 Excitation Table

• During the design process, we may need to know the transition from present
state to next state and wish to find the input conditions that will cause the
required transition. For this reason, we need a table that lists the required
inputs for a given change of state. Such a Table is called Excitation Table.

Prepared by Praches Acharya Lalitpur Engineering College

 REGISTERS

• Registers are important digital building blocks that can be used to store binary
data. They can accept data bits in either a serial or a parallel format and can,
likewise, deliver data in either serial or parallel.
• A register is composed of a group of flip-flops to store a group of bits (word). N
bit Register consists of N number of flip-flops.
• A Shift Register is a type of sequential logic circuit that can be used for storage
or transfer of the binary data. Shift register is capable of shifting bits either
towards right hand side or towards left hand side.
 TYPES OF SHIFT REGISTERS

• Serial in-serial out

• Serial in-parallel out
• Parallel in-serial out
• Parallel in-parallel out
 COUNTERS

• A counter is probably one of the most useful and versatile subsystems in a

digital system.
• A counter driven by a clock can be used to count the number of clock cycles.
Since the clock pulses occur at known intervals, the counter can be used as an
instrument for measuring time and therefore period or frequency.
• There are basically two different types of counters-synchronous and
asynchronous.
 A SY NC HR ON O US C OU NT ER S

• Ripple Counters
The figure below shows a three bit binary ripple counter constructed using edge
triggered JK flip flops connected in cascade. The system clock drives flip-flop A.
The output of A drives B, and the output of B drives flip-flop C. All the J and K
inputs are tied to +Vcc· This means that each flip-flop will change state (toggle)
with a negative transition at its clock input.
• Let's assume that the flip-flops are all initially reset to produce 0 outputs. If we
consider A to be the least-significant bit(LSB) and C the most-significant bit
(MSB), we can say the contents of the counter is CBA = 000.
• Every time there is a clock NT, flip-flop A will change state. Thus at point a on
the time line, A goes high, at point b it goes back low, at c it goes back high, and
so on.
• Every time there is a clock NT, flip-flop A will change state. Thus at point a on the
time line, A goes high, at point b it goes back low, at c it goes back high, and so on.
• Since A acts as the clock for B, each time the waveform at A goes low, flip-flop B
will toggle. Thus at point b on the time line, B goes high; it then goes low at point
d and toggles back high again at point f .
• Since B acts as the clock for C, each time the waveform at B goes low, flip-flop C
will toggle. Thus C goes high at point d on the time line and goes back low again at
point h.
• Because each output condition shown in the truth table is the binary equivalent
of the number of clock NTs, the three cascaded flip-flops in Fig. 10.1 comprise a 3-
bit binary ripple counter. This counter can be used to count the number of clock
transitions up to a maximum of seven. The counter begins at count 000 and
advances one count for each clock transition until it reaches count 111. At this
point it resets back to 000 and begins the count cycle all over again. We can say
that this ripple counter is operating in a count-up mode.
• Since a binary ripple counter counts in a straight binary sequence, it is easy to
see that a counter having n flip-flops will have 2n output conditions. For
instance, the three-flip-flop counter has 23 = 8 output conditions (000 through
111). Five flip-flops would have 25 = 32 output conditions (00000 through
11111 ), and so on. The largest binary number that can be represe:1ted by n
cascaded flip-flops has a decimal equivalent of 211 - 1.
• For example, the three-flip-flop counter reaches a maximum decimal number
of 23 - 1. The maximum decimal number for five flip-flops is 25 - l = 31, while
six flip-flops have a maximum count of 63.
• A three-flip-flop counter is often referred to as a modulus-8 (or mod-8) counter
since it has eight states. Similarly, a four-flip-flop counter is a mod-16 counter,
and a six-flip-flop counter is a mod-64 counter. The modulus of a counter is the
total number of states through which the counter can progress.
 R ipp le C ou nte r ( Do wn Co unt er)

• A 3bit ripple counter (down counter) is shown in Fig. 10.4. The system clock is
still used at the clock input to flip-flop A, but A’ is used to drive flipflop B,
likewise; B’ is used to drive flip-flop C.
• Flip-flop A simply toggles with each negative clock transition as before. But
flip-flop B will toggle each time A goes high! Notice that each time A goes high,
A’ goes low, and it is this negative transition on A that triggers B. On the time
line, B toggles at points a, c, e, g and i.
• Similarly, flip-flop C is triggered by B’ and so C will toggle each time B goes
high. Thus C toggles high at point a on the time line, toggles back low at point
e and goes back high again at point i.
• The counter contents become ABC= 111 at point a on the time line, change to
110 at point b, and change to 101 at point c. Notice that the counter is
operating in a count-down mode. This is still a mod-8 counter, since it has eight
discrete states, but it is connected as a down counter.
 Asynchronous up-down counter

• A 3-bit asynchronous up-down counter that counts in a straight binary sequence

is shown in Fig. 10.5. It is simply a combination of the two counters ( up and
down ring counter) discussed previously.
• For this counter to progress through a count-up sequence, it is necessary to
trigger each flip-flop with the true side of the previous flip-flop. If the count-
down control line is low and the count-up control line is high, the counter will
then operate as up counter.
• On the other hand, if count-down is high and count-up is low, each flip-flop will
be triggered from the complement side of the previous flip-flop. The counter
will then be in a count-down mode and will operate as down counter.
• This process can be continued to other flip-flops down the line to form an up-
down counter of larger moduli.
 DECODING GATES
• A decoding gate can be connected to the outputs of a counter in such a way
that the output of the gate will be high (or low) only when the counter contents
are equal to a given state.
 Synchronous Counters

• In Synchronous Counters,
every flip-flop is triggered in
synchronism with the clock.

Mod-8 binary counter

with parallel clock input:
• J and K inputs of each flip-flop
is kept high, such that the
flip-flop will toggle with
any clock NT at its clock input.
We then use AND gates to gate every second clock to flip-flop B, every fourth clock to
flip-flop C, and so on.
• The clock is applied directly to flip-flop A. At negative transition of the clock input
the flipflop A toggles, i.e. flip-flop A will change state with each clock NT.
• Whenever A is high, AND gate X is enabled and a clock pulse is passed through the
gate to the clock input of flip-flop B. Thus B changes state with every other clock NT
at points b, d,f, and h on the time line.
• Since AND gate Y is enabled and will transmit the clock to flip-flop C only when both
A and B are high, flip-flop C changes state with at points d and h on the time line.
• Examination of the waveforms and the truth table reveals that this counter
progresses upward in a natural binary sequence from count 000 up to count 111,
advancing one count with each clock NT;
• This is a mod-8 parallel or synchronous binary counter operating in the count-up
mode.
 COUNTER DESIGN AS A SYNTHESIS PROBLEM

• Design a modulo – 6 counter for the state diagram shown below.

• Step 1: Number of flipflops required is 3

• Now with three flip-flop, 8 different states are possible but in our design states
110 and 111 are not used in the counting sequence. To start with we shall
assume the counter is always initialized with one of the valid states and not
110 or 111. We decide to use three JK flip-flops labeled A, B and C as memory
element for this design.
• Step 2: Form a state synthesis table as shown in Table 10.1. The first column
represents current state of the counter and second column represents next
state of the counter state transition diagram. We fill up next three columns
using excitation table of JK flip-flop.
• Step 3: Obtain logic equation for each flip-flop input as a function of present
state of the counter using Karnaugh Map. Note that values corresponding to
unused states 110 and 111 appear as don't care 'x'. We have not shown
Karnaugh Map for JA and KAas it is obvious from Table 10.1 that JA =KA= 1.
• Step 4: This is the final step. In this step, circuit diagram is drawn from the
obtained equations. The decoding output is obtained from a three input AND
gate which goes high every time the counter goes to a valid state CBA = 000
and that occurs in every 6th clock cycle.
 CHANGING THE COUNTER MODULUS

• Counter Modulus
• Counters have a modulus given by 2n, where n indicates the number of flip-flops. Such
counters are said to have a "natural count" of 2n.
• A mod-2 counter consists of a single flip-flop; a mod-4 counter requires two flip-flops,
and it counts through four discrete states. Three flip-flops form a mod-8 counter, while
four flip-flops form a mod-16 counter. Thus we can construct counters that have a
natural count of 2, 4, 8, 16, 32, and so on by using the proper number of flip-flops.
• A small modulus counter can always be constructed from a larger modulus counter by
skipping states. Such counters are said to have a modified count. It is first necessary to
determine the number of flip-flops required. The correct number of flip-flops is
determined choosing the lowest natural count that is greater than the desired
modified count.
• For example, a mod-7 counter requires three flip-flops, since 8 is the lowest natural
count greater than the desired modified count of 7.
 * Indicate how many flip-flops are required to construct each of the following counters: (a) mod-3, (b)
mod-6, and (c) mod-9.
* What modulus counters can be constructed with the use of four flip-flops?
• Mod-3 Counter
The two flip-flops in Fig. 10.16 have been connected to provide a mod-3 counter.
Since two flip-flops have a natural count of 4, this counter skips one state. The
waveforms and the truth table in Fig. 10.16 show that this counter progresses
through the count sequence 00, 01, 10, and then back to 00. It clearly skips
count 11.