Module -2

Sequential Circuits
 Sequential Logic - Introduction

• External outputs in a sequential circuit are a function

not only of external inputs but also of the present
state of the memory elements.
• The next state of the memory elements is also a
function of external inputs and the present state.
• Thus, a sequential circuit is specified by a time
sequence of inputs, outputs, and internal states.
• Two main types of sequential circuits -classification
depends on the timing of their signals.
• A synchronous sequential circuit is a system whose
behavior can be defined from the knowledge of its
signals at discrete instants of time.
• The behavior of an asynchronous sequential circuit
depends upon the order in which its input signals
change and can be affected at any instant of time.
• The memory elements commonly used in
asynchronous sequential circuits are time-delay
devices.
Flip-Flops
• A flip-flop circuit can maintain a binary state
indefinitely (as long as power is delivered to the
circuit) until directed by an input signal to switch
states.
• The major differences among various types of flip-
flops are in the number of inputs they possess and
the manner in which the inputs affect the binary
state.
• A flip-flop is a bistable electronic circuit that has two
stable states-that is, its output is either 0 or +5 Vdc.
• Bistable device can be used store one binary digit
(bit).
Basic Flip-Flop Circuit
• The cross-coupled connection from the output of one
gate to the input of the other gate constitutes a
feedback path.
• Each flip-flop has two outputs, Q and Q′, and two
inputs, set and reset.
• This type of flip-flop is sometimes called a direct-
coupled RS flip-flop or SR latch.
• Both of these RS FFs are said to be
transparent; that is, any change in input
information at R or S is transmitted
immediately to the output at Q and Q’
according to the truth table.
Synchronous Operation

• Nearly all of the circuits in a digital system (computer)

change states in synchronism with the system clock.
• A change of state will either occur as the clock
transition from low to high or as it transition from high
to low.
• The low to high transition is frequently called the
positive transition (PT). A circuit that changes state at
this time is said to be positive-edge-triggered
• The high to low is called the negative transition (NT). A
circuit that changes state at this time is said to be
negative-edge-triggered.
• Virtually all circuits in a digital system are either
positive-edge-triggered or negative-edge-triggered,
and thus are synchronized with the system clock.

• There are few exceptions – The operation of push

button (RESET) by a human operator might result in
an instant change of state that is not in synchronism
with the clock. This is called an asynchronous
operation.
Clocked RS Flip-Flop

• By adding gates to the inputs of the basic circuit, the flip-flop can
be made to respond to input levels during the occurrence of a
clock pulse.
• The clocked RS flip-flop shown in Fig. 6-4(a) consists of a basic
NOR flip-flop and two AND gates.
• The outputs of the two AND gates remain at 0 as long as the clock
pulse (abbreviated CP) is 0, regardless of the S and R input values.
• When the clock pulse goes to 1, information from the S and R
inputs is allowed to reach the basic flip-flop.
• The set state is reached with S = 1, R = 0. and CP = 1. To change to
the clear state, the inputs must be S = 0, R = 1, and CP = 1. With
both S = 1 and R = 1, the occurrence of a clock pulse causes both
outputs to momentarily go to 0.
• It is possible to strobe or clock the flip-flop in
order to store information (set it or reset it) at
any time, and then hold the stored
information for any desired period of time.
This FF is called a gated or Clocked RS
flip-flop.
D Flip-Flop
S

R
• The D flip-flop shown in Fig. is a modification of the
clocked RS flip-flop.
• NAND gates 1 and 2 form a basic flip-flop and gates 3
and 4 modify it into a clocked RS flip-flop.
• The D input goes directly to the S input, and its
complement, through gate 5, is applied to the R
input.
• As long as the clock pulse input is at 0, gates 3 and 4
have a 1 in their outputs, regardless of the value of
the other inputs.
• The D input is sampled during the occurrence of a
clock pulse, if it is 1, the output of gate 3 goes to 0,
switching the flip-flop to the set state (unless it was
already set). If it is 0, the output of gate 4 goes to 0,
switching the flip-flop to the clear state.
• The D flip-flop receives the designation from its
ability to transfer “data” into a flip-flop.
• It is basically an RS flip-flop with an inverter in the R
input. The added inverter reduces the number of
inputs from two to one. This type of flip-flop is
sometimes called a gated D-latch.
• The CP input is often given the variable designation G
(for gate) to indicate that this input enables the
gated latch to make possible the data entry into the
flip-flop.
Clocked D flip-flop
JK Flip-Flop
• A JK flip-flop is a refinement of the RS flip-flop in that
the indeterminate state of the RS type is defined in
the JK type.
• Inputs J and K behave like inputs S and R to set and
clear the flip-flop (note that in a JK flip-flop, the letter
J is for set and the letter K is for clear).
• When inputs are applied to both J and K
simultaneously, the flip-flop switches to its
complement state, that is, if Q = 1, it switches to Q =
0, and vice versa.
• A clocked JK flip-flop is shown in Fig. Output Q is ANDed with
K and CP inputs so that the flip-flop is cleared during a clock
pulse only if Q was previously 1.
• Similarly, output Q′ is ANDed with J and CP inputs so that the
flip-flop is set with a clock pulse only if Q′ was previously 1.
• The JK flip-flop behaves like an RS flip-flop, except when both J
and K are equal to 1. When both J and K are 1, the clock pulse
is transmitted through one AND gate only—the one whose
input is connected to the flip-flop output which is presently
equal to 1.
• Thus, if Q = 1, the output of the upper AND gate becomes 1
upon application of a clock pulse, and the flip-flop is cleared.
• If Q′ = 1, the output of the lower AND gate becomes a 1 and
the flip-flop is set. In either case, the output state of the flip-
flop is complemented.
T Flip-flop

• The T flip-flop is a single-input version of the JK flip-

flop.
• As shown in Fig., the T flip-flop is obtained from a JK
type if both inputs are tied together.
• The designation T comes from the ability of the flip-
flop to “toggle,” or change state.
• Regardless of the present state of the flip-flop, it
assumes the complement state when the clock pulse
occurs while input T is logic-1.
Triggering of Flip-flops

• The state of a flip-flop is switched by a momentary change in the

input signal. This momentary change is called a trigger and the
transition it causes is said to trigger the flip-flop.
• Asynchronous flip-flops, such as the basic circuits of Figs. 6-2 and
6-3, require an input trigger defined by a change of signal level.
• This level must be returned to its initial before a second trigger is
applied.
• Clocked flip-flops are triggered by pulses. A pulse starts from an
initial value of 0, goes momentarily to 1, and after a short time,
returns to its initial 0 value.
• The time interval from the application of the pulse until the
output transition occurs is a critical factor that needs further
investigation.
• A clock pulse may be either positive or negative.
• A positive clock source remains at 0 during the
interval between pulses and goes to 1 during the
occurrence of a pulse.
• The pulse goes through two signal transitions; from 0
to 1 and the return from 1 to 0.
• As shown in the below Fig. , the positive transition is
defined as the positive edge and the negative
transition as the negative edge.
Master-Slave Flip-Flop
• A master-slave flip-flop is constructed from two
separate flip-flops.
• One circuit serves as a master and the other as a
slave, and the overall circuit is referred to as a
master-stave flip-flop.
• The logic diagram of an RS master-slave flip-flop
consists of a master flip-flop, a slave flip-flop, and an
inverter.
• When clock pulse CP is 0, the output of the inverter is 1.
• Since the clock input of the slave is 1, the flip-flop is
enabled and output Q is equal to Y, while Q′ is equal to Y′.
• The master flip-flop is disabled because CP = 0. When the
pulse becomes 1, the information then at the external R and
S inputs is transmitted to the master flip-flop.
• The slave flip-flop, however, is isolated as long as the pulse
is at its 1 level, because the output of the inverter is 0.
• When the pulse returns to 0, the master flip-flop is isolated,
which prevents the external inputs from affecting it.
• The slave flip-flop then goes to the same state as the master
flip-flop.
• Assume that the flip-flop is in the clear state prior to
the occurrence of a pulse, so that Y = 0 and Q = 0.
• The input conditions are S = 1, R = 0, and the next
clock pulse should change the flip-flop to the set
state with Q = 1.
• During the pulse transition from 0 to 1, the master flip-flop is set
and changes Y to 1.
• The slave flip-flop is not affected because its CP input is 0. Since
the master flip-flop is an internal circuit, its change of state is not
noticeable in the outputs Q and Q′.
• When the pulse returns to 0, the information from the master is
allowed to pass through to the slave, making the external output
Q = 1.
• The external S input can be changed at the same time that the
pulse goes through its negative edge transition. This is because,
once the CP reaches 0, the master is disabled and its R and S
inputs have no influence until the next clock pulse occurs.
• Thus, in a master-slave flip-flop, it is possible to switch the
output of the flip-flop and its input information with the same
clock pulse.
• It must be realized that the S input could come from the output
of another master-slave flip-flop that was switched with the
same clock pulse.
 Clocked Master-Slave JK flip-flop

• Master-slave JK flip-flop constructed with NAND gates is

shown in Fig.
• It consists of two flip-flops; gates 1 through 4 form the
master flip-flop, and gates 5 through 8 form the slave flip-
flop.
• The information present at the J and K inputs is transmitted to the
master flip-flop on the positive edge of a clock pulse and is held
there until the negative edge of the clock pulse occurs, after which
it is allowed to pass through to the slave flip-flop.
• The clock input is normally 0, which keeps the outputs of gates 1
and 2 at the 1 level. This prevents the J and K inputs from affecting
the master flip-flop.
• The slave flip-flop is a clocked RS type, with the master flip-flop
supplying the inputs and the clock input being inverted by gate 9.
• When the clock is 0, the output of gate 9 is 1, so that output Q is
equal to Y. and Q′ is equal to Y′.
• When the positive edge of a clock pulse occurs, the master flip-flop
is affected and may switch states. The slave flip-flop is isolated as
long as the clock is at the 1 level, because the output of gate 9
provides a 1 to both inputs of the NAND basic flip-flop of gates 7
and 8.
• When the clock input returns to 0, the master flip-flop is isolated
from the J and K inputs and the slave flip-flop goes to the same
state as the master flip-flop.
Edge-Triggered Flip-Flop
• Another type of flip-flop that synchronizes the state
changes during a clock pulse transition is the edge-
triggered flip-flop.
• In this type of flip-flop, output transitions occur at a
specific level of the clock pulse.
• When the pulse input level exceeds this threshold level,
the inputs are locked out and the flip-flop is therefore
unresponsive to further changes in inputs until the
clock pulse returns to 0 and another pulse occurs.
• Some edge-triggered flip-flops cause a transition on the
positive edge of the pulse, and others cause a
transition on the negative edge of the pulse.
• When S = 0 and R = 1, the output
goes to the set state with Q = 1.
• When S = 1 and R = 0, the output
goes to the clear state with Q = 0.
Inputs S and R are determined from
the states of the other two basic
flip-flops.
• These two basic flip-flops respond
to the external inputs D (data) and
CP (clock pulse).
Direct Inputs
• Flip-flops available in IC packages sometimes provide
special inputs for setting or clearing the flip-flop
asynchronously. These inputs are usually called direct
preset and direct clear.
• They affect the flip-flop on a positive (or negative) value
of the input signal without the need for a clock pulse.
• These inputs are useful for bringing all flip-flops to an
initial state prior to their clocked operation.
• Ex: After power is turned on in a digital system, the states
or its flip-flops are indeterminate. A clear switch clears all
the flip-flops to an initial cleared state and a start switch
begins the system’s clocked operation. The clear switch
must clear all flip-flops asynchronously without the need
for a pulse.
• The clock or CP input has a circle under the small triangle
to indicate that the outputs change during the negative
transition of the pulse. (The absence of the small circle
would indicate a positive edge-triggered flip-flop.)
• The direct clear input also has a small circle to indicate
that, normally, this input must be maintained at 1.
• If the clear input is maintained at 0, the flip-flop remains
cleared, regardless of the other inputs or the clock pulse.