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    Unit-4 (STLD) Lecture2

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    Sahithi kairamkonda
    The document discusses different types of flip-flops including SR, D, JK, and T flip-flops. It provides details on their structure using NAND gates and their truth tables. A flip-flop is a basic digital memory circuit that has two states, 1 or 0. It is controlled by clock signals unlike a latch. The D flip-flop propagates the value of its input D to the output with the positive clock edge. The JK flip-flop can toggle its output. The T flip-flop has a single input T and toggles its output. Race around condition in a JK flip-flop occurs when both J and K are high, causing the output to toggle continuously

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    Unit-4 (STLD) Lecture2

    Uploaded by

    Sahithi kairamkonda
    29 views21 pages
    The document discusses different types of flip-flops including SR, D, JK, and T flip-flops. It provides details on their structure using NAND gates and their truth tables. A flip-flop is a basic digital memory circuit that has two states, 1 or 0. It is controlled by clock signals unlike a latch. The D flip-flop propagates the value of its input D to the output with the positive clock edge. The JK flip-flop can toggle its output. The T flip-flop has a single input T and toggles its output. Race around condition in a JK flip-flop occurs when both J and K are high, causing the output to toggle continuously

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    The document discusses different types of flip-flops including SR, D, JK, and T flip-flops. It provides details on their structure using NAND gates and their truth tables. A flip-flop is a basic digital memory circuit that has two states, 1 or 0. It is controlled by clock signals unlike a latch. The D flip-flop propagates the value of its input D to the output with the positive clock edge. The JK flip-flop can toggle its output. The T flip-flop has a single input T and toggles its output. Race around condition in a JK flip-flop occurs when both J and K are high, causing the output to toggle continuously

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    29 views21 pages

    Unit-4 (STLD) Lecture2

    Uploaded by

    Sahithi kairamkonda
    The document discusses different types of flip-flops including SR, D, JK, and T flip-flops. It provides details on their structure using NAND gates and their truth tables. A flip-flop is a basic digital memory circuit that has two states, 1 or 0. It is controlled by clock signals unlike a latch. The D flip-flop propagates the value of its input D to the output with the positive clock edge. The JK flip-flop can toggle its output. The T flip-flop has a single input T and toggles its output. Race around condition in a JK flip-flop occurs when both J and K are high, causing the output to toggle continuously

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    SWITCHING THEORY AND

    LOGIC DESIGN

    Lecture-2 UNIT-iv

    Basic flip-flops

    V. KUMARA SWAMY,
    BE(ECE), MTECH(DSCE), [Ph.D], MIEEE
    ASSOC.PROF & ASSOC.HoD
    Dept of ECE
    Contents Covered in the last class
    Classification
    of sequential circuits (Synchronous,
    Asynchronous Pulse mode, and Level mode with
    examples).
    Latches
    • S’R’ Latch.
    • SR Latch with Clock Signal.
    • Gated D-Latch.
    Contents to be Covered Today
    Basic flip-flops.
    • SR Flip-Flop
    • D- Flip-Flop
    • JK-Flip-Flop
    • T-Flip-Flop
    Memory Devices

    Latches A latch is a memory element whose


    excitation signals control the state of the device. A
    latch has two stages set and reset. Set stage sets the
    output to 1. Reset stage set the output to 0.
    Flip-flops A flip-flop is a memory device that has
    clock signals control the state of the device.
    FLIP-FLOPS
    The basic 1-bit digital memory circuit is known as a flip-flop. It
    can have two states either the 1 state or the 0 state.
    It is also known as a bistable multivibrator. Flip-flops can be
    obtained by using NAND or NOR gates.
    Q NORMAL OUTPUT

    INPUTS
    Q’ INVERTED OUTPUT

    BLOCK DIAGRAM OF A FLIP-FLOP


    0 0 n+1 n+1

    1 1 Qn Qn
    Qn Qn

    1 0 1

    0
    1 0
    0 1
    1
    1 0 n+1 n+1

    0 Qn Qn
    Qn Qn

    0 0 1
    1 0
    1

    0 1
    1 0
    1
    1 1
    n+1 n+1

    0 Qn Qn
    Qn Qn
    1 0 1
    1 0
    1 Prohibited

    1 0
    0 1
    1
    1
    1
    1

    1
    1

    1
    D-Flip Flop using NAND Gates
    1 0 1
    0
    1
    0 1
    Truth Table
    1 1 0
    Truth
    Table:
    D-Flip Flop using NAND Gates
    0 1 0
    1
    1
    1 1
    Truth Table
    0 0 1
    Truth
    Table:
    D FLIP-FLOP
    • Make S and R complements of each other
    –Eliminates 1s catching problem
    –Value of D just propagated to output of the flip-flop with
    PD.
    –D FF is most commonly used in registers, and memory
    devices.
    JK Flip Flop using NAND gates

    0 1 0
    0 1

    1
    1
    0 1 0 1
    1
    1

    0 0 1
    1
    1
    0 0 1
    1
    Clk J K Qn+1 Qn+1
    1 X X Qn Qn

    0 0 Qn Qn
    1
    1 0 0
    0
    1 0 1 0
    1 1 0
    0
    0
    1 1 0
    1

    1
    1
    0 1
    0
    1 1 1 Qn Qn
    T FLIP-FLOP

    With a slight modification of a J-K flip-flop, we can construct a new flip


    flop called the T-FLIPFLOP . If the two inputs J and K of a J-K flip-
    flop are tied together it is referred to as a T-flip-flop. Hence a T flip-flop
    has only one input T and two outputs Q and Q’. The name T flip-flop
    actually indicates the fact that the flip-flop has the ability to TOGGLE. It
    has actually only two states TOGGLE STATE and MEMORY STATE.
    T FLIP FLOP

    TRUTH TABLE
    What is meant by race around condition?

    •In JK Flip-Flop the output is feedback to the input,


    therefore change in the output results change in the input.
    •Due to this in the positive half of the clock pulse if J and
    K are both high then output toggles continuously as
    shown at points a,b,c,d and e in the below figure.
    •This condition is known as “Race Around Condition”, it
    must be avoided
    Thank you &
    Welcome to Queries

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