Confidential

AMBA Based System for High Speed

IP Validation
Yash Kothari
Intern, Cosmic R&D, Bangalore

Date: 20-11- 2013

 Agenda

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 Agenda

1. Development of a MicroBlaze based Soft System

2. Use of Standard AMBA Architecture for System Bus Communication

3. Use of PCI Express for High Speed IP Validation

4. Backward Compatibility with USB 2.0 IP Validation Interface

5. Development of Software Application for PCIe and UART as IO Device

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 Background and Significance of the Project

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 Background on the Project

What is a System?
• A set of interacting or interdependent components forming an
integrated whole “Functional Block”
• Eg: Personal Computer, Smart Phones, Tablets, Ipod, etc…
• Features :
• Comprises of a Processor, multiple sub - systems
• Interconnect Bus - PCIe, AXI, PLB
• Comprises of an Operating System

What is a Sub - System?

• Miniature version of a system
• Limited Functionality
• No OS (Linux can be embedded in some subsystems if reqd.)

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 Background on the Project

A Typical PCI Express based Computer System

NOTE: Image taken from the Book - PCI Express System Architecture, Ravi Budruk et. al., Mindshare Inc.

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 Significance of the Project
 Compliance with AMBA Architecture -
• AMBA Architecture is a registered trademark of ARM and is an open standard, on-chip
interconnect specification for the connection and management of functional blocks in a System-
on-Chip (SoC)
• AMBA Architecture has gone far beyond microcontroller devices, and is now widely used on a
range of ASIC and SoC parts including application processors used in modern portable mobile
devices like smart phones

 Development of a Generic System -

• Pre & Post - Silicon IP Validation
• Availability of various modules like UART, GPIO, IIC, DDR, DMAC, PCI Express etc.
• Availability of various types of AMBA DUT channels (AXI, AHB, APB) for Interfacing
• Backward Integration with the existing USB 2.0 Interface

 System can be used for the verification of any AMBA compliant IP with the
flexibility of choosing from a wide set of modules and devices.

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 System Design: Functionality of each Module &
Design Flow

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 Development of the Base System - Completed

From PC

JTAG

MicroBlaze

AXI Interconnect

Boot
RAM

- AXI Master Interface

- AXI Slave Interface

9 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 MicroBlaze & Boot RAM

 MicroBlaze -
• Soft Processor Core from Xilinx
• Central Processor for the System
• Controls the operations of the Complete System
• Interrupt Processing Available
• Configured through JTAG Interface

 Boot RAM -
• System Boot Memory
• Contains the Boot up Information ( Instruction/ Command Set) of the System
• Application C Code (containing the Boot Up Info) written by the User is converted to a binary
format and loaded onto the Boot RAM

10 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 AMBA Architecture & AXI Interconnect

 AMBA Architecture -
• Reason: It facilitates the development of multi-processor designs with large numbers of
controllers and peripherals.
• Advantages:
1. Technology Independent
2. Encourages Modular System Design to improve processor independence
3. Supports High Performance and low power on chip communication

 AXI Interconnect -
• Uses AXI4 Bus Protocol of the AMBA-4 Architecture
• Central System Bus
• Connects MicroBlaze with other Modules of the System

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 Addition of the UART Module - Completed

From PC

JTAG

MicroBlaze

AXI Interconnect

Boot
UART
RAM
COM
Port
To PC

- AXI Master Interface

- AXI Slave Interface

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 Universal Asynchronous Reciever & Transmitter: UART

 UART -
• Piece of Computer Hardware - Translates Data between Serial & Parallel Form
• Used in Conjunction with RS 232 (Communication Standard)
• 3 line Interface on Zeus Board - Rx, Tx and Gnd
• Connected to COM Port on PC
• Application Software “Hypertrm” used to Display the UART Data on PC

13 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Addition of GPIO Module - Completed

From PC

JTAG

MicroBlaze

AXI Interconnect

Boot
UART GPIO
RAM
COM
Port
To PC

- AXI Master Interface

- AXI Slave Interface

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 General Purpose Input & Output: GPIO

 GPIO -
• System comprises of 4 different IO Devices -
1. LED’s: O/P Device

2. Switch: I/P Device

3. Push Button: I/P Device

4. Generic GPIO Bus: Bi-directional IO Bus

• All GPIO Interfaces port mapped to resp. devices on USB 3.0 Extension Board

15 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Addition of I2C Module - Completed

From PC

JTAG

MicroBlaze

AXI Interconnect

Boot
UART GPIO I2C
RAM
COM
Port
To PC

- AXI Master Interface

- AXI Slave Interface

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 Inter - Integrated Circuit: I2C

 IIC / I2C -
• A multi master serial single-ended Computer Bus
• Uses only two bi-directional open - drain lines - SDA and SCL

• System Comprises of two I2C Devices - Master & Slave

• I2C Master must for Slave to function properly

• Use to Configure Peripheral Devices like Camera in Mobiles

• Use for Data Transfer in EEPROM

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 Addition of Timer Module - Completed

From PC

JTAG

MicroBlaze

AXI Interconnect

Boot
UART GPIO I2C Timer
RAM
COM
Port
To PC

- AXI Master Interface

- AXI Slave Interface

18 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Addition of the Interrupt Controller - Completed

From PC

JTAG

MicroBlaze

AXI Interconnect

Boot INTR
UART GPIO I2C Timer
RAM Cntrl
COM
Port
To PC

- AXI Master Interface

- AXI Slave Interface

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 Timer & INTR Controller

 Timer -
• used to add accurate Time Delays or Time Intervals before a Service Routine
• Various Configuration Modes available – Count Up / Count Down/ Repeated Count
• INTR feature enabled in Hardware Design
• INT Enable / Disable from the Software Code

 INTR Controller -
• Controller for handling System Interrupts
• Modules connected to INTR Cntrl in Hardware Design - GPIO, UART, Timer, DMAC, DDR
• INTR for these modules should be enabled in the Software Code

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 Addition of the DDR2 Controller Module - Completed

From PC

JTAG

MicroBlaze DDR2

AXI Interconnect

Boot INTR
UART GPIO I2C Timer
RAM Cntrl
COM
Port
To PC

- AXI Master Interface

- AXI Slave Interface

21 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 DDR2 Controller

 DDR2 Controller -
• DDR (Double Data Rate) memory controllers are used to drive DDR SDRAM
• Data is transferred on the rising and falling edges of the memory clock of the system

• 16 bit DDR2 Controller Implemented

• System Tested with the DDR2 SDRAM available on Zeus Board
• Data Transfer speed - 500 Mbps
• Tested 32 bit burst Memory Read/ Write

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 Addition of the DMA Cntrl & Sys RAM Module - Completed

From PC

JTAG

MicroBlaze DMAC DDR2

AXI Interconnect

Boot Sys INTR

UART GPIO I2C Timer
RAM RAM Cntrl
COM
Port
To PC

- AXI Master Interface

- AXI Slave Interface

23 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Direct Memory Access Controller and System RAM

 DMA Controller -
• Processor can only do single Read/Write
• Burst Read/ Write from/to the System

• Configured in Simple Mode

• Requires Source Address, Destination Address and Bytes to Transfer
• Processor in Idle State - Free to perform other operations

 System RAM -
• RAM block for data storage

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 Addition of AMBA DUT Interface - Completed

From PC

JTAG

MicroBlaze DMAC DDR2

AXI Interconnect

Boot Sys INTR

UART GPIO I2C Timer
RAM RAM Cntrl AXI2AHB AXI2APB
COM
Port
To PC

AHB APB AXI

- AXI Master Interface
- AXI Slave Interface |------------ DUT Interface
------------|

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 AMBA DUT Interface

 AMBA DUT Interface -

• AMBA - 4 Compliant IP can be connected
• Supported DUT Interfaces -
1. AXI DUT Interface
 Both AXI Master and Slave DUT Interface Lines available

2. AHB DUT Interface

 AHB Slave DUT Interface lines available

3. APB DUT Interface

 APB Slave DUT Interface lines available

• Any other DUT not supported directly

26 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Addition of GPIF2AXI Interface - On Hold

From PC GPIF From PC

USB 2.0
CNTRL
JTAG

MicroBlaze DMAC GPIF2AXI DDR2

AXI Interconnect

Boot Sys INTR

UART GPIO I2C Timer
RAM RAM Cntrl AXI2AHB AXI2APB
COM
Port
To PC

AHB APB AXI

- AXI Master Interface
- AXI Slave Interface |------------ DUT Interface
------------|

27 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 GPIF2AXI Module

 GPIF Interface -
• Needed for IP Configuration & Validation using existing USB 2.0 Interface
• GPIF lines Port mapped to USB Controller’s Interface
• USB 3.0 Interface can also be connected thus enabling Higher Data Transfer Speeds

 GPIF2AXI Module -
• Converts GPIF Signals to AXI Signals
• Required to connect the GPIF Interface to MicroBlaze and the remaining System

28 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Addition of the PCIe Module - In Progress

From PC From PC GPIF From PC

USB 2.0
CNTRL
JTAG PCIe

MicroBlaze DMAC PCIe GPIF2AXI DDR2

AXI Interconnect

Boot Sys INTR

UART GPIO I2C Timer
RAM RAM Cntrl AXI2AHB AXI2APB
COM
Port
To PC

AHB APB AXI

- AXI Master Interface
- AXI Slave Interface |------------ DUT Interface
------------|

29 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 PCI Express Endpoint

 PCI Express -
• High Speed Serial Computer Bus
• Operates as a Primary motherboard-level interconnect in modern Computers

 PCIe Endpoint Device -

• High Speed Data Transfer from PC
• System Design supports a 1x PCIe Communication Channel
• Replacement for existing USB 2.0 Interface

30 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Complete System Design – Bock Diagram

From PC From PC GPIF From PC

USB 2.0
CNTRL
JTAG PCIe

MicroBlaze DMAC PCIe GPIF2AXI DDR2

AXI Interconnect

Boot Sys INTR

UART GPIO I2C Timer
RAM RAM Cntrl AXI2AHB AXI2APB
COM
Port
To PC

AHB APB AXI

- AXI Master Interface
- AXI Slave Interface |------------ DUT Interface
------------|

31 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Design Flow

Create the Base System using Define User Constraints, Port

BSB in XPS and Address Mapping

Export to ISIM Add other Std IP cores and

(Check Simulations) User IP’s (if reqd.)

Generate Test Generate Implement the Design

Case C code HDL files and Synthesize Bit file

Use XMD to Validate Export Bit file

Generate elf file the Design to SDK

33 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Application C Code Example
GPIO Memory Read
SWITCH
Algorithm -

• Read
• Read
Stored
Switch
Value
Value • Write to
• Store in
Interconn
Memory
ect

UART

• Display the
Read Value
on UART

34 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Application C Code Example

Implementation of the Code into Boot RAM -

A
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35 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Snapshot of the XMD Console launched from EDK

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 Snapshot of the “Hypertrm” Window

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 Application of AMBA based System

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 CSI DSI System
From PC
JTAG

FPGA
MB_Irq
MicroBlaze - AXI Master Interface
- AXI Slave Interface

AXI Interconnect

Boot GPIO INTR Controller I2C AXI2APB

RAM

UART
Intr CSI Intr
CSI to
DPHY TIF CSI DSI DSI
UART Interface Controller Controller
Bridge
DSI Intr

To COM Port DPHY

of PC LCD Panel

DPHY TX
DPHY RX

Camera
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 Advantages of AMBA based System

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 Limitations of Existing Mechanism

1. No Interrupt Mechanism

2. No Detection Mechanism for System Busy

3. System is always considered a Slave, thus cannot initiate a transaction

4. Separate driver/ application required for using FastChar

41 © 2013 Cadence Design Systems, Inc. Cadence confidential. Internal use only.
 Advantages of AMBA based System

1. Availability of Interrupt Controller

2. If System is busy, it will send Busy or Hold Signal.

3. System can act as Master/Slave.

4. Using UART as User IO Interface doesn’t need any driver/ application

5. High Speed IP Validation using PCI Express and USB 3.0

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 Advantages of AMBA based System (Contd.)

6. System is backward Integrated with the existing USB 2.0 Interface

7. Contains various Test Cases to choose from for various Module and DUT validation.

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 Questions?

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 Thank You!

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