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 Lecture 11: Sequential
Logic Latches & Flip-
flops
 Introduction
 Memory Elements
 Pulse-Triggered Latch
 S-R Latch
 Gated S-R Latch
 Gated D Latch
 Edge-Triggered Flip-
flops
 S-R Flip-flop
 D Flip-flop
 J-K Flip-flop
 T Flip-flop
 Asynchronous Inputs
Introduction
 A sequential circuit consists of a feedback path,
and employs some memory elements.
Combinational
output Memory
s outputs

Combinational Memory
logic elements

External inputs

Sequential circuit = Combinational logic + Memory

Elements
Introduction
 There are two types of sequential circuits:
 synchronous: outputs change only at specific time
 asynchronous: outputs change at any time

 Multivibrator: a class of sequential circuits.

They can be:
 bistable (2 stable states)
 monostable or one-shot (1 stable state)
 astable (no stable state)

 Bistable logic devices: latches and flip-flops.

 Latches and flip-flops differ in the method
used for changing their state.
Memory
 Memory element: a device which can
Elements
remember value indefinitely, or change value
on command from its inputs.

Memor Q
comman y stored
d eleme value
nt
 Characteristic
table: Comman Q(t) Q(t+1)
d (at Q(t): current state
time t)
Set X 1 Q(t+1) or Q+: next
Reset X 0 state
Memorise 0 0
/ No 1 1
Change
Memory
 Memory element with clock. Flip-flops are
Elements
memory elements that change state on
clock signals.
Memor Q
comman y stored
d eleme value
nt
clock

 Clock is usually a
square wave.
Positive
pulses

Positive Negative
edges edges
Memory
 Two types of triggering/activation:
Elements
 pulse-triggered
 edge-triggered

 Pulse-triggered
 latches
 ON = 1, OFF = 0

 Edge-triggered
 flip-flops
 positive edge-triggered (ON = from 0 to 1; OFF =
other time)
 negative edge-triggered (ON = from 1 to 0; OFF =
other time)
S-R
 Complementary outputs: Q and Q'.
Latch
 When Q is HIGH, the latch is in SET state.
 When Q is LOW, the latch is in RESET state.
 For active-HIGH input S-R latch (also known as
NOR gate latch),
R=HIGH (and S=LOW) ->
RESET state S=HIGH (and
R=LOW)-> SET
state both inputs LOW ->no
change
both inputs HIGH ->Q and Q' both
LOW (invalid)!
Block Diagram:

Circuit Diagram:
S-R
 For active-LOW input S'-R' latch (also known as
LatchNAND gate latch),
R'=LOW (and S'=HIGH) - RESET
state S'=LOW (and R'=HIGH) - SET
state both inputs HIGH - no
change
both inputs LOW - Q and Q' both
HIGH (invalid)!
 Drawback of S-R latch: invalid condition
exists and must be avoided.
S-R
 Characteristics table for active-high input S-
LatchR latch:
S R Q Q'
0 0 NC NC No change. Latch
remained in present state. S Q
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET. R Q'
1 1 0 0 Invalid condition.

 Characteristics table for active-low input S'-

R' latch:
S' R' Q Q'
1 1 NC NC No change. Latch
remained in present state. S Q
0 1 1 0 Latch SET.
1 0 0 1 Latch RESET. R Q'
0 0 1 1 Invalid condition.
S-R
 Active-HIGH input S-R
Latchlatch
10 100 R S R Q Q'
Q 11000 1 0 1 0 initial
0 0 1 0 (afer S=1,
R=0)
0 1 0 1
Q' 00110
10 0 0 1 S 0 0 0 1 (after S=0,
R=1)
1 1 0 0 invalid!
 Active-LOW input S’-R’
S' latch Q
S' R' Q Q'
R' Q'
S' 1 0 0 1 initial
Q 1 1 0 1 (afer S'=1,
R'=0)
0 1 1 0
Q' 1 1 1 0 (after S'=0,
R'
R'=1)
0 0 1 1 invalid!
Gated S-R
 S-R latch + enable input (EN) and 2 NAND
Latchgates 
gated S-R latch.
S
Q S Q
EN EN
Q' R Q'
R
Gated S-R
 Outputs change (if necessary) only when EN is
LatchHIGH.
 Under what condition does the invalid state
occur?
 Characteristic table:
EN=1
Q(t) S R Q(t+1) S R Q(t+1)
0 0 0 0 0 0 Q(t) No change
0 0 1 0 0 1 0 Reset
0 1 0 1
1 0 1 Set
0 1 1 indeterminate
1 1 indeterminate
1 0 0 1
1 0 1 0
Q(t+1) = S +
1 1 0 1
1 1 1 indeterminate
R'.Q
S.R = 0
Gated D
 Make R input equal to S'  gated D latch.
Latch
 D latch eliminates the undesirable condition of
invalid state in the S-R latch.

D
Q D Q
EN EN
Q' Q'
Gated D
 When EN is HIGH,
Latch D=HIGH  latch is SET
 D=LOW  latch is RESET

 Hence when EN is HIGH, Q ‘follows’ the D

(data) input.
 Characteristic table:
EN D Q(t+1)
1 0 0 Reset
1 1 1 Set
0 X Q(t) No change

When EN=1, Q(t+1) =

D
Latch Circuits: Not
 Latch circuits are not suitable in
Suitable
synchronous logic circuits.
 When the enable signal is active, the excitation
inputs are gated directly to the output Q.Thus,
any change in the excitation input
immediately causes a change in the latch
output.
 The problem is solved by using a special
timing control signal called a clock to
restrict the times at which the states of
the memory elements may change.
 This leads us to the edge-triggered memory
elements called flip-flops.
Edge-Triggered Flip-
 Flip-flops: synchronous bistable devices
flops
 Output changes state at a specified
point on a triggering input called the
clock.
 Change state either at the positive edge (rising
edge) or at the negative edge (falling edge) of
the clock signal.

Clock signal
Positive Negative
edges edges
Edge-Triggered Flip-
 S-R, D and J-K edge-triggered flip-flops. Note
flopsthe “>” symbol at the clock input.
S Q D Q J Q
C C C
R Q' Q' K Q'

Positive edge-triggered flip-

flops

S Q D Q J Q
C C C
R Q' Q' K Q'

Negative edge-triggered flip-

flops
S-R Flip-
 S-R flip-flop: on the triggering edge of the clock
flop pulse,
 S=HIGH (and R=LOW) 🢧 SET state
 R=HIGH (and S=LOW) 🢧 RESET state
 both inputs LOW 🢧 no change
 both inputs HIGH 🢧 invalid
 Characteristic table of positive edge-triggered
S-R flip- flop:
S R CLK Q(t+1) Comments
0 0 X Q(t) No change
0 1  0 Reset
1 0  1 Set
1 1  ? Invalid

X = irrelevant (“don’t care”)

 = clock transition LOW to HIGH
S-R Flip-
 It comprises 3 parts:
flop a basic NAND latch
 a pulse-steering circuit
 a pulse transition detector (or edge detector) circuit

 The pulse transition detector detects a rising

(or falling) edge and produces a very short-
duration spike.
S-R Flip-
flopThe pulse transition
detector. S
Q
Pulse
CLK transition
detector
Q'
R

CLK' CLK'
CLK CLK* CLK CLK*

CLK CLK

CLK' CLK'

CLK* CLK*

Positive-going Negative-going
transition transition
(rising edge) (falling edge)
D Flip-
 D flip-flop: single input D (data)
flop D=HIGH 🢧 SET state
 D=LOW 🢧 RESET state

 Q follows D at the clock edge.

 Convert S-R flip-flop into a D flip-flop: add an
inverter.
D D CLK Q(t+1) Comments
S Q
1  1 Set
C
0  0 Reset
CLK R Q'
 = clock transition LOW to HIGH
A positive edge-triggered D
flip-
flop formed with an S-R flip-
flop.
D Flip-
 Application: Parallel data transfer.
flop To transfer logic-circuit outputs X, Y, Z to flip-
flops Q1, Q2 and Q3 for storage.
D Q Q1 = X*

CLK
Q'
X
Combinational Y D Q Q2 = Y*
logic circuit
Z CLK
Q'

D Q Q3 = Z*
Transfer CLK
Q'

* After occurrence of negative-going

transition
J-K Flip-
 J-K flip-flop: Q and Q' are fed back to the
flop pulse- steering NAND gates.
 No invalid state.
 Include a toggle state.
 J=HIGH (and K=LOW) 🢧 SET state
 K=HIGH (and J=LOW) 🢧 RESET state
 both inputs LOW 🢧 no change
 both inputs HIGH 🢧 toggle
J-K Flip-
 J-K flip-
flop flop.
J
Q
Pulse
CLK transition
detector
Q'
K

 Characteristic Q J K Q(t+1)
table.
J K CLK Q(t+1) Comments 0 0 0 0
0 0  Q(t) No change 0 0 1 0
0 1  0 Reset 0 1 0 1
1 0  1 Set 0 1 1 1
1 1  Q(t)' Toggle 1 0 0 1
1 0 1 0
1 1 0 1
Q(t+1) = J.Q' +
1 1 1 0
K'.Q
T Flip-
 T flip-flop: single-input version of the J-K
flop flip flop, formed by tying both inputs
together.
T
Q T J
Pulse Q
CLK transition CLK C
detector
Q' K Q'

 Characteristic
table.
T CLK Q(t+1) Comments Q T Q(t+1)
0  Q(t) No 0 0 0
change 0 1 1
1 
Q(t)' Toggle 1 0 1
1 1 0
Q(t+1) = T.Q' +
T'.Q
T Flip-
 Application: Frequency
flop division.
High

High J QA QB
Q J J
CLK High C CLK C C

K K K

CLK CLK

Q QA

QB

Divide clock frequency by 2. Divide clock frequency

by 4.

 Application: Counter (to be covered in

Lecture 13.)
Asynchronous
 S-R, D and J-K inputs are synchronous inputs, as
Inputs
data on these inputs are transferred to the flip-
flop’s output only on the triggered edge of the
clock pulse.
 Asynchronous inputs affect the state of the
flip-flop independent of the clock; example:
preset (PRE) and clear (CLR) [or direct set (SD)
and direct reset (RD)]
 When PRE=HIGH, Q is immediately set to
HIGH.
 When CLR=HIGH, Q is immediately cleared to
LOW.
 Flip-flop in normal operation mode when both
PRE
and CLR are LOW.
Asynchronous
 A J-K flip-flop with active-LOW preset and clear
Inputs
inputs. PRE
PRE

J
Q
J Q Pulse
C transition
CLK
detector
K Q' Q'
K

CLR CLR

CLK

PRE

CLR
Q
J=K= Preset Toggle Clear
HIGH
Assignment

1. Explain Flip Flops and its types.

2. Explain truth table of J-K flip flop.
3. Explain S-R flip flop with the help of
circuit.
4. Differentiate between D and T flip flop.