Digital Logic Design

-Latches and Flip Flops-

 Combinational vs Sequential Logic

In combinational logic, the outputs depends only on

inputs.
In a sequential logic, the outputs depend on the
present inputs, as well as the past behavior of the
circuit.
Using past behavior means that the sequential circuits
have ‘memory’.

Instr: Dr. Awais M. Kamboh. 2

 Sequential Logic

In a sequential logic, the outputs depend on the present inputs, as

well as the past behavior of the circuit.
Example: Counter: The output increases a 1 when input is 1.
If the current output of a counter is 5, then giving a 1 on the
input A makes it 6. Bringing A back to 0 doesn’t change the
output. Making A equal to 1 again changes the output to 7.
It means the new output depends on what the previous output
was. This is memory.

Instr: Dr. Awais M. Kamboh. 3

 Latches – SR Latch
• A latch is a temporary storage device.
• A storage device, also called a ‘memory’, can ‘hold’ the output
value 0 or 1 even when the input changes.
• The output can be a stable 0 or a stable 1, thus a latch has two
stable states. It is called bistable.
• The S-R (Set-Reset) latch is the most basic type.

R
Q

Q
S

NOR Active-HIGH Latch

Instr: Dr. Awais M. Kamboh. 4
 Latches – SR Latch

• When the output of first gate becomes the input of second gate
and vice versa, this is called cross-coupling.
• The S-R (Set-Reset) latch can be constructed from NOR gates
or NAND gates.
• With NOR gates, the latch responds to active-HIGH inputs
• With NAND gates, it responds to active-LOW inputs.

R S
Q Q

Q Q
S R

NOR Active-HIGH Latch NAND Active-LOW Latch

Instr: Dr. Awais M. Kamboh. 5

 Latches – SR Latch

The active-HIGH S-R latch is in a stable (latched) condition

when both inputs are LOW.

Assume the latch is initially RESET (Q = 0) 0 R 01

Q
and the inputs are at their inactive level (0).
Latch
To SET the latch (Q = 1), a momentary initially
HIGH signal is applied to the S input while RESET
10
Q
the R remains LOW. 0 S

0 10
R
To RESET the latch (Q = 0), a momentary Q
HIGH signal is applied to the R input while Latch
the S remains LOW. initially
SET
01
Q
0 S

Instr: Dr. Awais M. Kamboh. 6

 Latches – SR Latch

Inputs Outputs R
Q
S R Initial Initial Next Next
Q Q’ Q Q’
0 0 0 1 0 1
Q
0 0 1 0 1 0 S
1 0 0 1 1 0
1 0 1 0 1 0 S R Q(t+1) Remarks
0 1 0 1 0 1 No Change
0 0 Q(t)
0 1 1 0 0 1 (HOLD)
1 1 0 1 Invalid Invalid 1 0 1 SET
0 1 0 RESET
1 1 1 0 Invalid Invalid
1 1 -- Invalid

• Q(t) means initial/current value of Q.

• Q(t+1) means the next value of Q.
Instr: Dr. Awais M. Kamboh. 7
 Latches – D Latch

The D latch is a variation of the S-R latch but combines the S

and R inputs into a single D input as shown:

R
D Q

EN

S Q

A simple rule for the D latch is:

When Enable is active, Q is connected to D
When Enable is inactive, Q holds its value
Instr: Dr. Awais M. Kamboh. 8
 Latches – D Latch

The truth table for the D latch summarizes its operation. If EN

is LOW, then there is no change in the output, and it is latched.

Inputs Outputs Remarks

D EN Q(t+1) Q’(t+1)
0 1 0 1 RESET
1 1 1 0 SET
X 0 Q(t) Q’(t) No Change(HOLD)

Q(t) means the initial value of Q

The output of the latch changes for as long as the level of EN
is active.

Instr: Dr. Awais M. Kamboh. 9

 Latches – D Latch

D Q

Determine the Q output for the EN

D latch, given the inputs shown. Q

EN

Notice that the Enable is not active during these times, so

the output is latched.

Instr: Dr. Awais M. Kamboh. 10

 Level vs Edge

The EN input has two defined levels, active and inactive.

However, the moment when EN changes from one level to another
is called an edge.
When the EN changes from the lower level to the higher level, it is
called a positive edge, represented by an upward arrow.
When the EN changes from the higher level to the lower level, it is
• called a negative edge, represented by a downward arrow.

Positive Edge

Negative Edge

Instr: Dr. Awais M. Kamboh. 11

 Level vs Edge Triggering

When the output changes, it is called triggering.

In a latch, the output can change as long as the level of EN is active.
Thus a latch is called a level-triggered device,
In a flip-flop the output can change only at the moment when EN
changes from inactive to active level. Thus a flip-flop is called an
edge-triggered device.

Instr: Dr. Awais M. Kamboh. 12

 D – Flip Flop

A flip-flop differs from a latch in the manner it changes

states/outputs.
A flip-flop is a clocked device which works on clock-edge.

Positive-edge triggered D flip-flop shows an up arrow,

Negative-edge triggered D flip-flop shows a down arrow.

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

(a) Positive-edge triggered (b) Negative-edge triggered

Q(t+1) = D
Instr: Dr. Awais M. Kamboh. 13
 D – Flip Flop

Positive-edge triggered D flip-flop shows an up arrow,

Negative-edge triggered D flip-flop shows a down arrow.

Inputs Outputs Inputs Outputs

D CLK Q Q Comments D CLK Q Q Comments
1 1 0 SET 1 1 0 SET
0 0 1 RESET 0 0 1 RESET

(a) Positive-edge triggered (b) Negative-edge triggered

D Q D Q

C C

Notch Q Q
indicates
clock edge (a) Positive edge-triggered (b) Negative edge-triggered

Instr: Dr. Awais M. Kamboh. 14

 D – Flip Flop (Positive Edge Triggered)

Q(t+1) = D

Instr: Dr. Awais M. Kamboh. 15

 T - Flip Flop

Output Q is toggled/inverted when T=1 and no change if T=0

Q(t+1) = TQ’(t) + T’Q(t)

T CLK Q(t+1)
0 Q(t) No Change
1 Q’(t) Toggle

Instr: Dr. Awais M. Kamboh. 16

 T – Flip Flop (Positive Edge Triggered)

Q(t+1) = TQ’(t) + T’Q(t)

Instr: Dr. Awais M. Kamboh. 17

 JK – Flip Flop
A J-K flip-flop has one clock input and two data inputs, J and K.
On the active clock edge (in this case, the rising/positive edge).
If both J and K = 0, outputs Q Q’ do not change. (Same as SR Latch)
If J=1 and K = 0, outputs change to Q=1 Q’=0 (SET) (Same as SR Latch)
If J=0 and K = 1, outputs change to Q=0 Q’=1 (RESET) (Same as SR Latch)
If both J and K = 1, output Q Q’ changes states (toggles) (Same as T Flip-flop)

Q(t+1) = JQ’(t) + K’Q(t)

Instr: Dr. Awais M. Kamboh. 18

 JK – Flip Flop
Input Initial State Output Remarks
Q(t+1) = JQ’+K’Q
J K Q Q’ Q Q’
0 0 0 1 0 1 No Change Q
J
0 0 1 0 1 0 No Change
0 1 0 1 0 1 Reset CLK
0 1 1 0 0 1 Reset
1 0 0 1 1 0 Set K Q
1 0 1 0 1 0 Set
1 1 0 1 1 0 Toggle
1 1 1 0 0 1 Toggle

J K CLK Q(t+1)
0 0 Q(t) No Change
0 1 0 Reset
Characteristic Table of 1 0 1 Set
JK Flip Flop
1 1 Q’(t) Toggle

Instr: Dr. Awais M. Kamboh. 19

 JK – Flip Flop Q
J

CLK

Determine the Q output for the J-K K Q

flip-flop, given the inputs shown.

J K Q(t+1)
0 0 Q(t) No Change
Q(t+1) = JQ’(t) + K’Q(t)
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Toggle

CLK

Instr: Dr. Awais M. Kamboh. 20

 JK – Flip Flop Q
J

CLK

Determine the Q output for the J-K K Q

flip-flop, given the inputs shown.

J K Q(t+1)
0 0 Q(t) No Change
Q(t+1) = JQ’(t) + K’Q(t)
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Toggle

CLK

Instr: Dr. Awais M. Kamboh. 21