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memory-design

Here are 6 public repositories matching this topic...

aieask / mdw21

Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis

memory ieee analog-design circuit-design sram-cell memory-design sram-memories

Updated Dec 9, 2022
AGS Script

akashlevy / pyxbar

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

python generator simulation waveform nvm spice circuit testbench netlist hspice verilog-a rram memory-design

Updated Jan 22, 2020
SourcePawn

AhmedIssa11 / Compiler-Design

csharp compiler-design lexical-analyzer semantic-analyzer syntax-analyzer memory-design

Updated Sep 3, 2022
C#

AkhilRai28 / Single-Port-RAM

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

fpga ram hardware verilog synchronous testbench digital-circuits hardware-description-language single-port fpga-programming memory-design

Updated Aug 24, 2024
Verilog

jtsimons / DRAMC

Behavioral architecture of a read/write cycle controller for a DRAM chip.

fpga vhdl tcl dram digital-design memory-controller memory-design

Updated May 26, 2023
VHDL

Pranavh-2004 / 64KB_RAM_iverilog

PESU Sem 3: Mini project for Digital Design and Computer Organization

ram verilog hdl modular-design memory-design digital-design-and-computer-organization

Updated Nov 17, 2024
Verilog

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