Chapter 7

Low-Power Testing

EE141 System-on-Chip Test Architectures

Ch. 7 Low-Power Testing - P. 1

What is this chapter about?

Introduce

the various aspects of lowpower testing on

Issues arising from excessive test power Structural and algorithmic solutions proposed to alleviate the low-power test pro lems

Focus

EE141 System-on-Chip Test Architectures

Ch. 7 Low-Power Testing - P. 2

Outline
1! Introduction "! Energ# and power modeling $! Test power issues 4! Low-power scan testing %! Low-power &IST '! Low-power test data compression (! Summar# and conclusion

EE141 System-on-Chip Test Architectures

Ch. 7 Low-Power Testing - P. 3

1. Introduction

Test in the past - )igh Fault *overage

Short Test Time Small Test +ata ,olume Low Test +evelopment Efforts Low area overhead

Test from now -

. Low-Power Test High Test Quality /e!g!0 high small-dela# detection capa ilit#1

EE141 System-on-Chip Test Architectures

Ch. 7 Low-Power Testing - P. 4

1. Introduction
Power dissipation in test mode is much higher than during functional mode

The circuit is highl# stressed 2o correlation etween consecutive test vectors Test vectors ignore functional constraints +FT circuitr# is intensivel# used Parallel testing is often used for efficienc# Low-power functional features /e!g!0 gated cloc31 often disa led during test
Ch. 7 Low-Power Testing - P. 5

EE141 System-on-Chip Test Architectures

1. Introduction
Industry generally resorts to ad-hoc solutions:
4ver si5ing power rails 4ver si5ing pac3ages and use of cooling s#stems Test with reduced operation fre6uenc# Partitioning and appropriate test planning

Costly or longer test time

EE141 System-on-Chip Test Architectures

Ch. 7 Low-Power Testing - P.

2. Energy and Power Modeling

Power dissipation in *74S I*s8

Static power8 power consumed when the circuit is idle /lea3age power1 +#namic power8 power consumed when the circuit is switching its state
*harging /9-118 : of energ# dissipated as heat

P
Vdd

+ischarging /1-918 energ# dissipated as heat CL Pdyn = CL.Vdd2.N01.1/T Pdyn = .CL.Vdd2.N.1/T

Ch. 7 Low-Power Testing - P. 7
7

N
EE141 System-on-Chip Test Architectures

2. Energy and Power Modeling

Energy ; total switching activit# generated during test
has

impact on the atter# lifetime during power up or periodic self-test of atter# operated devices

Average Power ; Energ# < Test time

has impact on the thermal load of the device

Peak Power ; )ighest value of instantaneous power

determines the thermal and electrical limits of components and the s#stem pac3aging re6uirements

EE141 System-on-Chip Test Architectures

Ch. 7 Low-Power Testing - P. !

2. Energy and Power Modeling

Energ# consumed after application of /,3-10,31

E,3 ; : ! c9!,"++ ! i si/31 ! Fi

Total energ# consumed during test application

ETotal ; : ! c9!,"++ ! 3 i si/31 ! Fi

=verage power consumed during the test session

P=,E>=?E ; ETotal < / LengthTest ! T 1

Pea3 power consumed during the test session

PPE=@ ; max3 Pinst/,31 ; max3 / E,3 < tsmall 1
9

EE141 System-on-Chip Test Architectures

Ch. 7 Low-Power Testing - P. "

2. Energy and Power Modeling

Test power acting parameters

Switching =ctivit#

has impact on the energ#0 average power and pea3 power

Test Fre6uenc#

has impact on the average power

Test Length

has impact on the energ#

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2. Energy and Power Modeling

Test power contri utors

*om inational Toggling

switching activit# in the com inational part of the circuit

Se6uential Toggling

switching activit# in the flip-flops

*loc3 Toggling

switching activit# in the cloc3 tree feeding the circuit

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11

. !est Power Issues

Thermal effects

)eat produced during the functioning of a circuit is proportional to the dissipated power /Aoule effect1 and is responsi le for die temperature increase Too high temperature can provo3e irreversi le structural degradations /premature destruction1 Too high temperature ma# affect circuit performance or can have an impact on the I*s relia ilit# /corrosion0 electro-migration0 hot-carrier-induced defects0 dielectric rea3down0 .1
12

EE141 System-on-Chip Test Architectures

Ch. 7 Low-Power Testing - P. 12

. !est Power Issues

2oise phenomena

Power suppl# noise L/di<dt1 due to current variations through inductive connections /pro es for wafer testing0 pins for pac3aged circuits1 B?round ounceC or B,oltage surge<droopC - ma# change the rise<fall times of some signals in the circuit I> drop /resistive effect1 and crosstal3 /capacitive effects1 D similar effects

?ood dies fail the test - manufacturing #ield loss /over3ill1

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". #ow$Power %can !esting $ &asics

Slow-speed scan testing
CLK

shift

shift E launch

capture

shift

SE

Time

Time

load<unload c#cles
EE141 System-on-Chip Test Architectures

load<unload c#cles

Time

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". #ow$Power %can !esting $ &asics

=t-speed scan testing with a L4* test scheme
Last shift , 1 applied
CLK

*apture E Launch , " applied

>esponse capture

shift

shift

SE LOC sche e

Time

SE LOS sche e

Time

Launch is caused # the difference etween the values loaded Time # the last shift pulse /,11 and the first capture pulse /,"1 SE eas#
load<unload c#cles to implement0

ut

test c#cle lower

fault

load<unload c#cles coverage than

L4S
15

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". #ow$Power %can !esting $ &asics

=t-speed scan testing with a L4S test scheme
, 1 applied
CLK

Last shift E Launch , " applied

>esponse capture

shift

shift

SE LOS sche e

Time

Time

Launch is caused # the difference etween the values loaded # the next-to-last /,11 and the last /,"1 shift pulses )igher fault coverage than L4*0 ut SE not eas# to implement
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". #ow$Power %can !esting $ &asics

The pro lem of excessive power during scan testing can e split into two su -pro lems8 excessive power during the shift operation /called shift power1 and excessive power during the capture operation /called capture power1 =t-speed scan testing especiall# vulnera le to excessive I> drop caused # the high switching activit# generated in the *FT etween launch and capture #ield loss

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". #ow$Power %can !esting

=TP? and G-filling techni6ues /1<$1

The fraction of donHt care its /XHs1 in a given =TP? test cu e is nearl# alwa#s a ver# large fraction of the total num er of its despite the application of state-of-the-art d#namic and static test pattern compaction techni6ues In classical =TP?0 XHs are randoml# filled and then the resulting full# specified pattern is simulated to confirm detection of all targeted faults and to measure the amount of Bfortuitous detectionC
Ch. 7 Low-Power Testing - P. 1!
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EE141 System-on-Chip Test Architectures

". #ow$Power %can !esting

Power-aware =TP? algorithms /"<$1

*lever assignment of donHt care its in com inational /P4+E7 li3e1 =TP? in order to minimi5e the num er of transitions etween two consecutive test vectors 7inimi5ing the difference etween the eforecapture and after-capture output values of a scan flip-flop

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". #ow$Power %can !esting

Power-aware G-filling heuristics /$<$1
From a set of deterministic test cu es0 the main goal of these techni6ues is to assign donHt care its of each test pattern so that the occurrence of transitions in the scan chain is minimi5ed8 =dIacent filling or 7T-filling 9-filling 1-filling 9GGG1GG9GG9GG 9999111999999 with 7T-filling 9999199999999 with 9-filling 9111111911911 with 1-filling

=pplica le at the end of the design process0 no area overhead >educe test power consumption # reasona le increase of test length = few solutions exist for reducing power during test c#cle /L4*1
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". #ow$Power %can !esting

Low power test vector compaction

Static compaction minimi5es the num er of test cu es generated # an =TP? tool # merging test cu es that are compati le in all it positions Example 18 11GG9 and 1G9G9 are compati le /- 119G91 Example 28 11GG9 and 911G1 are not compati le

*onventional approaches target the minimum num er of final test cu es JSan3aralingam "999K used a greed# heuristic for merging test cu es in a wa# that minimi5es the num er of transitions /use of weighted transition metric1 Significant reductions in average and pea3 power consumption
Ch. 7 Low-Power Testing - P. 21
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EE141 System-on-Chip Test Architectures

". #ow$Power %can !esting

Low-power /gated1 scan cells
*om inational Part

+ SI *L@ SE

9 1

L output

S4

?ate scan cells loc3 transitions during scan shifting ,er# effective in test power reduction Significant area overhead and performance degradation
22

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". #ow$Power %can !esting

Scan cell ordering /1<"1
!!" !!# !!$ !!% !!# !!% !!" !!$

9191

9 1 9 1 9

9 9 1 9 1

9 9 9 1 9

9 9 9 9 1

1199

9 9 9 1 1

9 9 9 9 1

9 9 9 9 9 9

9 9 9 9

19 transitions generated during loading of ,

" transitions generated after scan cell reordering

2eed to change the order of its in each vector during test application Scan cell reordering ma# lead to significant power reduction /up to ''M1 2o overhead0 F* and test time unchanged0 low impact on design flow 7a# lead to routing congestion pro lems .
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". #ow$Power %can !esting

Scan cell ordering /"<"1

Partition the circuit in clusters / # using geographical criteria1 Then reorder the scan cells within each cluster so as to reduce NS= *lusters are then stitched together using the nearest neigh or criteria ?ood tradeoff etween test power reduction and scan chain length
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". #ow$Power %can !esting

Scan chain segmentation
*om inational Logic SE
Scan *hain = Scan *hain &

*apture

*L@=
Scan *hain *

Scan In *L@= *L@ *L@& *loc3 =daptor

Scan4ut

*L@& *L@*

*L@*

The scan chain is partitioned into 2 segments 4ne segment at a time is active during scan shifting =verage power reduced # a factor of 2 with no impact on area and F* *loc3 power is reduced # gating the cloc3 trees rather than the SE signals
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". #ow$Power %can !esting

Scan architecture modification

Inserting logic elements /G4> gates1 etween scan cells in order to minimi5e the num er of transitions occurring inside the scan chain Fse of uffers /of various si5e1 in multi-scan circuits to provo3e a slight temporal shift etween scan chains and reduce pea3 power

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". #ow$Power %can !esting

To3en scan architecture /1<"1
ScanIn
1 " I 2

Scan4ut 1 " I 2

*L@

7ultiphase ?enerator

Scan architecture that uses the concept of a Bto3en ringC to reduce shift power SI is roadcasted to all scan cells ut onl# one scan cell is activated at a time =n N-phase non-overlapping cloc3ing scheme is applied with one cloc3 for each scan cell
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". #ow$Power %can !esting

To3en scan architecture /"<"1
*L@ Scan
Si +i

ScanIn
1 *L@ " I 2
9 1 *L> Ti + +" L S S9 T*@

1 9 + +1 L T9

Scan4ut

+9

=lternative solution to avoid large area overhead of the N multiphase cloc3 routes and inter-phase s3ews due to the different lengths of the N cloc3 routes It em eds the multiphase cloc3 generator into each scan cell >e6uire the use of a new t#pe of scan cells0 called to3en scan cells
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". #ow$Power %can !esting

Scan cloc3 splitting
*ircuit Fnder Test
*om4ut CLK/2 CLK/2

,dd CLK T ,dd CLK&# ,dd CLK&# ' "T 4T T $T %T Time "T $T 4T %T Time

ScanIn

Scan *ells =
SE

Scan *ells &

1 9

Scan4ut

Time

The two cloc3s are s#nchronous with the s#stem cloc3 and have the same period during shift operation except that the# are shifted in time +uring capture operation0 the two cloc3s operate as the s#stem cloc3 Lowers the transition densit# in the *FT0 the scan chains and the cloc3 tree
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'. #ow$Power &I%! $ &asics

Test Pattern ?enerator /TP?1 Logic &IST *ontroller *ircuit Fnder Test /*FT1

4utput >esponse =nal#5er /4>=1

= test pattern generator /TP?1 automaticall# generates test patterns for application to the inputs of the circuit under test /*FT1 In-circuit TP?s constructed from LFS>s are most commonl# used LFS>s are also used for output response analyzer /4>=1 &IST is implemented as Test-per-scan or as test-per-clock Even if it is slower0 test-per-scan is the industr# preferred solution toda#
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'. #ow$Power &I%!

Low power test pattern generators /1<$1
*ircuit Fnder Test

*L@ S*L@ SelO*L@

*L@

Slow LFS><7IS>

2ormal-speed LFS><7IS>

Dual-Speed LFSRs is ased on two LFS>s running at different fre6uencies =verage power during test is reduced # connecting the *FT inputs with the highest transition densities to the low speed LFS> while *FT inputs with the lowest activit# are connected to the normal speed LFS>
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'. #ow$Power &I%!

Low power test pattern generators /"<$1
3 LFS> r SI TFF Scan *hain m Scan4ut

*FT

Lo transition random test pattern generator involves inserting an =2+ gate and a toggle flip-flop /TFF1 etween the LFS> and the input of the scan chain to increase the correlation of neigh oring its in the scan vectors TFF holds its previous values until it receives a 1 on its input! The same value /9 or 11 is repeatedl# scanned into the scan chain until the value at the output of the =2+ gate ecomes 1
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'. #ow$Power &I%!

Low-power test pattern generators /$<$1

&# carefull# choosing the seed of the LFS> /choice of pol#nomial has no real influence1 &# inserting translating logic etween the LFS> and the *FT to o tain weighted random test vectors &# using ?ra# counters producing consecutive test vectors with onl# one it difference in the case of deterministic testing of data paths
Ch. 7 Low-Power Testing - P. 33
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EE141 System-on-Chip Test Architectures

'. #ow$Power &I%!

,ector filtering &IST
!est "e#uence
V0
*L@

LFS>

$%"& inhi'ition
Vi Vj V Vl

+ecoder

$%"& acti(ation $%"& inhi'ition $%"& acti(ation

FF

*ircuit Fnder Test

Prevent application of non-detecting / ut consuming1 vectors to the *FT = decoder is used to store the first and last vectors of each su -se6uence of consecutive non-detecting vectors to e filtered 7inimi5es average power without reducing fault coverage
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'. #ow$Power &I%!

*ircuit partitioning
( ) C * ( )
DMUX M U X

C
DMUX

)
DMUX

C
DMUX

C"

C#

C"

M U X

C#

C"

M U X

C#

MUX

MUX

MUX

MUX

Partition the original circuit /using a graph partitioning algorithm that minimi5es the cut si5e1 into structural su -circuits so each su -circuit can e successivel# tested through different &IST sessions F* and test time are unchanged and area overhead is 6uite low +raw ac3s are a slight penalt# on performance and an impact on routing
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'. #ow$Power &I%!

Power-aware test scheduling /1<$1
)o*er )o*er li+it

!est ti+e The goal is to determine the loc3s /memor#0 logic0 analog0 etc!1 of an S4* to e tested in parallel at each stage of the &IST session in order to 3eep power dissipation under a specified limit while optimi5ing test time Some of the test resources /pattern generators and response anal#5ers1 must e shared among the various loc3s
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'. #ow$Power &I%!

Power-aware test scheduling /"<$1

The 2P-complete test scheduling pro lem ma# e addressed # using a compati ilit# graph and heuristic-driven algorithms For given power constraints and parameters related to the test organi5ation /fixed0 varia le0 or undefined test sessions with or without precedence constraints1 or to the test structure /test us width0 test resources sharing10 these solutions allow to optimi5e overall S4* test time
37

EE141 System-on-Chip Test Architectures

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'. #ow$Power &I%!

Power-aware test scheduling /$<$1
SOC
Em edded Tester Tester 7emor# Test *ontroller &IST *ore $ &IST *ore 4 &IST *ore % *ore 1 &IST *ore " &IST

7ain focus is on total energ# minimi5ation under tester memor# constraint The test set is composed of core-level locall# generated pseudo-random test patterns and additional deterministic test patterns that are generated off-line and stored in the s#stem = careful tradeoff etween the deterministic pattern lengths of the core must therefore e made in order to produce a glo all# optimal solution
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(. #ow$Power !est )ata Co*pression

)igh test data volume leads to a high testing time and ma# exceed the limited memor# depth of =TE Test data compression involves encoding a test set so as to reduce its si5e =TE limitations0 i!e!0 tester storage memor# and andwidth gap etween the =TE and the *FT0 ma# hence e overcome Fsing compressed test data involves having an on-chip decoder which decompresses the data Low-+ower test data co +ressio, tech,i-ues are ,eeded to co,curre,tly reduce sca, +ower dissi+atio, a,d test data .olu e duri,g test
Ch. 7 Low-Power Testing - P. 3"
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EE141 System-on-Chip Test Architectures

(. #ow$Power !est )ata Co*pression

*oding- ased schemes

Fse of 9-filling on =TP? test cu es and then encode runs of 9Hs with !olom" codes /runlength codes1 for reducing the num er of transitions /(%M1 ?olom coding is ver# inefficient for runs of 1Hs = s#nchroni5ation signal etween the =TE and the *FT is re6uired as the si5e of the compressed data /codeword1 is of varia le length #lternating run-lengt$ coding improves the encoding efficienc# of ?olom coding /can encode oth runs of 9Hs and runs of 1Hs 1

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(. #ow$Power !est )ata Co*pression

Linear-decompression- ased schemes /1<"1

Linear +ecompressors consist of G4>s and flip-flops In LFS> reseeding

+eterministic test cu es generated # expanding seeds T#picall# 1-%M of its in test vector specified 7ost its need not e considered when seed computed Si5e of seed much smaller than si5e of vector Significantl# reduces test data volume and andwidth 3esults i, e4cessi.e switchi,g duri,g sca, shi2ti,g

Pro/le 0 %1s i, test cu/es 2illed ra,do ly

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(. #ow$Power !est )ata Co*pression

Linear-decompression- ased schemes /"<"1

Low power L+ using LFS> reseeding can e used LFS> reseeding not used to directl# encode specified its

Each test cu e divided into loc3s loc3s containing

LFS> reseeding used onl# to produce transitions For loc3s not containing transitions

Logic value fed into scan chain simpl# held constant etween test data compression

>educes num er of transitions in scan chain Efficient solution to trade-off and test power reduction

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(. #ow$Power !est )ata Co*pression

&roadcast-scan- ased schemes /1<"1
*loc3 Tree

Segmented #ddressa"le Scan &S#C'

Segment 1 Segment "

Segment =ddress
7ulti-)ot +ecoder

P P P Segment 7

4utput *ompressor

Tester *hannel or Input +ecompressor

&ased on roadcasting the same value to multiple scan segments S=* enhances the Illinois scan architecture # avoiding the limitation of having to have all segments compati le to enefit from the segmentation Test power is reduced as segments which are incompati le during the time needed to upload a given test pattern are not cloc3ed
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(. #ow$Power !est )ata Co*pression

&roadcast-scan- ased schemes /"<"1
Sense amplifiers E 7IS> >ow ena le shift register 7ode

(rogressi)e Random #ccess Scan &(R#S'

Test *ontrol Scan data I<4

*olumn line driver

*olumn address decoder

*olumn address

Scan cells are configured as an S>=7-li3e structure using P>=S scan cells P>=S allows individual accessi ilit# to each scan cell0 thus eliminating unnecessar# switching activit# during scan0 while reducing the test application time and test data volume # updating onl# a small fraction of scan-cells
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7. #ow$Power +,M !esting

7otivated # the need to concurrentl# test several an3s of memories in a s#stem to reduce test time = first strateg# is to reorder memory tests to reduce the switching activit# on each address line while retaining the fault coverage and the memor# overall test time
Origi,al Test Low-+ower Test Q s /N90 >90 N10 >11R Q s /N/1odd<9even10 >/1odd<9even10
N/9odd<1even10 >/9odd<1even11R

5ero-O,e Chec6er )oard

Q /N91R Q />91R Q /N11R Q />11R Q /N/1odd<9even11R Q/>/1odd<9even11R Q/N/9odd<1even11R Q/>/9odd<1even11R

Single it change /S&*1 counting

Power dissipation reduced # a factor of two to sixteen = special design of the &IST circuitr# is needed
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EE141 System-on-Chip Test Architectures

7. #ow$Power +,M !esting

= second strateg# is to e*ploit t$e predicta"ility o+ t$e addressing se,uence to reduce t$e pre-c$arge acti)ity during test Pre-charge circuits contri ute to up to (9M to power dissipation In functional mode0 the cells are selected in random se6uence0 and all pre-charge circuits need to e alwa#s active0 while during the test mode the access se6uence is 3nown0 and hence onl# the columns that are to e selected need to e pre-charged This low-power test mode can e implemented # using a modified pre-charge control circuitr#0 and # exploiting the first degree of freedom of 7arch tests0 which allows choosing a specific addressing se6uence =ddressing se6uence is fixed to Bword line after word lineC and the pre-charge activit# is restricted to onl# two columns for each cloc3 c#cle8 the selected column and the following one
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EE141 System-on-Chip Test Architectures

7. #ow$Power +,M !esting

&LI-1 &L&I-1 &LI &L&I &LIS1 &L&IS1

Prec Prec

Prec

=dditional pre-charge control logic Prec

LPtest ; Low power test command

PrI-1 *S I-1

PrI *SI

PrIS1 *SIS1

%9M power savings with negligi le impact on area overhead and memor# performance
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EE141 System-on-Chip Test Architectures

%u**ary and Conclusions

Test throughput and manufacturing #ield ma# e affected # excessive test power Therefore0 lowering test power has een and is still a focus of intense research and development Following points have een surve#ed8

Test power parameters and contri utors Pro lems induced # an increased test power

Structural and algorithmic solutions for low-power test along with their impacts on parameters such as fault coverage0 test time0 area overhead0 circuit performance penalt#0 and design flow modification
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%u**ary and Conclusions

=dditional concerns Testing when new low-power design techni6ues used +#namic power management techni6ues TShut-downT parts of design when idle Testing currentl# done se6uentiall# Test deals with power domains one at a time Practice ecoming inade6uate due to test time concern 7ultiple-voltage domains used to reduce power )ow to safel# handle test of such designsU .

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49