Cmos Vlsi Design

CMOS VLSI Design
Jitendra S Sengar
Asst. Professor(ECE)
CMOS VLSI Design
Jitendra S Sengar, Asst. Professor (ECE)
MOS Transistor
A MOS (Metal-Oxide-Semiconductor) structure is
created by superimposing several layers of
conducting and insulating materials to form a
sandwich-like structure
These structures are manufactured using a series of
chemical processing steps involving oxidation of the
silicon, the diffusion of impurities into the silicon to
give it certain conduction characteristics, and the
deposition and etching of aluminium or other metals
to provide interconnection in the same way that a
printed wiring board is constructed
This is carried out on a single crystal of silicon, which
is available as thin flat circular wafers around 15-30
cm in diameter
CMOS VLSI Design
MOS Transistor
MOS technology provides two types of transistors (also
called devices): an n-type transistor (nMOS) and a p-type
transistor (pMOS)
Transistor operation is based on electric fields so the
devices are also called Metal Oxide Semiconductor Field
Effect Transistors (MOSFETs) or simply FETs
Each transistor consists of a stack of the conducting gate,
an insulating layer of silicon dioxide (Si02, better known as
glass), and the silicon wafer, also called the substrate, body
or bulk
Gates of early transistors were built from metal, so the
stack was called metal- oxide-semiconductor, or MOS, now
the gate is typically formed from polycrystalline silicon
{polysilicon), but the name stuck
CMOS VLSI Design
MOS Transistor
An nMOS transistor is built with a p-type body and
has regions of n-type semiconductor adjacent to the
gate called the source and drain, they are physically
equivalent and for now we will regard them as
interchangeable, the body is typically grounded
A pMOS transistor is just the opposite, consisting of
p-type source and drain regions with an n-type body
In a CMOS technology with both flavors of
transistors, the substrate is either n-type or p-type,
the other flavor of transistor must be built in a
special well in which dopant atoms have been locally
added to form the body of the opposite type
CMOS VLSI Design
MOS Transistor
CMOS VLSI Design

MOS Transistor
CMOS VLSI Design

MOS Transistor
CMOS VLSI Design

MOS Transistor
The gate is a control input: It affects the flow of electrical
current between the source and drain
For an nMOS transistor, the body is generally grounded so
the p-n junctions of the source and drain to body are
reverse-biased
If the gate is also grounded, no current flows through the
reverse-biased junctions, hence, the transistor is OFF
If the gate voltage is raised, it creates an electric field that
starts to attract free electrons to the underside of the SiSi02 interface
If the voltage is raised enough, the electrons outnumber
the holes and a thin region under the gate called the
channel is inverted to act as an n-type semiconductor
A conducting path of electron carriers is formed from
source to drain and current can flow, hence, the transistor
CMOS VLSI Design
is ON
MOS Transistor Switch

The gate of an MOS transistor controls the flow of
current between the source and drain, hence the
MOS transistors can be viewed as simple on/off
switches
When the gate of an nMOS transistor is '1,' the
transistor is ON and there is a conducting path from
source to drain, when the gate is low, the nMOS
transistor is OFF and almost zero current flows from
source to drain
A pMOS transistor is just the opposite, being ON
when the gate is low and OFF when the gate is high
This switch model is so useful that it will be our most
common model for thinking about circuit behavior
illustrated, where g, s, and d Vindicate gate, source,
and drain
CMOS VLSI Design
MOS Transistor Switch
CMOS VLSI Design

CMOS Logic (Inverter)

A CMOS inverter or NOT gate is constructed using
one nMOS transistor and one pMOS transistor
The horizontal bar at the top indicates VDD and
the triangle at the bottom indicates GND
When the inputs is '0,' the nMOS transistor is OFF
and the pMOS transistor is ON
Thus the output Y is pulled up to '1' because it is
connected to VDD but not to GND
Conversely, when A is '1, the nMOS is ON, the
pMOS is OFF, and the Y is pulled down to '0
CMOS VLSI Design
CMOS Logic (Inverter)
CMOS VLSI Design

CMOS Logic (NAND Gate)

A 2-input CMOS NAND gate consists of two series
nMOS transistors between Y and GND and two
parallel pMOS transistors between Yand VDD
If either inputs A or B is '0, at least one of the
nMOS transistors will be OFF, breaking the path from
Y to GND
But at least one of the pMOS transistors will be ON,
creating a path from Y to VDD, hence, the output Y
will be 1'
If both inputs are '1,' both of the nMOS transistors
will be ON and both of the pMOS transistors will be
OFF, hence, the output will be '0
CMOS VLSI Design
CMOS Logic (NAND Gate)
CMOS VLSI Design

CMOS Logic (Combinational Logic)

The inverter and NAND gates are examples of
complementary CMOS logic gates, also called
static CMOS gates
In general, a fully complementary CMOS gate has
an nMOS pull-down network to connect the
output to '0' (GND) and pMOS pull-up network to
connect the output to '1' (VDD),
The networks are arranged such that one is ON
and the other OFF for any input pattern
CMOS VLSI Design

The pull-up and pull-down networks in the
inverter each consists of a single transistor
The NAND gate uses a series pull-down network
and a parallel pull-up network
More elaborate networks are used for more
complex gates
Two or more transistors in series are ON only if all
of the series transistors are ON
Two or more transistors in parallel are ON if any
of the parallel transistors are ON
CMOS VLSI Design
CMOS VLSI Design


In general when we join a pull-up network to a pull-down
network to form a logic gate they both will attempt to exert a
logic level at the output
The possible levels at the output of a CMOS logic gate can be in
four states
The '1' and 0 levels have been encountered with the inverter
and NAND gates, where either the pull-up or pull-down is OFF
and the other structure is ON
When both pull-up and pull-down are OFF, the high-impedance
or floating Z output state results, This is of importance in
multiplexers, memory elements, and bus drivers
The crowbarred X level exists when both pull-up and pulldown are simultaneously turned ON, This causes an
indeterminate level and also static power to be dissipated,It is
usually an unwanted condition in any CMOS digital circuit
CMOS VLSI Design
CMOS Logic (NOR Gate)

In a 2-input NOR gate the nMOS transistors are in
parallel to pull the output low when either input
is high
The pMOS transistors are in series to pull the
output high when both inputs are low
With the NAND gate, there is never a case in
which the output is crowbarred or left floating
CMOS VLSI Design

CMOS Logic (NOR Gate)
CMOS VLSI Design

CMOS Logic (Compound gates)
CMOS VLSI Design

CMOS Logic (Compound gates)
CMOS VLSI Design

Circuit and system representation

Any complex digital system may be broken down
into component gates and memory elements by
successively subdividing the system in a hierarchical
manner
To do this, a specific set of abstractions have been
developed to describe integrated electronic systems
This divides the system in three distinct design
domains:
Behavioral Domain
Structural Domain
Physical Domain
CMOS VLSI Design

Behavioral domain specifies what a particular
system dose
Structural domain specifies how entities are
connected together effect the prescribed
behavior
Physical domain specifies how to actually build a
structure that has the required connectivity to
implement the prescribed behavior
Each design domain may be specified at a variety
of levels of abstraction
CMOS VLSI Design

Digital VLSI design is often partitioned into five
interrelated tasks: architecture design,
microarchitecture design, logic design, circuit design,
and physical design
Architecture describes the functions of the system.
For example, the x86 microprocessor architecture
specifies the instruction set, register set, and
memory model
Microarchitecture describes how the architecture is
partitioned into registers and functional units, the
80386, 80486, Pentium, Pentium II, Pentium III,
Pentium 4, Celeron, Cyrix Mil, AMD K5, and Athlon
are all microarchitectures offering different
performance / transistor count tradeoffs for the x86
architecture
CMOS VLSI Design

Logic describes how functional units are constructed,
for example, various logic designs for a 32-bit adder
in the x86 integer unit include ripple carry, carry
lookahead, and carry select
Circuit design describes how transistors are used to
implement the logic. For example, a carry lookahead
adder can use static CMOS circuits, domino circuits,
or pass transistors. The circuits can be tailored to
emphasize high performance or low power
Physical design describes the layout of the chip
These elements are inherently interdependent
CMOS VLSI Design

To deal with these interdependencies, microarchitecture,
logic, circuit, and physical design must occur, at least in
part, in parallel
Microarchitects depend on circuit and physical design
studies to understand the cost of proposed
microarchitectural features
Engineers are sometimes categorized as "short and fat" or
"tall and skinny"
Tall, skinny engineers understand something about a broad
range of topics
Short, fat engineers understand a large amount about a
narrow field
Digital VLSI design favours the tall, skinny engineer who
can evaluate how choices in one part of the system impact
other parts of the system
CMOS VLSI Design

An alternative way of viewing design partitioning is
done with the Y-chart [Gajski83, Kang03]
The radial lines on the Y-chart represent three
distinct design domains: behavioural, structural, and
physical
These domains can be used to describe the design of
almost any artefact and thus form a very general
taxonomy for describing the design process
Within each domain there are a number of levels of
design abstraction that start at a very high level and
descend eventually to the individual elements that
need to be aggregated to yield the top level function
(i.e., in the case of chip design and transistors)
CMOS VLSI Design
CMOS VLSI Design


The behavioural domain describes what a
particular system does
For instance, at the highest level we might state
that we desire to build a chip that can generate
audio tones of specific frequencies (i.e., a touchtone generator for a telephone)
This behaviour can be successively refined to
more precisely describe what needs to be done in
order to build the tone generator (i.e., the
frequencies desired, output levels, distortion
allowed, etc.)
CMOS VLSI Design

At each abstraction level, a corresponding structural
description can be described
The structural domain describes the interconnection
of modules necessary to achieve a particular
behaviour
For instance, at the highest level, the touch-tone
generator might consist of a keyboard, a tone
generator, an audio amplifier, a battery, and a
speaker
Eventually at lower levels of abstraction, the
individual gate and then transistor connections
required to build the tone generator are described
CMOS VLSI Design

For each level of abstraction, the physical domain
description explains how to physically construct
that level of abstraction
At high levels this might consist of an engineering
drawing showing how to put together the
keyboard, tone generator chip, battery, and
speaker in the associated housing
At the top chip level, this might consist of a floor
plan, and at lower levels, the actual geometry of
individual transistors
CMOS VLSI Design

The design process can be viewed as making
transformations from one domain to another while
maintaining the equivalency of the domains
Behavioral descriptions are transformed to structural
descriptions, which in turn are transformed to physical
descriptions
These transformations can be manual or automatic. In
either case, it is normal design practice to verify the
transformation of one domain to the other by some
checking process
This ensures that the design intent is carried across the
domain boundaries
Hierarchically specifying each domain at successively
detailed levels of abstraction allows us to design very large
systems.
CMOS VLSI Design
MOS Transistor Theory

The MOS transistor is a majority-carrier device in
which the current in a conducting channel
between the source and drain is controlled by a
voltage applied to the gate
In an nMOS transistor, the majority carriers are
electrons
In a pMOS transistor, the majority carriers are
holes
The behaviour of MOS transistors can be
understood by first examining an isolated MOS
structure with a gate and body but no source or
drain
CMOS VLSI Design
MOS Transistor Theory (Accumulation)
CMOS VLSI Design

MOS Transistor Theory (Depletion)
CMOS VLSI Design

MOS Transistor Theory (Inversion)
CMOS VLSI Design

MOS Transistor Theory (Cut-off)

In an nMOS transistor with a grounded source
and p-type body, the transistor consists of the
MOS stack between two n-type regions called the
source and drain
If the gate-to-source voltage Vgs is less than the
threshold voltage, then source and drain have
free electrons and the body has free holes but no
free electrons
The junctions between the body and the source
or drain are reverse-biased, so almost zero
current flows, this mode of operation is called
cut-off
CMOS VLSI Design
MOS Transistor Theory (Cut-off)
CMOS VLSI Design

MOS Transistor Theory (Linear)

If the gate voltage is greater than the threshold voltage,
then an inversion region of electrons (majority carriers)
called the channel connects the source and drain,
creating a conductive path
The number of carriers and the conductivity increases with
the gate voltage
The potential difference between drain and source is
Vds =Vgs- Vgd , If Vds = 0 (i.e., Vgs = Vgd), there is no
electric field tending to push current from drain to source
When a small positive potential Vds is applied to the drain,
current Ids flows through the channel from drain to source
This mode of operation is termed linear, resistive,
nonsaturated, or unsaturated
The current increases with both the drain voltage and gate
voltage
CMOS VLSI Design
MOS Transistor Theory (Linear)
CMOS VLSI Design

MOS Transistor Theory (Saturation)

If Vds becomes sufficiently large that Vgd < Vt, the
channel is no longer inverted near the drain and
becomes pinched-off
However, conduction is still brought about by the
drift of electrons under the influence of the positive
drain voltage
As electrons reach the end of the channel, they are
injected into the depletion region near the drain and
accelerated toward the drain
Above this drain voltage the current Ids is controlled
only by the gate voltage and ceases to be influenced
by the drain
This mode is called saturation
CMOS VLSI Design
MOS Transistor Theory (Saturation)
CMOS VLSI Design

MOS Transistor Theory

In summary, the nMOS transistor has three
modes of operation
If Vgs < Vt the transistor is cut off and no current
flows
If Vgs > Vt and Vds is small, the transistor acts as
a linear resistor in which the current flow is
proportional to Vds
If Vgs > Vt and Vds is large, the transistor acts as
a current source in which the current flow
becomes independent of Vds
CMOS VLSI Design
MOS Transistor Theory(I-V Characteristics)

MOS transistors have three regions of operation:
* Cutoff or subthreshold region
* Linear or nonsaturation region
* Saturation region
Let us derive a first-order (ideal Shockley) model
relating the current and voltage (I-V) for an nMOS
transistor in each of these regions
In the cutoff region (Vgs < Vt), there is no channel
and almost zero current flows from drain to source
In the other regions, the gate attracts carriers
(electrons) to form a channel, the electrons drift
from source to drain at a rate proportional to the
electric field between these regions
CMOS VLSI Design

Thus we can compute currents if we know the
amount of charge in the channel and the rate at
which it moves
We know that the charge on each plate of a
capacitor is Q = CV
Thus the charge in the channel Qchannel is
CMOS VLSI Design

CMOS VLSI Design


We can model the gate as a parallel plate
capacitor with capacitance proportional to area
over thickness
If the gate has length L and width W and the
oxide thickness is tox, then, the capacitance is
CMOS VLSI Design

CMOS VLSI Design


Each carrier in the channel is accelerated to an
average velocity proportional to the lateral
electric field, i.e., the field between source and
drain, the constant of proportionality u. is called
the mobility
The electric field E is the voltage difference
between drain and source Vds divided by the
channel length
CMOS VLSI Design

The time required for carriers to cross the
channel is the channel length divided by the
carrier velocity: L/v
Therefore, the current between source and drain
is the total amount of charge in the channel
divided by the time required to cross
CMOS VLSI Design


Previous equation describes the linear region of operation,
for Vgs > Vt but Vds relatively small
It is called linear or resistive because Vds/2 Vgs- Vt Ids
increases almost linearly with Vds, just like an ideal resistor
However, if Vds > Vdsat =Vgs-Vt, the channel is no longer
inverted in the vicinity of the drain; we say it is pinched off
Beyond this point, called the drain saturation voltage,
increasing the drain voltage has no further effect on
current
Substituting Vds = Vdsat, at this point of maximum current
into the previous equation, we find an expression for the
saturation current that is independent of Vds
This expression is valid for Vgs > Vt, and Vds > Vdsat
CMOS VLSI Design
It is sometimes convenient to define Idsat as the

current of a transistor that is fully ON,
ie; Vgs=Vds=VDD
CMOS VLSI Design


Summarily the current in the three regions:
CMOS VLSI Design


n-MOS Transistor
CMOS VLSI Design

p-MOS Transistor
CMOS VLSI Design
MOS Transistor Theory(MOS Capacitance)

An MOS transistor can be viewed as a fourterminal device with capacitances between each
terminal pair
The gate capacitance includes an intrinsic
component (to the body, source and drain, or
source alone, depending on operating regime)
and overlap terms with the source and drain
The source and drain have parasitic diffusion
capacitance to the body.
CMOS VLSI Design
MOS Transistor Theory(MOS Capacitance)
CMOS VLSI Design

CMOS Inverter DC Characteristics

Digital circuits are merely analog circuits used
over a special portion of their range
The DC transfer characteristics of a circuit relate
the output voltage to the input voltage,
assuming the input changes slowly enough that
capacitances have plenty of time to charge or
discharge
Specific ranges of input and output voltages are
defined as valid '0' and '1 logic levels
CMOS VLSI Design
The DC transfer function is a plot (Vout vs. Vln) for

the complementary CMOS inverter
Table outlines various regions of operation for the nand p-transistors
Vtn is the threshold voltage of the n-channel device,
and Vtp is the threshold voltage of the p-channel
device
Note that Vtp is negative, The equations are given
both in terms of Vgs / Vds and Vin / Vout
As the source of the nMOS transistor is grounded,
Vgsn = Vin and Vdsn = Vout
As the source of the pMOS transistor is tied to VDD,
Vgsp=Vin-VDD and Vdsp=V0ut-VDD
CMOS VLSI Design
CMOS VLSI Design

CMOS VLSI Design


The objective is to find the variation in output
voltage (Vout) as a function of the input voltage
(Vin)
This may be done graphically, analytically or
through simulation
Given Vin we must find Vout subject to the
constraint that Idsn = ! Idsp !
For simplicity, we assume Vtp = -Vtn and that the
pMOS transistor is 2-3 times as wide as the nMOS
transistor
CMOS VLSI Design

The first plot shows Idsn and Idsp in terms of Vdsn and
Vdsp for various values of Vgsn and Vgsp
Second plot shows the same plot of Idsn and ! Idsp ! now
in terms of Vout for various values of Vin
The possible operating points of the inverter, marked with
dots, are the values of Vout where Idsn = ! Idsp ! for a given
value of Vin
These operating points are plotted on Vout vs. Vin axes in
third plot to show the inverter DC transfer characteristics
The supply current IDD = Idsn = ! Idsp ! ls also plotted
against Vin in fourth plot showing that both transistors are
momentarily ON as Vin passes through voltages between
GND and VDD, resulting in a pulse of current drawn from
the power supply
CMOS VLSI Design
CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design


The operation of the CMOS inverter can be
divided into five regions indicated on third Plot
In region A, the nMOS transistor is OFF so the
pMOS transistor pulls the output to VDD
In region B, the nMOS transistor starts to turn
ON, pulling the output down
In region C, both transistors are in saturation
Notice that ideal transistors are only in region C
for Vin = VDD/2 and that the slope of the transfer
curve is 8 in this region, corresponding to
infinite Gain
CMOS VLSI Design

Real transistors have finite output resistances,
and thus have finite slopes over a broader region
C
In region D, the pMOS transistor is partially ON
In region E, it is completely OFF, leaving the
nMOS transistor to pull the output down to
GND
Also notice that the inverter's current
consumption is zero when the input is within a
threshold voltage of the VDD or GND rails. This
feature is important for low-power operation.
CMOS VLSI Design
CMOS VLSI Design

CMOS VLSI Design

Circuit Characterization
The most obvious way to characterize a circuit is
through simulation
Simulations only inform us how a particular circuit
behaves, not how to change the circuit to make it
better
Moreover, if we don't know approximately what the
result of the simulation should be, we are unlikely to
catch bugs in our simulation model
Mediocre engineering rely predominantly on
computer tools, but outstanding engineering develop
its physical intuition to rapidly estimate the
behaviour of circuits
CMOS VLSI Design
Circuit Characterization(Resistance)
The resistance of a uniform slab of conducting
material is given as
Where
This can be rewritten as

Rs is the sheet resistance
CMOS VLSI Design
CMOS VLSI Design

CMOS VLSI Design

Although the voltage current characteristics of a
MOS transistor is generally nonlinear
It is sometimes useful to approximate the
behavior in terms of channel resistance to
estimate the performance
Channel resistance in linear region
Where
CMOS VLSI Design
For both n-channel and p-channel devices, K
may take a value within the range 1000 to
30000 Ohm/Sq
Channel resistance is dependent on the surface
mobility (u) of majority charge carriers
Since mobility and threshold voltage are a
function are a function of temperature
The channel resistance and therefore switching
time parameters as well as power dissipation,
change with temperature variations
CMOS VLSI Design
Contacts and vias also have a resistance
associated with them that is dependent on
contact materials and proportional to the area
of contact
As contacts are reduced in size (Scaled down),
the associated resistance increases
Typical values for process currently in use
ranges from 0.25 Ohm to a few ohms
CMOS VLSI Design
Circuit Characterization(capacitance)
The dynamic response (Switching speed) of MOS
systems are very much dependent on the
parasitic capacitance
These capacitances are associated with the MOS
device and interconnection
capacitances that are formed by metal, poly, and
diffusion wires in concert with transistor and
conductor resistance
CMOS VLSI Design
The total load capacitance on the output of an
MOS gate is the sum of
Gate capacitance (of other input connected to
the output of the gate)
Diffusion capacitance (of the drain region
connected to the output)
Routing capacitance (of connections between the
output and other inputs)
CMOS VLSI Design

The C-V characteristics of a MOS structure
depends on the state of semiconductor surface
Depending on the gate voltage the surface may
be in Accumulation, Depletion or Inversion
In accumulation MOS structure behaves like a
parallel plate capacitor and the gate capacitance
may be approximated by
Where
A= area of the gate
CMOS VLSI Design
CMOS VLSI Design

CMOS VLSI Design

Since the magnitude of the charge density per unit
area in the surface depletion region is dependent on
the doping concentration (N), electronic charge (q)
and the depth of the surface depletion region(d)
Increasing the gate to substrate voltage also
increases d
Depletion capacitance is given as
Where
d=depletion layer depth
CMOS VLSI Design
As the depth of the depletion region increases,
the capacitance from gate to substrate will
decrease
Total capacitance from gate to substrate under
depletion condition can be regarded as that being
due to gate oxide capacitance Co in series with
Cdep
CMOS VLSI Design

Surface inversion yields a relatively high
conductivity layer under the gate, which restores
the low frequency capacitance to Co
Because of the limited supply of
carriers(electrons) to the inversion layer, the
surface charge is not able to track fast moving
gate voltage
Hence the dynamic capacitance remains the same
as for the maximum depletion situation
Low frequency(< 100Hz)
CMOS VLSI Design
CMOS VLSI Design

MOS device capacitance
CMOS VLSI Design

MOS device capacitance
CMOS VLSI Design

In MOS transistor deferent parasitic capacitances
involved are
Cgs, Cgd = Gate to channel capacitance
Csb, Cdb = Source and drain- diffusion
capacitance to bulk
Cgb = Gate to bulk capacitance
Total gate capacitance Cg of an MOS transistor is
given as
Cg = Cgb + Cgs +Cgd
CMOS VLSI Design
The behavior of the gate capacitance of a MOS
device can be explained in terms of the following
simple models in the three regions of operation
Off region: Cgb can be modeled as series
combination of Co and Cdep
Non-seturated region: here Cgb effectively falls to
zero and Gate to channel capacitances are
estimated as
CMOS VLSI Design

Saturation region: the drain region of the channel
is pinched off causing Cgd to be zero, Cgs
increases to approximately
CMOS VLSI Design

CMOS VLSI Design

Some of the components of the gate capacitance
are highly voltage dependent
The overall gate capacitance is approximately
equal to the intrinsic gate oxide capacitance for
all values of gate voltage
The only region where this does not hold is
around the threshold voltage of the transistor
Since transistor in digital circuits switch through
this region rapidly
We can conservatively approximate Cg = Co
CMOS VLSI Design
Another way of stating this approximation is
Cg = Cox . A
Where Cox is the thin oxide capacitance per unit
area given as
CMOS VLSI Design

Diffusion capacitance
Diffusion regions form source and drain terminals
of MOS device and also used as wires
All diffusion regions have a capacitance to
substrate that depends on the voltage between
the diffusion regions and substrate (or well)
As well as on the effective area of the depletion
region separating diffusion and substrate(or well)
The diffusion capacitance Cd is proportional to
the total diffusion to substrate junction area
CMOS VLSI Design
Diffusion capacitance is a function of base area and

also of the area of the sidewall periphery because
the diffusion region has a finite depth
sidewall capacitance can be characterized (assuming
constant depth diffusion) by a periphery capacitance
per unit length
The total Cd can be represented as
Cd= Cja * (ab) + Cjp * (2a+2b)
Where Cja= Junction capacitance/Sq .um
Cjp= periphery capacitance/ um
a= width of diffusion region
b= extent of diffusion region
CMOS VLSI Design
CMOS VLSI Design

CMOS VLSI Design

Since the thickness of depletion layer depends on the
voltage across the junction
Both Cja and Cjp are functions of junction voltage Vj
A general expression that decides the junction
capacitance is
Where Vj = junction Voltage

Cjo= Zero bise capacitance (Vj=0)
= Built in junction potential=0.6 Volt
m = constant which depends on distribution of
impurity near junction (0.3 to 0.5)
CMOS VLSI Design
Routing capacitance between metal and poly layers
and the substrate can be approximated using a
parallel plate model
where A = area of the parallel plate capacitor

t = insulator thickness
Parallel plate approximation ignores fringing fields
The effect of the fringing fields is to increase the
effective area of the
Consequently poly and metal lines will actually have
a higher capacitance(up to twice as large) than
predicted by the model
CMOS VLSI Design
Interlayer capacitance such as metal-poly
capacitance is also enhanced by fringing
CMOS VLSI Design

A factor taken into account for small geometries
when using parallel plate model is that a drawn
shape (on mask) will not be same as the actual
physical shape produced on Silicon
CMOS VLSI Design

CMOS Switching Characteristics

Transient switching times are used to calculate
data throughput rates and are also important in
system timing
Switching times are determined by two circuit
properties: transistor current flow levels and
parasitic capacitances
Both are set by the chip design parameters, and
are sensitive to the transistor aspect ratios, layout
geometry, and logic routing
CMOS VLSI Design

To model the basic problem, we consider the output
capacitance Cout
This capacitance represents the total capacitance at
the output node, and consists of contributions from
the MOSFETs and the external network
For the analytic calculations, Cout is assumed to be a
linear, time-invariant (LTI) quantity
Moreover, one is able to clarify the design issues
that affect CMOS designs in general
It is important to note, however, that Cout has both
linear and non-linear (voltage-dependent) terms that
are needed to deal with
CMOS VLSI Design
CMOS VLSI Design


Switching performance of CMOS digital circuits
are characterized by the time intervals required
to charge and discharge capacitors at output
nodes
CMOS inverter use transistors to provide current
flow paths between the power supply (Mp) and
ground (Mn)
All switching times are thus set by the current
levels and the value of Cout
CMOS VLSI Design

Figure shows the inverter input and output
voltages as functions of time
The input waveform Vin(t) has been taken to
have idealized step characteristics
This choice simplifies the calculations and also
provides a standard reference
When the input voltage is low with Vin = 0 the
output voltage is high at a value of Vout = Vdd
CMOS VLSI Design


This corresponds to the case where the nFET is OFF,
while the pFET is ON and provides the connection to
the power supply
Changing the input voltage to high value Vin = Vdd
reverses this; now the nFET is active while the pFET
is in cutoff
The capacitor Cout discharges to 0v through Mn, and
the output voltage decays to a final value of Vin = 0v
as shown
The switching time associated with this decay is the
output high-to-low time tLH If the input voltage is
returned to a low voltage Vin = 0v the nFET is
CMOS VLSI Design

If the input voltage is returned to a low voltage
Vin = 0v the nFET is driven into cutoff while the
pFET reconnects Cout to the power supply
This allows Cout to charge to a final voltage of
Vout = Vdd in a characteristic time tLH the output
low-to-high time
CMOS VLSI Design

CMOS VLSI Design


The importance of the switching times tHL and
tLH is obvious
They represent the times required for the output
to stabilize to a final value in response to changes
of the input voltage
These are limiting factors in the performance of a
digital CMOS logic circuit
It is important that the two quantities can be
treated as being distinct, and that each depends
on the behaviour of only one MOSFET
CMOS VLSI Design

Rise time: time for a waveform to rise from 10%
to 90% of its steady-state value
Fall time: time for a waveform to fall from 90%
to 10% of its steady-state value
Delay time: time difference between input
transition (50%) and the (50%) output level (this
is the time taken for a logic transition to pass
from input to output)
CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

Integrating from Vo=0.9VDD to Vo=VDD-Vtn
CMOS VLSI Design


When the n device begins to operate in the
linear region, the discharge current is no
longer constant
The time taken to discharge the capacitor
voltage from (VDD - Vtn) to 0.1 VDD can be
obtained as
CMOS VLSI Design

CMOS VLSI Design


Thus the complete term for the fall time Tf is
Assuming that Vtn = 0.2 VDD (in a 5 volt process

Vtn=1V and Vtp= -1V) then Tf can be approximated
by
CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design


Due to symmetry of the CMOS circuit a similar
approach may be used to obtain the rise time(tr)
With Vtp =0.2VDD this reduces to
CMOS VLSI Design


For equally sized n and p transistor where
The relation between fall time and rise time is

given as
Thus the fall time is faster than the rise time,
primarily due to different carrier motilities
associated with the p and n devices
CMOS VLSI Design


Therefore if we want to have approximately the
same rise and fall time for an inverter we need
This implies that the channel width for the pdevice must be increased to approximately two
times that of the n device, so
This depends on process parameters

CMOS VLSI Design
CMOS VLSI Design

Transistor Sizing(Similar stage loads)

If we want to have approximately the same rise
and fall time for an inverter, we must make
This increases layout area and dynamic power
dissipation
In some cascaded structures it is possible to use
minimum size devices without compromising the
switching response
This is illustrated in the following analysis, in
which the delay response for an inverter pair with
Wp = 2Wn is given as
CMOS VLSI Design
CMOS VLSI Design

Where R is the effective on resistance of a unit sized

transistor
Ceq = Cg + Cd is the capacitance of a unit sized gate and
drain region
CMOS VLSI Design
CMOS VLSI Design


The inverter pair delay with Wp = Wn is
Where R is the effective on resistance of a unit

sized transistor
Ceq = Cg + Cd is the capacitance of a unit sized
gate and drain region
CMOS VLSI Design

Thus we find similar responses are obtained for
the two different conditions
It is important to not that changes in ratio also
affect inverter threshold voltage Vinv, the relation
defining Vinv is given by
CMOS VLSI Design

CMOS VLSI Design

Transistor Sizing(Pseudo nMOS)
CMOS VLSI Design

Transistor Sizing(Pseudo nMOS)

A simple model of pseudo n MOS inverter is
taken to model the problem
This uses the 3:1 transistor width ratio
The approximate delay for a pair of inverter is
Where R is the effective on resistance of a unit

sized transistor
Ceq = Cg + Cd is the capacitance of a unit sized
gate and drain region
CMOS VLSI Design
Transistor Sizing(Cascaded stage loads)
CMOS VLSI Design

Transistor Sizing(Cascaded stage loads)

The stage ratio is the ratio used to multiply the
size of transistor sizes in successive stages
For optimum speed this ratio is 2.7, but value
from 2 to 10 may be used
CMOS VLSI Design

Conductor Sizing
CMOS VLSI Design

Power dissipation (Outline)

Power and Energy
Dynamic Power
Static Power
CMOS VLSI Design

Power and Energy

Power is drawn from a voltage source
attached to the VDD pin(s) of a chip.
Instantaneous Power:
P(t ) I (t )V (t )
T
E P(t )dt
Energy:
Average Power:
E 1
Pavg P(t )dt
T T 0
CMOS VLSI Design

Power in Circuit Elements

PVDD t I DD t VDD
VR2 t
PR t
I R2 t R
R
dV
EC I t V t dt C V t dt
dt
0
0
VC
C V t dV 12 CVC2
0
CMOS VLSI Design
Charging a Capacitor
When the gate output rises

Energy stored in capacitor is
2
EC 12 CLVDD
But energy drawn from the supply is
EVDD I t VDD dt CL
0
CLVDD
dV
VDD dt
dt
VDD
dV C V
2
L DD
Half the energy from VDD is dissipated in the pMOS transistor as

heat, other half stored in capacitor
When the gate output falls
Energy in capacitor is dumped to GND
Dissipated as heat in the nMOS transistor
CMOS VLSI Design
Switching Waveforms
Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz
CMOS VLSI Design

Switching Power
T
Pswitching
1
iDD (t )VDD dt
T 0
T
VDD
iDD (t )dt
T 0
VDD
Tfsw CVDD
T
CVDD 2 f sw
VDD
iDD(t)
fsw
CMOS VLSI Design

Activity Factor
Suppose the system clock frequency = f
Let fsw = af, where a = activity factor
If the signal is a clock, a = 1
If the signal switches once per cycle, a =
Dynamic power:
Pswitching a CVDD 2 f
CMOS VLSI Design
Short Circuit Current

When transistors switch, both nMOS and
pMOS networks may be momentarily ON at
once
Leads to a blip of short circuit current.
< 10% of dynamic power if rise/fall times are
comparable for input and output
We will generally ignore this component
CMOS VLSI Design

Power Dissipation Sources

Ptotal = Pdynamic + Pstatic
Dynamic power: Pdynamic = Pswitching + Pshortcircuit
Switching load capacitances
Short-circuit current
Static power: Pstatic = (Isub + Igate + Ijunct )VDD

Subthreshold leakage
Gate leakage
Junction leakage
CMOS VLSI Design
Dynamic Power Example

1 billion transistor chip
50M logic transistors
Average width: 12 l
Activity factor = 0.1
950M memory transistors

Average width: 4 l
Activity factor = 0.02
1.0 V 65 nm process
C = 1 fF/mm (gate) + 0.8 fF/mm (diffusion)
Estimate dynamic power consumption @ 1 GHz.

Neglect wire capacitance and short-circuit
current.
CMOS VLSI Design
Solution
Clogic 50 106 12l 0.025m m / l 1.8 fF / m m 27 nF
Cmem 950 106 4l 0.025m m / l 1.8 fF / m m 171 nF
Pdynamic 0.1Clogic 0.02Cmem 1.0 1.0 GHz 6.1 W
2
CMOS VLSI Design

Dynamic Power Reduction

Pswitching a CVDD 2 f
Try to minimize:
Activity factor
Capacitance
Supply voltage
Frequency
CMOS VLSI Design
Activity Factor Estimation

Let Pi = Prob(node i = 1)
Pi = 1-Pi
ai = P i * P i
Completely random data has P = 0.5 and a = 0.25
Data is often not completely random
e.g. upper bits of 64-bit words representing bank
account balances are usually 0
Data propagating through ANDs and ORs has

lower activity factor
Depends on design, but typically a 0.1
CMOS VLSI Design
Switching Probability
CMOS VLSI Design

Example
A 4-input AND is built out of two levels of
gates
Estimate the activity factor at each node if the
inputs have P = 0.5
CMOS VLSI Design

Clock Gating
The best way to reduce the activity is to turn
off the clock to registers in unused blocks
Saves clock activity (a = 1)
Eliminates all switching activity in the block
Requires determining if block will be used
CMOS VLSI Design

Capacitance
Gate capacitance
Fewer stages of logic
Small gate sizes
Wire capacitance
Good floorplanning to keep communicating blocks
close to each other
Drive long wires with inverters or buffers rather
than complex gates
CMOS VLSI Design
Voltage / Frequency
Run each block at the lowest possible voltage and
frequency that meets performance requirements
Voltage Domains
Provide separate supplies to different blocks
Level converters required when crossing
from low to high VDD domains
Dynamic Voltage Scaling
Adjust VDD and f according to

workload
CMOS VLSI Design
Static Power
Static power is consumed even when chip is
quiescent.
Leakage draws power from nominally OFF devices
Ratioed circuits burn power in fight between ON
transistors
CMOS VLSI Design

Static Power Example

Revisit power estimation for 1 billion
transistor chip
Estimate static power consumption
Subthreshold leakage
Normal Vt:
100 nA/mm
High Vt:
10 nA/mm
High Vt used in all memories and in 95% of logic gates
Gate leakage
Junction leakage
5 nA/mm
negligible
CMOS VLSI Design

Solution
Wnormal-Vt 50 106 12l 0.025m m / l 0.05 0.75 106 m m
Whigh-Vt 50 106 12l 0.95 950 106 4l 0.025m m / l 109.25 106 m m
I sub Wnormal-Vt 100 nA/m m+Whigh-Vt 10 nA/m m / 2 584 mA
I gate Wnormal-Vt Whigh-Vt 5 nA/m m / 2 275 mA
Pstatic 584 mA 275 mA 1.0 V 859 mW
CMOS VLSI Design
Subthreshold Leakage
For Vds > 50 mV
I sub I off 10
Vgs Vds VDD k Vsb

S
Ioff = leakage at Vgs = 0, Vds = VDD
CMOS VLSI Design
Typical values in 65 nm
Ioff = 100 nA/mm @ Vt = 0.3 V
Ioff = 10 nA/mm @ Vt = 0.4 V
Ioff = 1 nA/mm @ Vt = 0.5 V
= 0.1
k = 0.1
S = 100 mV/decade
Stack Effect
Series OFF transistors have less leakage
Vx > 0, so N2 has negative Vgs
Vx VDD
I sub I off 10
I off 10
Vx VDD Vx VDD k Vx
S
N2
Vx
N1
VDD
1 2 k
I sub I off 10
1 k
VDD
1 2 k
I off 10
VDD
S
Leakage through 2-stack reduces ~10x

Leakage through 3-stack reduces further
CMOS VLSI Design
Leakage Control
Leakage and delay trade off
Aim for low leakage in sleep and low delay in
active mode
To reduce leakage:
Increase Vt: multiple Vt
Use low Vt only in critical circuits
Increase Vs: stack effect
Input vector control in sleep
Decrease Vb
Reverse body bias in sleep

Or forward body bias in active mode
CMOS VLSI Design
Gate Leakage
Extremely strong function of tox and Vgs
Negligible for older processes

Approaches subthreshold leakage at 65 nm and below
in some processes
An order of magnitude less for pMOS than nMOS

Control leakage in the process using tox > 10.5
High-k gate dielectrics help
Some processes provide multiple tox
e.g. thicker oxide for 3.3 V I/O transistors
Control leakage in circuits by limiting VDD

CMOS VLSI Design
NAND3 Leakage Example

100 nm process
Ign = 6.3 nA
Ioffn = 5.63 nA
Igp = 0
Ioffp = 9.3 nA
Data from [Lee03]
CMOS VLSI Design

Junction Leakage
From reverse-biased p-n junctions
Between diffusion and substrate or well
Ordinary diode leakage is negligible

Band-to-band tunneling (BTBT) can be significant
Especially in high-Vt transistors where other leakage is
small
Worst at Vdb = VDD
Gate-induced drain leakage (GIDL) exacerbates

Worst for Vgd = -VDD (or more negative)
CMOS VLSI Design
Power Gating
Turn OFF power to blocks when they are idle
to save leakage
Use virtual VDD (VDDV)
Gate outputs to prevent
invalid logic levels to next block
Voltage drop across sleep transistor degrades

performance during normal operation
Size the transistor wide enough to minimize
impact
Switching wide sleep transistor costs dynamic

power
Only justified when circuit sleeps long enough
CMOS VLSI Design
CMOS Power dissipation

There are two components that establish
the amount of power dissipated in the
CMOS circuit
Static dissipation due to leakage current
Dynamic dissipation due to
Switching transient current
Charging and discharging of load
capacitances
CMOS VLSI Design
CMOS Power dissipation(Static)
CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design


When input = 0, P-device is ON and n device is
OFF
When input = 1, P-device is OFF and n device is
ON
It shows that one transistor is always OFF when
the gate is in either of these logic states
Since no current flows into the gate terminal,
and there is no DC current path from Vdd to Vss,
the resultant quiescent (steady state) current,
and hence the power Ps, is zero
CMOS VLSI Design

There is some small static dissipation due to
reverse bias leakage between diffusion regions
and the substrate
This can be modeled as parasitic diodes for a
CMOS inverter
The source- drain diffusions and p-well diffusion
form parasitic diodes
Since parasitic diodes are reverse biased, only
their leakage current contributes to static power
dissipation
CMOS VLSI Design

The leakage current is described by diode
equation
Where
CMOS VLSI Design


The static power dissipation is the product of the
device leakage current and supply voltage
Where
n = number of devices
CMOS VLSI Design

CMOS Power dissipation(Dynamic)

During transition from 0 to 1 or, alternatively
from 1 to 0, both n and p transistors are on for a
short period of time
This results in a short current pulse from Vdd to
Vss
Current is also required to charge and discharge
the output capacitive load
The current pulse results in a short circuit
dissipation which is dependent on the load
capacitance and gate design
CMOS VLSI Design
CMOS VLSI Design


The dynamic dissipation is given as
where
CMOS VLSI Design

CMOS VLSI Design

Charge sharing
In many structures a bus can be modeled as a
capacitor Cb
Sometimes the voltage on this bus is sampled
(latched) to determine the state of a given signal
Frequently, this sampling can be modeled by the
two capacitors Cs and Cb and a switch
In general, Cs is in some way related to the
switching element
CMOS VLSI Design

Charge sharing
CMOS VLSI Design

Charge sharing
The charge associated with each of the
capacitances prior to closing the switching can be
described as
And
The total charge Qt is then given by
CMOS VLSI Design

Charge sharing
The total capacitance Ct is given by
Therefore, when the switch is closed, the

resultant voltage Vr is
CMOS VLSI Design

Charge sharing
CMOS VLSI Design

Design Margining
When considering the various aspects of
determining a circuit's behaviour, we only allude
to the variations that might occur in this
behaviour given different operating conditions
In general, there are three different sources of
variationtwo environmental and one
manufacturing, These are:
Supply voltage
Operating temperature
Process variation
CMOS VLSI Design
Design Margining
One must aim to design a circuit that will reliably
operate over all extremes of these three variables
Failure to do so invites circuit failure, potentially
catastrophic system failure, and a rapid decline
in reliability (a loss of customers)
CMOS VLSI Design

Design Margining (Temperature)

As temperature increases, drain current changes
The junction temperature of a transistor is the
sum of the ambient temperature and the
temperature rise caused by power dissipation in
the package
This rise is determined by the power
consumption and the package thermal resistance
Table lists the ambient temperature ranges for
parts specified to commercial, industrial, and
military standards
CMOS VLSI Design

Parts must operate at the bottom end of the
ambient range unless they are allowed to warm
up before use
The junction temperature may significantly
exceed the maximum ambient temperature
Commonly commercial parts are verified to
operate with junction temperatures up to 110 to
125 C
CMOS VLSI Design

CMOS VLSI Design

Design Margining (Supply Voltage)

Systems are designed to operate at a nominal
supply voltage, but this voltage may vary for
many reasons including tolerances of the voltage
regulator, IR drops along supply rails, and di/dt
noise
The system designer may trade off power supply
noise against resources devoted to power supply
regulation and distribution
Typically the supply is specified at 10% around
nominal at each logic gate
CMOS VLSI Design
Design Margining (Supply Voltage)

In other words, the variation has a uniform
distribution with a half-range of 10% of VDD
Speed is roughly proportional to VDD, so to first
order this leads to 10% delay variations
Power supply variations also appear in noise
budgets
CMOS VLSI Design

Design Margining (Process variation)

Devices and interconnect have variations in film
thickness, lateral dimensions, and doping
concentrations
These variations occur from one wafer to another,
between dice on the same wafer, and across an
individual die
Variation is generally smaller across a die than
between wafers
CMOS VLSI Design


These effects are sometimes called inter-die and
intra-die variations
Intra-die variation is also called process tilt
because certain parameters may slowly and
systematically vary across a die
For example, if an ion implanter delivered a
greater dose nearer the centre of a wafer than
near the periphery, the threshold voltages might
tilt radially across the wafer
CMOS VLSI Design

For devices, the most important variations are
channel length L, oxide thickness tox, and
threshold voltage Vt
Channel length variations are caused by
photolithography proximity effects, deviations in
the optics, and plasma etch dependencies
Oxide thickness is well controlled and generally is
only significant between wafers
CMOS VLSI Design


Its effects on performance are often lumped into
the channel length variation
Threshold voltages vary because of different
doping concentrations and annealing effects,
mobile charge in the gate oxide, and discrete
dopant variations caused by the small number of
dopant atoms in tiny transistors
CMOS VLSI Design


For interconnect, the most important variations
are line width and spacing, metal and dielectric
thickness, and contact resistance
Line width and spacing, like channel length,
depend on photolithography and etching
proximity effects
Thickness may be influenced by polishing
Contact resistance depends on contact
dimensions and the etch and clean steps
CMOS VLSI Design
Reliability
Designing reliable CMOS chips involves
understanding and addressing the potential
failure modes
The reliability problems {hard errors) that cause
integrated circuits to fail permanently, include:
Electromigration
Self-heating
Hot carriers
Latchup
Overvoltage failure
CMOS VLSI Design
Reliability
CMOS VLSI Design

CMOS Logic gate design
Fan-in
Fan-out
Typical CMOS NAND and NOR delays
Transistor sizing
CMOS VLSI Design

Physical design of Simple logic gates

Layout for Inverter
Layout for NAND
Layout for NOR
CMOS VLSI Design

CMOS logic structures
CMOS complementary logic

BiCMOS logic
Pseudo-nMOS logic
Dynamic CMOS logic
Clocked CMOS logic
Pass transistor logic
CMOS Domino logic
CMOS VLSI Design

I/O Structures
The input/output (I/O) subsystem is
responsible for communicating data
between the chip and the external world
A good I/O subsystem has the following
properties:
Drives large capacitances typical of off-chip
signals
Operates at voltage levels compatible with
other chips
CMOS VLSI Design
I/O Structures
Provides adequate bandwidth
Limits slew rates to control high-frequency
noise
Protects chip against damage from
electrostatic discharge (ESD)
Protects against over-voltage damage
Has a small number of pins (low cost)
CMOS VLSI Design

I/O Structures
CMOS VLSI Design

I/O Structures
CMOS VLSI Design

I/O Structures
CMOS VLSI Design

I/O Structures
CMOS VLSI Design

I/O Structures
I/O pad design requires specialized analog
expertise and knowledge of process-specific
ESD structures
Thus, the system designer should obtain a
well-characterized pad library from the
processor or library vendor, that is suited to
the manufacturing process
Basic I/O pads include VDD and GND,
digital input, output, and bidirectional
pads, and analog pads
CMOS VLSI Design
I/O Structures
A pad consists of a square of top-level metal of
approximately 100 um on a side that is either
soldered to a bond wire connecting to the
package
The term pad sometimes refers to just the
metal square and other times to the complete
cell containing the metal, ESD protection
circuitry, and I/O transistors
Input and output pads usually contain built-in
receiver and driver circuits to perform level
conversion and amplification
CMOS VLSI Design
I/O Structures (Vdd and GND Pads)

Power and ground pads are simply squares of
metal connected to the package and the on-chip
power grid
Most high-performance chips devote about half
of their pins to power and ground
This large number of pins is required to carry
the high current and to provide low supply
resistance
One of the largest sources of noise in many
chips is the ground bounce caused when output
pads switch
CMOS VLSI Design
I/O Structures (Vdd and GND Pads)

The pads must rapidly charge the large external
capacitive loads, causing a big current spike and
high L di/dt noise
The problem is especially bad when many pins
switch simultaneously, as could be the case in a
64-bit off-chip data bus
Such busses should be interdigitated with many
power and ground pins to supply the output
current through a low-inductance path
In many designs, the dirty power and ground
lines serving the output pads are separated
from the main power grid to reduce the
coupling of I/O- related noise into the core
CMOS VLSI Design
I/O Structures (Output Pads)

First and foremost, an output pad must have sufficient
drive capability to deliver adequate rise and fall times
into a given capacitive load
If the pad drives resistive loads, it must also deliver
enough current to meet the required DC transfer
characteristics
Given a load capacitance (typically 2-50 pF) and a
rise/fall time specification, the output transistor widths
can be calculated or determined through simulation
Typically, these transistors must be very wide and are
folded into many legs
Output pads generally contain additional buffering to
reduce the load seen by the on-chip circuitry driving the
pad
CMOS VLSI Design
I/O Structures (Output Pads)

The method of logical effort tells us that the fastest
buffers are built from strings of inverters with
fanouts of about 4
In practice, a higher fanout (e.g., 6-8) gives nearly
as good delay while reducing the area and power
consumption of the buffer
The final stage may have an especially high fanout
because the edge rates in the external world are
normally an order of magnitude longer than those
on chip
However, the final stage must be large enough to
source or sink reasonable amounts of current with
a small voltage drop
CMOS VLSI Design
I/O Structures (Input Pads)

Input pads also contain an inverter or buffer as a
level of protection between the pad and core
circuitry
The buffer can perform some level conversion or
noise filtering as well
For example, an input pad might receive a TTL
signal with V0L = 0.4 V and V0H = 2.4 V, If the
pad operates at 5 V, it should use a LO-skewed
inverter with a trip point well below 2.4 V to
properly receive the signal
Pads can include pull-up or pulldown resistors to
place an unconnected pad in a certain state
CMOS VLSI Design
I/O Structures (Input Pads)

ESD Protection
CMOS VLSI Design

I/O Structures (Tristated Pads)

A bidirectional pad with an output driver that can be
tristated and an input receiver is shown in the figure
The output driver consists of independently controlled
nMOS and pMOS transistors
When the enable is '1,' one of the two transistors turns
ON
When the enable is '0,' both transistors are OFF so the
pad is tristated
This design is preferable to the four-transistor "totem
pole" tristate, when driving large capacitances because
it has only two rather than four huge transistors in the
final stage and the transistors
need only be half as wide
CMOS VLSI Design
CMOS VLSI Design

CMOS VLSI Design

I/O Structures (Analog Pads)

Analog inputs and outputs connect to simple
metal pads and then directly to the on-chip
analog circuitry without any digital buffer or
driver
Analog pads still require protection circuitry
The protection circuitry must be carefully
designed, so it does not degrade the bandwidth
or signal integrity of the analog components
This is achieved by minimizing the protection
diode area
RF pads are extremely demanding because any
extra load can compromise performance
CMOS VLSI Design
Low Power Design

Total power dissipation is the sum of the static
and dynamic dissipation components
Dynamic dissipation has been far greater than
static power when systems are active, and
hence, static power is often ignored, although
this will change as gate and sub-threshold leakage
increase
Power dissipation has become extremely
important to VLSI designers
CMOS VLSI Design
Low Power Design

For high-performance systems such as workstations
and servers, dynamic power consumption per chip is
often limited to about 150 W by the amount of heat
that can be managed with air-cooled systems and
cost-effective heatsinks
This number increases slowly with advances in
heatsink technology and can be increased
significantly with expensive liquid cooling, but has
not kept pace with the growing power demands of
systems
Therefore, performance may be limited by the
inability to cool huge systems with power-hungry
circuits operating at high speeds
CMOS VLSI Design
Low Power Design

For battery-based systems such as laptops, cell
phones, and PDAs, power consumption sets the
battery life of the product
In these systems, most or all of the switching
activity may be stopped in an idle or "sleep"
mode
Hence, in addition to dynamic power while
active, static power consumption may limit the
battery life while idle
CMOS VLSI Design
Low Power Design(Dynamic Power)

If a process is selected with sufficiently high
threshold voltages and oxide thicknesses, static
dissipation is small and dynamic dissipation usually
dominates while the chip is active
Dynamic power is reduced by decreasing the
activity factors, the switching capacitance, the
power supply, or the operating frequency
Activity factor reduction is very important, Static
logic has an inherently low activity factor
Clocked nodes such as the clock network and the
clock input to registers have an activity factor of 1
and are very power-hungry
CMOS VLSI Design

Dynamic circuit families have clocked nodes and a high
internal activity factor, so they are also costly in Power
Clock gating can be used to stop portions of the chip that
are idle
A large fraction of power is dissipated by the clock
network itself, so entire portions of the clock network can
be turned off where possible
The chip can also sense die temperature and cut back
activity if the temperature becomes too high
A drawback of activity factor reduction is that if the system
transitions rapidly from an idle mode with little switching
to a fully active mode, a large di/dt spike will occur, This
leads to noise in the power supply network
CMOS VLSI Design

Device-switching capacitance is reduced by
choosing small transistors
Minimum-sized gates can be used on non-critical
paths
Although Logical Effort finds that the best stage
effort is about 4, using a larger stage effort
increases delay only slightly and greatly reduces
transistor sizes
For example, buffers driving I/O pads or long
wires may use a stage effort of 8-12 to reduce the
buffer size
CMOS VLSI Design

Interconnect switching capacitance is most effectively
reduced through careful floorplanning, placing
communicating units near each other to reduce wire
lengths
Voltage has a quadratic effect on dynamic power,
therefore, choosing a lower power supply significantly
reduces power consumption
As many transistors are operating in a velocity-saturated
regime, the lower power supply may not reduce
performance as much as first-order models predict
Voltage can be adjusted based on operating mode; for
example, a laptop processor may operate at high voltage
and high speed when plugged into an AC adapter, but at
lower voltage and speedCMOS
when
on battery power
VLSI Design

If the frequency and voltage scale down in proportion, a
cubic reduction in power is achieved, For example, the
laptop processor may scale back to 2/3 frequency and
voltage to save 70% in power when unplugged
Frequency can also be traded for power, For example, in a
digital signal processing system primarily concerned with
throughput, two multipliers running at half speed can
replace a single multiplier at full speed
At first, this may not appear to be a good idea because it
maintains constant power and performance while doubling
area
However, if the power supply can also be reduced
because the frequency requirement is lowered, overall
power consumption goes
down
CMOS VLSI Design
Low Power Design (Static Power)

Static power reduction involves minimizing Istatic
Some circuit techniques such as analog current
sources and pseudo-nMOS gates intentionally
draw static power
They can be turned off when they are not
needed
Subthreshold leakage power is already a major
problem for battery-powered designs in the 180
nm generation and will be growing exponentially
as power supplies and threshold voltages are
scaled down in future processes
CMOS VLSI Design

Many low-power systems need high
performance while active and low leakage while
idle
The high-performance requirement entails
relatively low thresholds, which contribute
excessive leakage current in the idle mode
Selective application of multiple threshold
voltages can maintain performance on critical
paths with low- Vt transistors while reducing
leakage on other paths with high- Vt transistors
CMOS VLSI Design

Another way to control leakage is through the
body voltage using the body effect
For example, low-Vt devices can be used and a
reverse body bias (RBB) can be applied during
idle mode to reduce leakage
Alternatively, higher- Vt devices can be used,
and then a forward body bias (FBB) can be
applied during active mode to increase
performance
Threshold voltages vary from one die to another
on account of manufacturing variations
CMOS VLSI Design

An adaptive body bias (ABB) can compensate
and achieve more uniform transistor
performance despite the variations
In any case, the body bias should be kept to less
than about 0.5 V
Too much reverse body bias leads to greater
junction leakage through a mechanism called
band-to-band tunneling, while too much
forward body bias leads to substantial current
through the body to source diodes
CMOS VLSI Design

Applying a body bias requires additional power
supply rails to distribute the substrate and well
voltages
CMOS VLSI Design

CMOS VLSI Design


Reducing VDD in standby mode reduces the
drain-induced barrier lowering contribution to
leakage
It also decreases gate leakage in processes where
that component is important
The supply should be maintained at a high
enough level to preserve the state of the system
CMOS VLSI Design


Yet another method of reducing idle leakage current
in low-power systems is to turn off the power supply
entirely
This could be done externally with the voltage
regulator or internally with a series transistor
Multiple Threshold CMOS circuits (MTCMOS) use
low-Vt transistors for computation and a high- Vt
transistor as a switch to disconnect the power
supply during idle mode
The high- Vt device is connected between the true
VDD and the virtual VDDV rails connected to the logic
gates
CMOS VLSI Design
CMOS VLSI Design

CMOS Design Methods

The manner in which the designer go about
designing a particular system, chip, or circuit can
have a profound impact on both the effort expended
and the outcome of the design
IC designers have developed and adapted strategies
from allied disciplines such as software engineering
to form a cohesive set of principles to increase the
likelihood of timely, successful designs
While the broad principles of design have not
changed in decades, the details of design styles and
tools have evolved along with advances in
technology and increasing levels of productivity
CMOS VLSI Design
CMOS Design Methods
CMOS VLSI Design

CMOS Design Methods

An integrated circuit can be described in terms of
three domains:
(1) the behavioural domain
(2) the structural domain
(3) the physical domain
The behavioral domain specifies what we wish to
accomplish with a system
The structural domain specifies the interconnection
of components required to achieve the behavior we
desire
The physical domain specifies how to arrange the
components in order to connect them, which in turn
allows the required behavior
CMOS VLSI Design
CMOS Design Methods

In each of these domains there are a number of
design options that can be selected to solve a
particular problem
For instance, at the behavioral level, we can choose
the wireless standard and the format in which data is
transmitted by the sensor radio
In the structural domain, we can select which
particular circuit style, logic family, or clocking
strategy to use
At the physical level, we have many options about
how the circuit is implemented in terms of chips,
boards, and enclosures
CMOS VLSI Design
CMOS Design Methods

These domains can further be hierarchically
divided into different levels of design abstraction
Classically, these have included the following for
digital chips:
Architectural or functional level
Logic or Register Transfer level (RTL)
Circuit level
CMOS VLSI Design

CMOS Design Methods
CMOS VLSI Design

Design Strategies
The viability of an IC is in large part affected by the
productivity that can be brought to bear on the
design
This in turn depends on the efficiency with which the
design can be converted from concept to
architecture, to logic and memory, to circuit, and
ultimately to physical layout
A good VLSI design system should provide for
consistent descriptions in all three description
domains (behavioral, structural, and physical) and at
all relevant levels of abstraction (e.g., architecture,
RTL/block, logic, circuit)
CMOS VLSI Design
Design Strategies
The means by which this is accomplished can be
measured in various terms that differ in
importance based on the application
These parameters can be summarized in terms of:
Performancespeed, power, function, flexibility
Size of die (hence, cost of die)
Time to design (hence, cost of engineering and
schedule)
Ease of verification, test generation, and
testability (hence, cost of engineering and
schedule)
CMOS VLSI Design
Design Strategies
Design is a continuous tradeoff to achieve
adequate results for all of the parameters
As such, the tools and methodologies used for a
particular chip will be a function of these
parameters, Certain end results have to be met
(i.e., the chip must conform to certain
performance specifications)
Other constraints may depend on economics
(i.e., size of die affecting yield) or even
subjectivity (i.e., what one designer finds easy,
another might find incomprehensible)
CMOS VLSI Design
Design Strategies
Given that the process of designing a system on
silicon is complicated, the role of good VLSI-design
aids is to reduce this complexity, increase
productivity, and assure the designer of a working
product
A good method of simplifying the approach to a
design is by the use of constraints and abstractions
By using constraints, the tool designer has some
hope of automating procedures and taking a lot of
the "legwork" (effort) out of a design
By using abstractions, the designer can collapse
details and arrive at a simpler object to handle
CMOS VLSI Design
Design Strategies (Hierarchy)

The use of hierarchy, or "divide and conquer,"
involves dividing a system into modules, then
repeating this process on each module until the
complexity of the sub modules is at an appropriately
comprehensible level of detail
This may entail stopping at a level where a prebuilt
component is available for the particular function
The process parallels the software strategy in which
large programs are split into smaller and smaller
sections until simple subroutines with well-defined
behavior and interfaces can be written
In the case of predefined modules, the design task
involves using library code intended for the required
function
CMOS VLSI Design
Design Strategies (Hierarchy)

The notion of "parallel hierarchy" can be used to
aggregate descriptions in each of the behavioral,
structural, and physical domains that represent a design
(parallel hierarchy means a hierarchynot necessarily
identicalis used in each domain)
Equivalency tools can ensure the consistency of each
domain, Because these tools can be applied hierarchically,
you can progress in verification from the bottom to the top
of a design, checking each level of hierarchy where
domains are intended to correspond
For instance, a RISC processor core can have an HDL model
that describes the behavior of the processor; a gate netlist
that describes the type and interconnection of gates
required to produce the processor; and a placement and
routing description that describes how to physically build
the processor in a given process
CMOS VLSI Design
Design Strategies (Regularity)

Hierarchy involves dividing a system into a set of
submodules, however, hierarchy alone does not
solve the complexity of the problem
For instance, we could repeatedly divide the
hierarchy of a design into different submodules but
still end up with a large number of different
submodules
With regularity as a guide, the designer attempts to
divide the hierarchy into a set of similar building
blocks
Regularity can exist at all levels of the design
hierarchy
CMOS VLSI Design
Design Strategies (Regularity)

Regularity aids in verification efforts by reducing
the number of subcomponents to validate and
by allowing formal verification programs to
operate more efficiently
Design reuse depends on the principle of
regularity to use the same virtual component in
multiple places or products
CMOS VLSI Design

Design Strategies (Modularity)

The tenet of modularity states that modules have
well-defined functions and interfaces
If modules are "well-formed," the interaction with
other modules can be well characterized
First of all, a clearly defined interface is required In
the IC case, this corresponds to a clearly defined
behavioral, structural, and physical interface that
indicates the function as well as the name, signal
type, and electrical and timing constraints of the
ports on the design
Reasonable load capacitance and drive capability
should be required for I/O ports
CMOS VLSI Design

Too large a fan-in or too small a drive capability can
lead to unexpected timing problems that take effort
to solve, where we are trying to minimize effort
For noise immunity and predictable timing, inputs
should only drive transistor gates, not diffusion
terminals
The physical interface specification includes such
attributes as position, connection layer, and wire
width
In common with HDL descriptions, we usually
classify ports as inputs, outputs, bidirectional, power,
or ground
CMOS VLSI Design

In addition, one should note whether a port is
analog or digital
Modularity helps the designer clarify and
document an approach to a problem, and also
allows a design system to more easily check the
attributes of a module as it is constructed (i.e.,
outputs are not shorted to each other)
The ability to divide the task into a set of welldefined modules also aids in System-On-Chip
(SOC) designs where a number of IP sources
have to be interfaced to complete a design
CMOS VLSI Design
Design Strategies (Locality)

By defining well-characterized interfaces for a
module, we are effectively stating that other than
the specified external interfaces, the internals of
the module are unimportant to other modules
In this way we are performing a form of
"information hiding" that reduces the apparent
complexity of the module
In the software and HDL world, this is paralleled
by a reduction of global variables to a minimum
CMOS VLSI Design
Design Strategies (Locality)

Increasingly, locality often means temporal
locality or adherence to a clock or timing protocol
One of the central themes of temporal locality is
to reference all signals to a clock
Thus, input signals are specified with required
setup and hold times relative to the clock, and
outputs have delays related to the edges of the
clock
CMOS VLSI Design

Design Strategies
CMOS VLSI Design

Design Methods
A designer has a range of design methods that
can be used to implement a CMOS system
Designer concentrate on the target of the design
method, in contrast to the design flow used to
build a chip
The base design methods are arranged roughly in
order of "increased investment," which loosely
relates to the time and cost it takes to design and
implement the system
CMOS VLSI Design
Design Methods
It is important to understand the costs,
capabilities, and limitations of a given
implementation technology to select the right
solution
For instance, it is futile to design a custom chip
when an off-the-shelf solution that meets the
system criteria is available for the same or lower
cost
CMOS VLSI Design

Design Methods
Many times, the most practical method to solve a
system design problem is to use a standard
microprocessor or digital signal processor (DSP)
There are many single-chip microprocessors with
built-in RAM and EEROM/EPROM available in the
market
For example, the PIC family of processors from
Microchip offers a wide range of clock speeds,
memory sizes, and analog I/O capability (ADCs) in
a small package
CMOS VLSI Design
Design Methods
For more signal-intensive problems, classical DSPs
can be employed
Microprocessors provide great flexibility because
systems can be upgraded in the field through
software patches
Do not underestimate the cost of software
development for microprocessor-based systems
CMOS VLSI Design

Design Methods
Even when one decides to build a system with an
off-the-shelf microprocessor, one should consider
the possibility of eventual integration
For example, if the product becomes very
successful and the designer wants to reduce costs
by integrating it into a single system-on-chip
rather than building it as a board with a
microprocessor and various support chips, one
will need a microprocessor that is available in
embedded form so that one can keep the
software
CMOS VLSI Design
Design Methods (Programmable Logic)

Often, the cost, speed, or power dissipation of a
microprocessor may not meet system goals and
an alternative solution is required
A variety of programmable chips are available
that can be more efficient than general purpose
microprocessors yet faster to develop than
dedicated chips:
Chips with programmable logic arrays
Chips with programmable interconnect
Chips with reprogrammable logic and
interconnect
CMOS VLSI Design

The system designer should be familiar with these
options for two reasons:
First, it allows the designer to competently assess
a particular system requirement for an IC and
recommend a solution, given the system
complexity, the speed of operation, cost goals,
time-to-market goals, and any other top-level
concerns
Second, it familiarizes the IC designer with
methods of making any chip reprogrammable at
the hardware level and hence both more useful
and of wider spread use
CMOS VLSI Design

The system designer should be familiar with these
options for two reasons:
First, it allows the designer to competently assess
a particular system requirement for an IC and
recommend a solution, given the system
complexity, the speed of operation, cost goals,
time-to-market goals, and any other top-level
concerns
Second, it familiarizes the IC designer with
methods of making any chip reprogrammable at
the hardware level and hence both more useful
and of wider spread use
CMOS VLSI Design
Semiconductor Chips
ASICs
Application Specific
Integrated Circuits
Microprocessors
Microcontrollers
CMOS VLSI Design

FPGA & CPLD
Programmable logic
An integrated circuit that can be
programmed/reprogrammed with a digital
logic of a curtain level.
Started at late 70s and constantly growing
Now available of up to approximately 700K
Flip-Flops in a single chip.
CMOS VLSI Design

Advantages
Short Development time

Reconfigurable
Saves board space
Flexible to changes
No need for ASIC expensive design and production
Fast time to market
Bugs can be fixed easily
Of the shelf solutions are available
CMOS VLSI Design

How it Began : PLA
Programmable Logic Array

First programmable device
2-level and-or structure
One time programmable
A
Programmable switch or fuse

f1 A B C A B C
OR plane
f2 A B A B C
AND plane
CMOS VLSI Design

SPLD - CPLD
Simple Programmable logic device
Single AND Level
Flip-Flops and feedbacks
Complex Programmable logic device

Several PLDs Stacked together
AND plane
Interconnection Matrix
MUX
I/O Block
Clock
Enable
f1
Flip-flop
PLD
Block
I/O Block
Select
PLD
Block
I/O Block
I/O Block
CMOS VLSI Design

PLD
Block
PLD
Block
FPGA - Field Programmable Gate Array

Programmable logic blocks (Logic Element LE)
Implement combinatorial and sequential logic. Based on LUT and DFF.
Programmable I/O blocks

Configurable I/Os for external connections supports various voltages and tri-states.
Programmable interconnect
Wires to connect inputs , outputs and logic blocks.
Logic
clocks
block
short distance local connections
long distance connections across chip
MUX
SET
I/O
N Input
LUT
I/O
I/O
a
b
Interconnection switches
d
CLR
clk
rst
CMOS VLSI Design

I/O
Configuring LUT
LUT is a RAM with data width of 1bit.
The contents are programmed at power up
Truth Table
Required Function
Programmed LUT
LUT
a
b
y a b c
CMOS VLSI Design
0
1
a,b,c
MUX
Special FPGA functions

Internal SRAM
Embedded Multipliers
and DSP blocks
Embedded logic analyzer
Embedded CPUs
High speed I/O (~10GHz)
DDR/DDRII/DDRIII SDRAM
interfaces
PLLs
CMOS VLSI Design
Flexibility
Comparison
Processors
Instruction Flexibility
90% Area Overhead
(Cache , Predictions)
FPGA
Device-wide flexibility
99% Area Overhead
(Configuration)
ASIC
No Flexibility
20% Area Overhead
(Testing)
CMOS VLSI Design
Speed , Power Efficiency
Usages
Digital designs where ASIC is not commercial

Reconfigurable systems
Upgradeable systems
ASIC prototyping and emulation
Education
CMOS VLSI Design

Manufacturers
Xilinx
Altera
Lattice
Actel
CMOS VLSI Design
Cyclone II - 20
18,752 LEs
52 M4K RAM blocks
240K total RAM bits
52 9x9 embedded multipliers
4 PLLs
16 Clock networks
315 user I/O pins
SRAM Based volatile configuration
CMOS VLSI Design
Cyclone II Internals
Embedded
Multipliers
Logic Array
M4K Memory
Blocks
I/O
Elements
Phase-Locked
Loops
CMOS VLSI Design
Cyclone II Logic Array

Build of LABs (logic array blocks) and
reconfigurable interconnect
CMOS VLSI Design

Cyclone II Logic Array Block (LAB)

16 LEs
Local Interconnect
LE carry chains
Register chains
LAB Control Signals
Direct link
interconnect
to left
2 CLK
2 CLK ENA
2 ACLR
1 SCLR
1 SLOAD
Fast Local Interconnect
4
4
4
4
4
4
CMOS VLSI Design

LE1
LE2
LE3
LE4
LE13
LE14
LE15
LE16
Direct link
interconnect
to right
Cyclone II Logic Element (LE)
CMOS VLSI Design

LE in Normal Mode
Suitable for general logic applications and
combinational functions.
CMOS VLSI Design
LE in Arithmetic Mode
Ideal for implementing adders, counters,
accumulators, and comparators.
CMOS VLSI Design
Cyclone II I/O Features
In/Out/Tri-state
Different Voltages and I/O Standards
Flip-flop option
Pull-up resistors
DDR interface
Series resistors
Bus keeper
Drive strength control
Slew rate control
Single ended/differential
CMOS VLSI Design
Cyclone II I/O Buffer

Three-State
Three-State
Control
Clock
Output
Output Path
Direct Input
Registered
Input
Input Path
Q
CMOS VLSI Design

Cyclone II Clocking
16 Global Clocks
4 PLLs
CMOS VLSI Design
Cyclone II PLL
3 Outputs
Clock Division
Clock Multiplication
Phase shift
CMOS VLSI Design
Memory
True Dual port RAM/ROM with dual clock
Variable data width
4K1, 2K2, 1K4, 5128, 5129, 25616, 25618

12832, 12836 (not available in true dual-port mode)
Input data and address are registered
1 Clock Write latency
Output data can be registered
Read latency of 1 or 2 clocks
Byte Enable
CMOS VLSI Design
Cyclone II Memory Structure
CMOS VLSI Design

Cyclone II Multipliers
18x18 or 2 9x9 modes
Up to 250MHz Performance
18
36
Sign_Y
Clock
Clear
CMOS VLSI Design
Output Registers
18
X
Input Registers
Sign_X
36
Delays and maximal frequency

Gate delay Delay of logic element
DFF delay tco (tsu - Very small)
Interconnect delay
1/Fmax = Tco + Tpdlogic + Tpd interconnect

Maximum Frequency is the fastest speed a circuit containing flip-flops can operate.
CMOS VLSI Design
Design flow
Specification
HDL
(VHDL , Verilog ,C , Simulink)
Timing constrains
Synthesis
Convert HDL to FPGA logic
(Quartus / Third party tools)
Timing constrains
Pin-out
Place and Route

(Quartus)
Timing Analyzer
(Quartus)
Simulation
(Modelsim / Quartus)
Timing Simulation if needed

(Modelsim / Quartus)
Bit-File
(FPGA configuration)
FPGA
(Debug using Signal TAP logic analyser)
CMOS VLSI Design

Design Rules
ASIC
FPGA
Adder
CLA
Ripple Carry
Latch
Commonly used
Not
Recommended
Gated clock Commonly used
Unacceptable
Tri-State
Commonly used
Only in I/O
Async RAM Commonly used
Only Small
CMOS VLSI Design

Design Economics
It is important for the IC designer to be able to
predict the cost and the time to design a
particular IC or sets of Ics
This can guide the choice of an implementation
strategy
System-level issues such as packaging and power
dissipation can affect the cost of an IC
CMOS VLSI Design

Design Economics
The selling price Stotal of an integrated circuit
may be given by
Stotal = Ctotal /(l-m)

Where
Ctotal is the manufacturing cost of a single IC to
the vendor
m is the desired profit margin
The margin has to be selected to ensure a profit
after overhead and the cost of sales (marketing
and sales costs) have been considered
CMOS VLSI Design
Design Economics
The costs to produce an integrated circuit are
generally divided into the following elements:
Non-recurring engineering costs (NREs)
Recurring costs
Fixed costs
CMOS VLSI Design

Non-recurring Engineering Costs (NREs)

Non-recurring engineering costs are those that
are spent once during the design of an integrated
circuit, They include
Engineering design cost Etotal
Prototype manufacturing cost Ptotal
These costs are amortized over the total number
of ICs sold
Ftotl, the total nonrecurring cost, is given by
Ftotal = Etotal + Ptotal
CMOS VLSI Design

The NRE costs can be amortized over the lifetime
volume of the chips
Alternatively, the non-recurring costs can be
viewed as an investment for which there is a
required rate of return
For instance, if $1M is invested in NRE for a chip,
then $10M has to be generated for a rate of
return of 10
CMOS VLSI Design


Engineering Costs: The cost of designing the IC
Etotal happens once during the chip design
process, The costs include:
Personnel cost
Support costs
CMOS VLSI Design

The personnel costs might include the labor for

architectural design
logic capture
simulation for functionality
layout of modules and chip
timing verification
DRC and tapeout procedures
test generation
CMOS VLSI Design

The support costs amortized over the life of the
equipment and the length of the design project
include
Computer costs
CAD software costs
Education or re-education costs
Costs can be drastically reduced by reusing

modules or acquiring fully completed modules
from an intellectual property vendor
CMOS VLSI Design

Prototype Manufacturing Costs: These costs
(Ptotal) are the fixed costs to get the first ICs
from the vendor, they include
The mask cost
Test fixture costs
Package tooling
CMOS VLSI Design

Recurring Costs
Once the development cost of an IC has been
determined, the IC manufacturer will arrive at a
price for the specific IC
A few large companies such as Intel, TI,
STMicroelectronics, Toshiba, and IBM have inhouse manufacturing divisions
Many fabless semiconductor companies
outsource their manufacturing to a silicon
foundry such as TSMC, Hitachi/UMC, IBM, LSI
Logic, or ST
This is a recurring cost; that is, it recurs every
time an IC is sold
CMOS VLSI Design
Recurring Costs
Another component of the recurring cost is the
continuing cost to support the part from a technical
viewpoint
Finally, there is "the cost of sales," which is the
marketing, sales force, and overhead costs
associated with selling each IC
In a captive situation such as the IBM
microelectronics division selling CPUs to the
mainframe division, this might be zero
The IC manufacturer will determine a part price for
an IC based on the cost to produce that IC and a
profit margin
The margin generally falls as the volume increases
CMOS VLSI Design
Recurring Costs
An expression for the cost to fabricate an IC is as
follows:
Rtotal = Rprocess + Rpackage + Rtest
where
Rpackage = package cost
Rtest = test costthe cost to test an IC is usually
proportional to the number of vectors
and the time to test
Rprocess= processing cost
CMOS VLSI Design
Fixed Costs
Once a chip has been designed and put into
manufacture, the cost to support that chip from
an engineering viewpoint may have a few sources
Data sheets describing the characteristics of the
IC have to be written, even for applicationspecific ICs that are not sold outside the company
that developed them
From time to time, application notes describing
how to use the IC may be needed
CMOS VLSI Design
Fixed Costs
In addition, specific application support may
have to be provided to help particular users
This is especially true for ASICs, where the
designer usually becomes the walking, talking,
data sheet and application note
Another ongoing task may be failure or yield
analysis if the part is in high volume and designer
want to increase the yield
CMOS VLSI Design

Fixed Costs
As a side comment, every chip or test chip
designed should have accompanying
documentation that explains what it is and how
to use it
This even applies to chips designed in the
academic environment because the time
between design submission and fabricated chip
can be quite large and can tax even the best
memory
CMOS VLSI Design
Schedule
At the outset of a system design project involving
newly designed ICs, it is important to estimate
the design cost and design time for that system
Estimating the cost can help designer determine
the method by which the ICs will be designed
Estimating the schedule is essential to be able to
select a strategy by which the ICs will be
available in the right time and at the right price
This task is usually the least well specified and
requires some experience
CMOS VLSI Design
Schedule
A number of fairly obvious methods for increasing
productivity, thereby improving schedules:
Using a high-productivity design method

Improving the productivity of a given technique
Decreasing the complexity of the design task by
partitioning
CMOS VLSI Design

Data Sheets and Documentation

A data sheet for an IC describes what it does and
outlines the specifications for making the IC work in
a system, such as power supply voltages, currents,
input setup times, output delay times, and clock
cycle times
The data sheet also includes package and pinout
details
A good habit to acquire is that of compiling a data
sheet for any chip designer might design
Not only is it the interface between the chip
designer and the board-level designer, but also it is
the interface to other members of the design team
CMOS VLSI Design

In particular, it is good practice and is mandatory
in industry to compile the data sheet for the chip
and give it to the ultimate customer before the
chip is fabricated
This prevents many undesirable scenarios that
can arise when a perfectly designed chip meets a
perfectly designed system
CMOS VLSI Design


The Summary: A summary of the chip includes
the following details to orient the user:
the designation and descriptive name of the chip
a concise description of what the chip does
a features list
a high-level block diagram of the chip function
CMOS VLSI Design


Pinout: The pinout section should contain a
description of the following pin attributes to
document the external interface of the chip:
name of the pin
type of pin (i.e., whether input, output, tristate,
digital, analog, etc.)
a brief description of the pin function
the package pin number
CMOS VLSI Design


Description of Operation: This section should
outline the operation of the chip as far as the
user of the chip is interested
Programming options, data formats, and control
options should be summarized
CMOS VLSI Design


DC Specifications: This section communicates the
power dissipation and required voltages for the
chip to correctly operate
The absolute maximum ratings should be stated
for:
supply voltage
pin voltages
junction temperature
CMOS VLSI Design


The style of each I/O (i.e.,TTL, CMOS, LVDS, ECL)
should be summarized and the following DC
specifications should be given over the operating
range (temperature and voltagei.e., mins and
maxes):
VIL and VIH for each input
VOL and VOH for each output (at a given maximum
drive current level)
the input loading for each input
quiescent current
leakage current
power-down current (if applicable)
any other relevant voltages and currents
CMOS VLSI Design

AC Specifications: The following timing
specifications should be presented:
setup and hold times on all inputs
clock (and all other relevant inputs) to output
delay times
other critical timing such as minimum pulse
widths
CMOS VLSI Design


Package Diagram: A diagram of the package with the
pin names attached should be supplied
Principles of Operation Manual: Although the data
sheet provides enough data to familiarize a user of a
particular chip with the device, it is good practice to
provide a Principles of Operation manual for internal
users that have to test the chip or build support
systems
User Manual: A User Manual should also be
provided
This is designed for use outside the group that
designed the chip and can be a "cut down" version of
the Principles of Operation manual
CMOS VLSI Design

Package Diagram: A diagram of the package with the
pin names attached should be supplied
Principles of Operation Manual: Although the data
sheet provides enough data to familiarize a user of a
particular chip with the device, it is good practice to
provide a Principles of Operation manual for internal
users that have to test the chip or build support
systems
User Manual: A User Manual should also be
provided
This is designed for use outside the group that
designed the chip and can be a "cut down" version of
the Principles of Operation manual
CMOS VLSI Design
CMOS Subsystem Design

Most chip functions can be divided into the
following categories:
Data path operators
Memory elements
Control structures
Special-purpose cells
I/O cells
Power distribution
Clock generation and distribution
Analog
CMOS VLSI Design

CMOS system design consists of partitioning the
system into subsystems of the types listed
Many options exist that make tradeoffs between
speed, density, programmability, ease of design,
and other variables
Datapath operators benefit from the structured
design principles of hierarchy, regularity,
modularity, and locality
They may use N-identical circuits to process N-bit
data
CMOS VLSI Design

Related data operators are placed physically
adjacent to each other to reduce wire length and
delay
Generally, data is arranged to flow in one
direction, while control signals are introduced in
a direction orthogonal to the dataflow
Common datapath operators include adders,
one/zero detectors, comparators, counters,
Boolean logic units, error-correcting code blocks,
shifters, and multipliers
CMOS VLSI Design
CMOS Subsystem Design (Addition)

Addition forms the basis for many processing
operations, from counting to multiplication to
filtering
As a result, adder circuits that add two binary
numbers are of great interest to digital system
designers
An extensive, almost endless, assortment of
adder architectures serve different speed/area
requirements
This begins with half adders and full adders for
single-bit addition
CMOS VLSI Design

It then goes to a plethora of carry-propagate
adders (CPAs) for the addition of multi-bit words
Finally, related structures such as subtracters and
multiple-input adders can be implemented
CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS Subsystem Design (Perity generator)
CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS Subsystem Design (Parity generator)
CMOS VLSI Design

Comparators
0s detector:
A = 00000
1s detector:
A = 11111
Equality comparator:
A=B
Magnitude comparator: A < B
CMOS VLSI Design

1s & 0s Detectors
1s detector: N-input AND gate
0s detector: NOTs + 1s detector (N-input NOR)
A7
A6
A3
A2
A5
A4
allones
A3
A2
allzeros
A1
A0
A1
A0
A7
A6
A5
A4
A3
A2
allones
A1
A0
CMOS VLSI Design

Equality Comparator
Check if each bit is equal (XNOR, aka equality
gate)
1s detect on bitwise equality
B[3]
A[3]
B[2]
A[2]
A=B
B[1]
A[1]
B[0]
A[0]
CMOS VLSI Design
Magnitude Comparator
Compute B A and look at sign
B A = B + ~A + 1
For unsigned numbers, carry out is sign bit
A B
C
B3
A B
A3
B2
A2
B1
A=B
A1
B0
A0
CMOS VLSI Design
CMOS Subsystem Design (Comparator)
CMOS VLSI Design

CMOS Subsystem Design (Comparator)
CMOS VLSI Design

Counters
Two commonly used types of counters are binary
counters and linear-feedback shift registers
An N-bit binary counter sequences through 2^N
outputs in binary order
It has a minimum cycle time that increases with
N
An N-bit linear-feedback shift register sequences
through up to 2^N-1 outputs in pseudo-random
order
CMOS VLSI Design
Counters
It has a short minimum cycle time independent
of N, so it is useful for extremely fast counters as
well as pseudo-random number generation
In general, divide-by-M counters (M < 2^N) can
be built using an ordinary N-bit counter and
circuitry to reset the counter upon reaching M
M can be a programmable input if an equality
comparator is used
CMOS VLSI Design

Counters
The simplest binary counter is the asynchronous
ripple-carry counter
It is composed of N registers connected in toggle
configuration, where the falling transition of each
register clocks the subsequent register
Therefore, the delay can be quite long
It has no reset signal, making it extremely difficult to
test
In general, asynchronous circuits introduce a whole
assortment of problems, so the ripple-carry counter
is studied mainly for historical interest and would
not be recommended for commercial designs
CMOS VLSI Design
Counters
CMOS VLSI Design

Counters
A general synchronous up/down counter uses a
resettable register and full adder for each bit
position
The cycle time is limited by the ripple-carry delay
and can be improved using any of the faster
adder techniques
CMOS VLSI Design

Counters
CMOS VLSI Design

Counters
If only an up counter (also called an incrementer)
is required, the full adder degenerates into a half
adder
Including an input multiplexer allows the counter
to load an initialization value
A clock enable is also often provided to each
register for conditional counting
CMOS VLSI Design

Counters
CMOS VLSI Design

linear-feedback shift register (LFSR)

A linear-feedback shift register (LFSR) consists of a
registers connected together as a shift register
The input to the shift register comes from the XOR of
particular bits of the register
On reset, the registers must be initialized to a nonzero
value (e.g., all l's)
LFSRs are used for high speed counters and pseudorandom number generators
The pseudo-random sequences are handy for built-in selftest and bit-error-rate testing in communications links
They are also used in many spread-spectrum
communications systems such as GPS and CDMA where
their correlation properties make other users look like
uncorrelated noise
CMOS VLSI Design

This LFSR is an example of a maximal-length shift
register because its output sequences through all
2^n-l combinations (excluding all 0's)
The inputs fed to the XOR are called the tap
sequence and are often specified with a
characteristic polynomial
For example, this 3-bit LFSR has the characteristic
polynomial 1 + x2 + x3 because the taps come
after the second and third registers
CMOS VLSI Design
CMOS VLSI Design

CMOS VLSI Design

Memory Array Architecture
CMOS VLSI Design

12T SRAM Cell

Basic building block: SRAM Cell
Holds one bit of information, like a latch
Must be read and written
12-transistor (12T) SRAM cell

Use a simple latch connected to bitline
46 x 75 l unit cell
bit
write
write_b
read
read_b
CMOS VLSI Design
6T SRAM Cell
Cell size accounts for most of array size
Reduce cell size at expense of complexity
6T SRAM Cell
Used in most commercial chips
Data stored in cross-coupled inverters
Read:
Precharge bit, bit_b
Raise wordline
Write:
Drive data onto bit, bit_b
Raise wordline
CMOS VLSI Design
6T SRAM Cell
bit
bit_b
word
CMOS VLSI Design


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CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

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MOS Transistor Switch

MOS Transistor Switch

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CMOS Logic (Inverter)

CMOS Logic (Inverter)

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CMOS Logic (NAND Gate)

CMOS Logic (NAND Gate)

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CMOS Logic (Combinational Logic)

CMOS Logic (Combinational Logic)

CMOS Logic (Combinational Logic)

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CMOS Logic (Combinational Logic)

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CMOS Logic (NOR Gate)

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CMOS Logic (Compound gates)

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CMOS Logic (Compound gates)

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Circuit and system representation

Circuit and system representation

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CMOS VLSI Design

Circuit and system representation

Circuit and system representation

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MOS Transistor Theory (Depletion)

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MOS Transistor Theory (Inversion)

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MOS Transistor Theory (Cut-off)

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MOS Transistor Theory (Linear)

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MOS Transistor Theory (Saturation)

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MOS Transistor Theory

MOS Transistor Theory(I-V Characteristics)

MOS Transistor Theory(I-V Characteristics)

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MOS Transistor Theory(I-V Characteristics)