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    RTN For SRC Instructions 1-Bus

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    professor_cuong

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    RTN For SRC Instructions 1-Bus

    Uploaded by

    professor_cuong
    1K views5 pages

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    RTN for SRC Instructions 1-Bus

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    1K views5 pages

    RTN For SRC Instructions 1-Bus

    Uploaded by

    professor_cuong

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    4-7 Chapter 4—Processor Design

    Abstract and Concrete RTN for SRC


    add Instruction
    Abstract RTN: (IR ← M[PC]: PC ← PC + 4; instruction_execution);
    instruction_execution := ( • • •
    add (:= op= 12) → R[ra] ← R[rb] + R[rc]:

    Tbl 4.1 Concrete RTN for the add R0


    31 0 〈31..0〉

    32
    Instruction 32 32-bit
    General
    31
    PC
    0

    Purpose Registers

    Step RTN
    T0 MA ← PC: C ← PC + 4; R31

    T1 MD ← M[MA]: PC ← C; IR

    T2 IR ← MD; IF
    A

    T3 A ← R[rb];
    IEx. A B
    MA

    T4 C ← A + R[rc]; ALU
    To memory subsystem

    T5 R[ra] ← C; C MD

    • Parts of 2 RTs (IR ← M[PC]: PC ← PC + 4;) done in T0


    • Single add RT takes 3 concrete RTs (T3, T4, T5)
    Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan
    4-9 Chapter 4—Processor Design

    Concrete RTN for Arithmetic Instructions:


    addi
    Abstract RTN:
    addi (:= op= 13) → R[ra] ← R[rb] + c2〈16..0〉
    {2's complement sign extend} :

    31 0 〈31..0〉
    Concrete RTN for addi: R0
    32 32-bit 32 31 0
    General PC
    Purpose Registers

    Step RTN
    T0. MA ← PC: C ← PC + 4; R31

    T1. MD ← M[MA]; PC ← C; IR

    T2. IR ← MD; Instr Fetch A

    T3. A ← R[rb]; Instr Execn. A B


    MA

    T4. C ← A + c2〈16..0〉 {sign ext.}; ALU


    To memory subsystem

    T5. R[ra] ← C; C MD

    • Differs from add only in step T4


    • Establishes requirement for sign extend hardware
    Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan
    4-11 Chapter 4—Processor Design

    Abstract and Concrete RTN for


    Load and Store
    ld (:= op= 1) → R[ra] ← M[disp] :
    st (:= op= 3) → M[disp] ← R[ra] :
    where
    disp〈31..0〉 := ((rb=0) → c2〈16..0〉 {sign ext.} :
    (rb≠0) → R[rb] + c2〈16..0〉 {sign extend, 2's comp.} ) :

    Tbl 4.3 The ld and St (load/store register from memory) Instructions

    Step RTN for ld RTN for st


    T0–T2 Instruction fetch
    T3 A ← (rb = 0 → 0: rb ≠ 0 → R[rb]);
    T4 C ← A + (16@IR〈16〉#IR〈15..0〉);
    T5 MA ← C;
    T6 MD ← M[MA]; MD ← R[ra];
    T7 R[ra] ← MD; M[MA] ← MD;

    Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan
    4-13 Chapter 4—Processor Design

    Concrete RTN for Conditional Branch

    br (:= op= 8) → (cond → PC ← R[rb]):


    cond := ( c3〈2..0〉=0 → 0: never
    c3〈2..0〉=1 → 1: always
    c3〈2..0〉=2 → R[rc]=0: if register is zero
    c3〈2..0〉=3 → R[rc]≠0: if register is nonzero
    c3〈2..0〉=4 → R[rc]〈31〉=0: if positive or zero
    c3〈2..0〉=5 → R[rc]〈31〉=1 ): if negative
    Tbl 4.4 The Branch Instruction, br
    Step RTN
    T0–T2 Instruction fetch
    T3 CON ← cond(R[rc]);
    T4 CON → PC ← R[rb];

    Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan
    4-15 Chapter 4—Processor Design

    Abstract and Concrete RTN for SRC Shift


    Right

    shr (:= op = 26) → R[ra]〈31..0〉 ← (n @ 0) # R[rb]〈31..n〉 :


    n := ( (c3〈4..0〉 = 0) → R[rc]〈4..0〉 : Shift count in register
    (c3〈4..0〉 ≠ 0) → c3〈4..0〉 ): or constant field of
    instruction
    Tbl 4.5 The shr Instruction

    Step Concrete RTN


    T0–T2 Instruction fetch
    T3 n ← IR〈4..0〉;
    T4 (n = 0) → (n ← R[rc]〈4..0〉);
    T5 C ← R[rb];
    T6 Shr (:= (n ≠ 0) → (C〈31..0〉 ← 0#C〈31..1〉: n ← n - 1; Shr) );
    T7 R[ra] ← C;

    step T6 is repeated n times


    Computer Systems Design and Architecture by V. Heuring and H. Jordan © 1997 V. Heuring and H. Jordan

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