International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.

5, October 2012

QUATERNARY LOGIC AND APPLICATIONS USING MULTIPLE QUANTUM WELL BASED SWSFETS
P. Gogna1,2, M. Lingalugari2, J. Chandy2, E. Heller3, E-S. Hasaneen4 and F. Jain2
2 3

Intel Massachusetts Corp, Hudson, MA, USA Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA
fcj@engr.uconn.edu

RSoft Design Group, Ossining, NY, 4Electrical Engineering, Minia University, Egypt

ABSTRACT
This paper presents Spatial Wavefunction-Switched Field-Effect Transistors (SWSFET) to implement efficient quaternary logic and arithmetic functions. Various quaternary logic gates and digital building blocks are presented using SWSFETs. In addition, arithmetic operation with full adder using novel logic algebra is also presented. The SWSFET based implementation of digital logic, cache and arithmetic block results in up to 75% reduction in transistor count and up to 50% reduction in data interconnect densities. Simulations of quaternary logic gates using the BSIM equivalent models for SWSFET channels are also described.

KEYWORDS
Quaternary Logic, Multi-Channel, Nanotechnology, SWSFETs

1. INTRODUCTION
The concept of SWSFET was introduced by Jain et al. [1]. SWSFETs offer multiple channels in a single transistor. In this paper we are discussing multichannel SWSFETs and presenting efficient quaternary logic gates and building blocks. The designs could potentially lower the device count by 75% for the same functionality and hence could significantly reduce the die size and data interconnect metal densities.

2. SPATIAL WAVE SWITCHED FIELD EFFECT TRANSISTOR (SWSFET)

In this section we will discuss different topologies of SWSFETs and related quantum mechanical simulations. Figure 1 shows the cross-sectional schematic of a two channel Si-SiGe SWSFET. Here the Si wells are grown on Si0.75Ge0.25 relaxed layer. It is a type-II structure with Si0.5Ge0.5 barrier layers. Figure 2 illustrates two channels corresponding to each quantum well. Generally, the quantum wells are asymmetric having different thicknesses. As the gate voltage VG is applied above threshold VTH1, the electrons are confined in well W2, the lower of the two wells. As the gate voltage is further increased (VG > VTH2), the electrons from W2 starts transferring to the upper well W1. Eventually, all electrons would belong to the upper level. Since the gate voltage is higher when the electrons transfer to the upper well W1, it has a greater density of electrons, and hence higher drain current.

DOI : 10.5121/vlsic.2012.3503

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

Figure 1. Layer topology of two quantum well SiGe-Si SWSFET.

Gate Metal

Gate Insulator Twin inversion channels at VTH1 and VTH2 Well 2 Well 1

qVG=-q(VTH+VG)

Figure 2. Schematic energy band diagram of two-well SWSFET structure.

2.1. Two-Well SWSFET

Figure 3(a)-(b) presents the quantum mechanical simulations for a two well SWSFET. At a gate voltage of -1.5V, the electron wavefunction is confined to W2. The wave function moves with changes in the gate voltage to 0.5V from lower well W2 to the upper well W1. Hence the carrier concentration also moves from lower to upper well, with this increased gate voltage.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

Figure 3 (a). Quantum mechanical simulations showing carriers available in lower well only.

Figure 3 (b). Quantum mechanical simulations showing carriers available in upper well only

2.2. Three-Well SESFET

Three-well SWSFET was designed with Ge wells and ZnSSe barrier layers. Unlike Fig. 1, it is a type I structure. Figure 4 shows the topology of the three-well design. Figure 5(a) and (b) present the quantum mechanical simulations for this structure. The carriers move from lower most well W3 to the upper most well W1with the change in gate voltage as show in figure 5(a) and (b). It should be noted that the gate voltage at which the wavefunction transfers, will change depending on the work function, gate insulator thickness and other parameters.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

Figure 4. Layer structure for three well SWSFETs

Figure 5 (a). Quantum mechanical simulations showing carriers available in lower most well of three well SWSFET.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

Figure 5 (b). Quantum mechanical simulations showing carriers available in upper most well of three well SWSFET.

2.3. Four-Well SWSFET:

Figure 6 presents the four well SWSFET structure with InGaAs wells and AlInAs as barriers. Figure 7 (a) and (b) shows the quantum mechanical simulations for this structure with movement of carriers from lower wells to the upper wells with the change in the gate voltage.

Gate

Sources S1-S4 n+

S1

S4

II-VI Gate Insulator InGaAs Well W1(2nm) AlInAs Barrier B1(1.5nm) InGaAs Well W2(2.5nm) AlInAs Barrier B2(1.5nm) InGaAs Well W3(3.0nm) AlInAs Barrier B3(1.5nm) InGaAs Well W4(3.5nm) AlInAs Barrier B4(20-100nm) P-InGaAs p-InP substrate

Drain n+

Figure 6. Design of four well SWSFET layer structure

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

Figure 7 (a). Quantum mechanical simulations showing carriers available in lower wells of four well SWSFET

Figure 7 (b). Quantum mechanical simulations showing carriers available in upper wells of four well SWSFET

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2.4. Fabricated SWS MOS Device

Figure 8 shows cross-sectional schematic of a fabricated SWS-MOS structure which is used to demonstrate carrier transfer as a funciton of the gate voltage. Figure 9 presents the measured C-V characteristics of this device. The existence of the peak in C-V is a proof of carrier transfer from one well to the other. The capacitance peak (gate voltage Vg=0 V) corresponds to charge (holes) in the lower well W2 as the device moves from threshold towards accumulation. The transfer of carriers to upper well W1 takes place at Vg=-2.0 V in this asymmetrically coupled quantum well InGaAs SWS-FET device. The inversion peak (~-3.8V) is not that pronounced. Simulation has verified the capacitance behaviour showing two peaks, one near the accumulation and the other near the inversion regime [1,4].
Gate II-VI Gate Insulator W1 (2nm) ` B1(1.5nm) W2 (5nm) B2 (100nm) P-GaInAs (200nm) P-InP substrate Ohmic Contact

GaInAs Well 1 AlInAs Barrier 1 GaInAs Well 2 AlInAs Barrier 2

Figure 8. Structure of fabricated two-well SWSFET with layer topology.

InGaAs 1965 SWS

8.00E-10 7.00E-10 Capacitance (F) 6.00E-10 5.00E-10 4.00E-10 3.00E-10 2.00E-10 1.00E-10 0.00E+00 -1 0 10 KHz 100 KHz 1 MHz

-2

1 Voltage (V)

Figure 9. C-V characteristics for a fabricated two-well InGaAs SWSMOS structure

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

3. QUATERNARY LOGIC, LOGIC GATES BLOCKS USING SWSFET.

3.1. Quaternary Logic

AND

OTHER DIGITAL BUILDING

In the last section we discussed SWSFET with multiple channels and the control over channel carrier concentration with change in gate voltages. The multiple channels in SWSFET offers design possibilities that are not available using single channel CMOS transistors. To develop efficient logic gates we decided to use the quaternary logic. Figure 10 compares the binary logic used in CMOS based digital cells, with the quaternary logic, we decided to use for SWSFET based cells.

Figure 10: Binary logic verses Quaternary logic with two inversions.

3.2. Logic Cells

In this section we are presenting the Quaternary logic building blocks along with implemented truth tables for the logic levels presented in sec 3.1. 3.2.1 NOT Gate The NOT gate implementation with SWSFET as well as CMOS is shown in figure 11. The related truth table is presented in table I. Two bit NOT gate implementation with CMOS binary logic requires four transistors as compared to one SWSFET using quaternary logic.

(a)

(b)

Figure 11: NOT Gates (a) Quaternary NOT gate implemented with SWSFET (b) Two binary NOT gates implemented with CMOS binary logic.
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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

Table I: Truth table implementing NOT Gate.

# 1 2 3 4 A (A1,A2) 0 (00) 1 (01) 2 (10) 3 (11) Y(Y1,Y2) 3 (11) 2 (10) 1 (01) 0 (00)

3.2.2 OR Gate Two bit OR gate implementations using SWSFET with quaternary logic and CMOS with binary logic are presented in figure 12. The truth table for the implemented OR-gates is presented in table II. Two bit OR gate implementation in CMOS based binary logic requires twelve transistors as compared to three transistors required SWSFET based implementation with quaternary logic.

(a) (b) Figure 12: OR Gates (a) Quaternary OR gate implemented using SWSFET (b) Two binary OR gates using CMOS. Table II: Truth table implementing OR Gate.
S/N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A(A1,A2) 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 B(B1,B2) 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 A OR B = Y(Y1,Y2) 00 01 10 11 01 01 11 11 10 11 10 11 11 11 11 11

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

3.2.3 AND Gate The AND gate implementations using SWSFET with quaternary logic and CMOS with binary logic are shown in figure 13. The related truth table is presented in table III. Two bit AND gate implementation in CMOS based binary logic requires twelve transistors as compared to three transistors required SWSFET based implementation with quaternary logic.

A1 Y1

B1

A2 Y2

B2

(a) (b) Figure 12: AND Gates (a) Quaternary AND gate implemented using SWSFET (b) Two binary AND gates using CMOS. Table III: Truth table implementing AND gate
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 3.2.4 Full Adder Arithmetic blocks are important and integral part of the processors. We are introducing quaternary full adder using SWSFET. Figure 14 shows full adder implemented using SWSFET with quaternary logic and using CMOS logic with binary logic. The truth table for the implemented full adder is presented in table IV. A simple full adder implementation in CMOS with binary logic for two bits requires eighty transistors as compared to eleven required for the
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A(A1,A2) 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11

B(B1,B2) 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11

A AND B = Y(Y1,Y2) 00 00 00 00 00 01 00 01 00 00 10 10 00 01 10 11

International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

adder presented here using SWSFET with quaternary logic. Also the longest delay path in SWSFET implementation is three transistors as while in CMOS based implementation it is five gates as shown in figure 14.

Table IV: Truth table implementing two bit Full adder.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Carry-in 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 B 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 Sum 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 01 10 11 00 10 11 00 01 11 00 01 10 00 01 10 11 Carry-Out 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

(a)

(b) Figure 14: Full adders (a) Two binary full adders implemented using CMOS and Quaternary full adder implemented using SWSFET

(b)

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

3.2.5 Quaternary Latch All the digital logic could be implemented using NOT, AND & OR gates. An additional building block for digital processors is a latch or flop. A quaternary latch implementation using SWSFET is shown in figure 15. The related truth table is presented in table V. A similar two bit latch implementation for two bits using CMOS binary logic would require about twelve transistors as compared to four required using SWSFET with quaternary logic.

Figure 15: Quaternary Latch implanted using SWSFET.

Table V: Truth table for a latch

# 1 2 Clock 0 1 D-Out D-Out Data-In

3.2.6 SRAM Cell Digital microprocessors today require massive amount of on die caches. Performance processors use over 50% of the die area for caches [5,6]. We are presenting the quaternary logic based cache implementation using SWSFET. Figure 16 shows the SRAM cell implementations using SWSFET with quaternary logic along with existing CMOS with binary logic. Two bit SRAM cell implementation in CMOS with binary logic requires eight transistors as compared to two transistors required using SWSFET with quaternary logic.

(a) (b) Figure 16: SRAM cells (a) Quaternary SRAM cells implemented using SWSFET (b) Two binary SRAM cells implanted using CMOS.
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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

In this section we have discussed basic building blocks of a digital micro processor. Also we have seen some comparison between the quaternary and binary implementation. Table VI gives the summary of transistor count comparison for implementations using SWSFET vs. CMOS for digital building blocks.

Table VI: Transistor count per two bits for digital building blocks.
S/N 1 2 3 4 5 6 Cell NOT AND OR Full Adder SRAM Latch CMOS Count 4 12 12 80 8 16 SWSFET Count 1 3 3 11 2 4

3.2.7 Integration with Binary logic We also designed a simple set of circuits to convert binary logic signals to quaternary logic signals and vice versa. Figure 17 presents these simple designs. This helps integrate CMOS based binary logic along with SWSFET based quaternary logic designs on the same die.

(a)

(b)

Figure 17: (a) Binary logic to quaternary logic conversion circuit (b) Quaternary logic to binary logic conversion circuit.

4. SIMULATIONS
We simulated the basic gates using the BSIM equivalent channel models for the quaternary logic using SWSFETs. Figures 18 and 19 give the simulation results for quaternary AND gate, OR gate and NOT gate, in agreement with corresponding truth tables presented in the previous section.

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International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.5, October 2012

(a) (b) Figure 18: Simulation results for quaternary gates using BSIM equivalent channel models in agreement with tables II and III (a) SWSFET based two input quaternary AND gate (b) SWSFET based two input quaternary OR gate.

Figure 19: Simulation results for SWSFET based quaternary inverter using BSIM equivalent channel models.

5. CONCLUSIONS
Spatial wavefunction-switched field-effect transistors (SWSFETs) have multiple coupled channels allowing the location of the charge to be selected by the gate voltage, and providing a pathway for implementing quaternary logic functions. This novel approach provides a methodology for processing two binary bits simultaneously. Furthermore, the SWSFET-based building blocks may be easily integrated with current CMOS technology. In particular, the conversion circuits presented in the paper may be used for this purpose. Finally, simulations are presented for basic SWS quaternary gates with BSIM equivalent models using Cadence Spectre simulator. Though manufacturing of multi-channel SWSFETs have challenges, they have the potential to significantly reduce the device count in the implementation of logic and cache in digital processors. This would help reduce the die cost and extend Moores law.

ACKNOWLEDGEMENTS
The authors would like to thank support of Office of Naval Research and National Science Foundation (ECS 0622065) to carry out the SWS research.

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REFERENCES
F. Jain, J. Chandy, and E. Heller, Proc. Lester Eastman Conf. on High Performance Devices, Int. J. High Speed Electronics and Systems, Vol. 20, pp. 641-652, September 2011. [2] F. C. Jain, B. Miller, E. Suarez, P-Y. Chan, S. Karmakar, F. Al-Amoody, M .Gogna, J. Chandy, and E. Heller, Spatial Wavefunction Switched (SWS) InGaAs FETs with II-VI Gate Insulators, J. Electronic Materials, 40, pp. 1717-1726, August 2011. [3] A. Sharma, Advanced Semiconductor Memories, John Wiley (2003). [4] El-Sayed Hasaneen, E. Heller, R. Bansal, and F. Jain, Modeling of Nonvolatile Floating Gate Quantum Dot Memory, Solid-State Electronics, 48, pp. 2055-2059, 2004. [5] M. Farrens, G. Tyson, and A.R. Pleszkun, A Study of Single-ChipProcessor/Cache Organizations for Large Number of Transistors, Proc. 21st Ann. Intl Symp. Computer Architecture, pp. 338-347, Apr. 1994. [6] Hong Wang, Tong Sun and Qing Yang Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags, IEEE Transactions on Computers, vol. 46, no. 11, November 1997 [7] Paul Harrison, Quantum Wells, Wires and Dots: Theoretical and Computational Physics, John Wiley (2002). [8] Alex Harwit, Effects of Electric Fields on quantum well Intersubband transitions, 1987 [9] Hirokatsu Shirahama and Takahiro Hanyu, Design of High-Performance Quaternary Adders Basedon Output-Generator Sharing, Proceedings of the 38th International Symposium on Multiple Valued Logic P: 8-13, 2008. [10] A. Srivastava, H.N. Venkata, Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS, INTEGRATION, the VLSI Journal, vol. 36, P 87-101, 2003 [11] K.W. Current, Current-mode multiple-valued logic circuits, IEEE J. Solid-State Circuits 29 (1994) 95107. [1]

Authors
Pawan Gogna received his B. Tech from Indian Institute of Technology, Kharagpur and M.S from The University of Connecticut. He is currently an engineer at Intel Massachusetts Corp and pursuing PhD at The University of Connecticut. He is a member of IEEE and IEEE SSCS. His research interests include nanotechnology, novel semiconductor devices and design architectures. M. Lingalugari is a doctoral student at the University of Connecticut. His research interests include fabrication of quantum dot gate FETs and simulation of logic circuits. Dr. J. Chandy received his S. B. from the Massachusetts Institute of Technology and Doctorate from University of Illinois. He is currently an Associate Professor and Associate Department Head at the University of Connecticut. His research interests are simulation of electronic and photonic devices and circuits. Dr. E. K. Heller received his doctorate from the University of Connecticut. He is currently R & D engineer at RSoft Design Group. His research interests are simulation of electronic and photonic devices and circuits. Dr. E-S. Hasaneen received his doctorate from the University of Connecticut. He is currently an Associate Professor in the Electrical Engineering Department at Minia University (Egypt). His research interests are simulation of quantum dot non-volatile memories, single electron transistors, and simulation of 22 nm mixed-signal circuits. Dr. F. C. Jain is a professor of Electrical and Computer Engineering at The University of Connecticut. He is a member of IEEE, SPIE, and APS. His research interests include quantum dot gate and channel FETs and memories exhibiting multi-state characteristics.

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