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DFT FAQs

The document discusses various topics related to testing digital circuits including differences between combinatorial and sequential ATPG, reasons for X'ing out inputs and masking outputs, false path and multi-cycle path differences, differences between DFT lockup latches and functional lockup latches, scan chain compression, JTAG registers, timing simulation failures, low coverage issues, scan chain tracing, pin constraints, excluding flops, linehold options, scan chain arrangement factors, clock gating cell structures, scan enable signals, differences between testmode and scanmode signals, and differences between test coverage and fault coverage.

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Sanmati Jain
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526 views2 pages

DFT FAQs

The document discusses various topics related to testing digital circuits including differences between combinatorial and sequential ATPG, reasons for X'ing out inputs and masking outputs, false path and multi-cycle path differences, differences between DFT lockup latches and functional lockup latches, scan chain compression, JTAG registers, timing simulation failures, low coverage issues, scan chain tracing, pin constraints, excluding flops, linehold options, scan chain arrangement factors, clock gating cell structures, scan enable signals, differences between testmode and scanmode signals, and differences between test coverage and fault coverage.

Uploaded by

Sanmati Jain
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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1. Diffrence between combinatorial and sequential ATPG.

2. Why Xout Input and Mask Outputs?


3. 4. 5. 6. 7. 8. What is flush and DC testmode False path,multicycle path Diffrence between DFT lockup latch and functional lockup latch Scan chain compression JTAG registers Timing simulation failures? no annotation for cells data race

9. Low coverage issues clock gating cells RAM functional model remove compression dc_reset mode 10. scan chain not traced.

11. what are general pin constraints

12. Exclude_xx_flops - excluding some flops during AC coz of false path

13. Linehold option, propxignore 14. scan chain compression length criterion compression routing becoms difficult other tests like mbist will take more time fault aliasing - two lines have same value no fault propagation 15. How scan chains are arranged..factors affecting it. how many scan pins are there 10 scan i/o and 200k flops so 20k flops per chain 16. clock gating cell structure

17. 18. 19. 20.

scan_en_i and scan_en_o values in ICTEST Diffrence between testmode signal and scanmode signals Why XOR logic in scan decompression Test coverage vs Fault coverage

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