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54ABT240 Octal Buffer/Line Driver With TRI-STATE Outputs: General Description

54ABT240 is an inverting Octal Buffer and Line Driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver. Features n Output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High Impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Connection Diagrams OE 1, OE 2 TRI-ST

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29 views

54ABT240 Octal Buffer/Line Driver With TRI-STATE Outputs: General Description

54ABT240 is an inverting Octal Buffer and Line Driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver. Features n Output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High Impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Connection Diagrams OE 1, OE 2 TRI-ST

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meroka2000
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© © All Rights Reserved
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54ABT240

Octal Buffer/Line Driver with TRI-STATE

Outputs
General Description
The ABT240 is an inverting octal buffer and line driver de-
signed to be employed as a memory address driver, clock
driver and bus oriented transmitter or receiver which pro-
vides improved PC board density.
Features
n Output sink capability of 48 mA, source capability of
24 mA
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Nondestructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9318801
Ordering Code
Military
Package
Number
Package Description
54ABT240J-QML J20A 20-Lead Ceramic Dual-In-Line
54ABT240W-QML W20A 20-Lead Cerpack
54ABT240E-QML E20A 20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Names Description
OE
1
, OE
2
TRI-STATE Output
Enable Inputs
I
0
I
7
Inputs
O
0
O
7
Outputs
TRI-STATE

is a registered trademark of National Semiconductor Corporation.


Pin Assignment
for DIP and Flatpak
DS100202-1
Pin Assignment
for LCC
DS100202-2
July 1998
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1998 National Semiconductor Corporation DS100202 www.national.com
Truth Tables
Inputs Outputs
(Pins 12, 14, 16, 18) OE
1
I
n
L L H
L H L
H X Z
Inputs Outputs
(Pins 3, 5, 7, 9) OE
2
I
n
L L H
L H L
H X Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
www.national.com 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature 65C to +150C
Ambient Temperature under Bias 55C to +125C
Junction Temperature under Bias
Ceramic 55C to +175C
V
CC
Pin Potential to
Ground Pin 0.5V to +7.0V
Input Voltage (Note 2) 0.5V to +7.0V
Input Current (Note 2) 30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State 0.5V to 5.5V
in the HIGH State 0.5V to V
CC
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
DC Latchup Source Current
(Across Comm Operating
Range) 150 mA
Over Voltage Latchup (I/O) 10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military 55C to +125C
Supply Voltage
Military +4.5V to +5.5V
Minimum Input Edge Rate (V/t)
Data Input 50 mV/ns
Enable Input 20 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol Parameter ABT240 Units V
CC
Conditions
Min Typ Max
V
IH
Input HIGH Voltage 2.0 V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage 1.2 V Min I
IN
= 18 mA
V
OH
Output HIGH Voltage 54ABT 2.5 V Min I
OH
= 3 mA
54ABT 2.0 V Min I
OH
= 24 mA
V
OL
Output LOW Voltage 54ABT 0.55 V Min I
OL
= 48 mA
I
IH
Input HIGH Current 5 A Max V
IN
= 2.7V (Note 4)
5 V
IN
= V
CC
I
BVI
Input HIGH Current Breakdown Test 7 A Max V
IN
= 7.0V
I
IL
Input LOW Current 5 A Max V
IN
= 0.5V (Note 4)
5 V
IN
= 0.0V
V
ID
Input Leakage Test 4.75 V 0.0 I
ID
= 1.9 A
All Other Pins Grounded
I
OZH
Output Leakage Current 50 A 0 5.5V V
OUT
= 2.7V; OE
n
= 2.0V
I
OZL
Output Leakage Current 50 A 0 5.5V V
OUT
= 0.5V; OE
n
= 2.0V
I
OS
Output Short-Circuit Current 100 275 mA Max V
OUT
= 0.0V
I
CEX
Output High Leakage Current 50 A Max V
OUT
= V
CC
I
ZZ
Bus Drainage Test 100 A 0.0 V
OUT
= 5.5V; All Others GND
I
CCH
Power Supply Current 50 A Max All Outputs HIGH
I
CCL
Power Supply Current 30 mA Max All Outputs LOW
I
CCZ
Power Supply Current 50 A Max OE
n
= V
CC
;
All Others at V
CC
or Ground
I
CCT
Additional I
CC
/Input Outputs Enabled 1.5 mA Max V
I
= V
CC
2.1V
Outputs TRI-STATE 1.5 mA Enable Input V
I
= V
CC
2.1V
Outputs TRI-STATE 50 A Data Input V
I
= V
CC
2.1V
All Others at V
CC
or Ground
I
CCD
Dynamic I
CC
No Load mA/ Max Outputs Open
(Note 4) 0.1 MHz OE
n
= GND, (Note 3)
One Bit Toggling, 50% Duty Cycle
Note 3: For 8 bits toggling, I
CCD
< 0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
3 www.national.com
AC Electrical Characteristics
Symbol Parameter 54ABT Units Fig.
No. T
A
= 55C to +125C
V
CC
= 4.5V5.5V
C
L
= 50 pF
Min Max
t
PLH
Propagation Delay 0.8 5.5 ns Figure 5
t
PHL
Data to Outputs 1.0 5.5
t
PZH
Output Enable 0.8 7.5 ns Figure 4
t
PZL
Time 0.8 7.7
t
PHZ
Output Disable 1.0 7.5 ns Figure 4
t
PLZ
Time 1.0 7.2
Capacitance
Symbol Parameter Typ Units Conditions
T
A
= 25C
C
IN
Input Capacitance 5.0 pF V
CC
= 0V
C
OUT
(Note 5) Output Capacitance 9.0 pF V
CC
= 5.0V
Note 5: C
OUT
is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
AC Loading
DS100202-3
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100202-4
FIGURE 2. Test Input Signal Levels
Amplitude Rep. Rate t
W
t
r
t
f
3.0V 1 MHz 500 ns 2.5 ns 2.5 ns
FIGURE 3. Test Input Signal Requirements
www.national.com 4
AC Waveforms
DS100202-6
FIGURE 4. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100202-7
FIGURE 5. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
5 www.national.com
6
Physical Dimensions inches (millimeters) unless otherwise noted
20-Terminal Ceramic Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
7 www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
LIFE SUPPORT POLICY
NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Franais Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: sea.support@nsc.com
National Semiconductor
Japan Ltd.
Tel: 81-3-5620-6175
Fax: 81-3-5620-6179
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
5
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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