Digital Electronic Systems Unit 11

SEQUENTIAL LOGIC SYSTEMS 1

Introduction
Up to now, we have considered only combinational logic circuits. Combinational logic
circuits are digital circuits where the output is totally dependent on the values of the present
inputs and does not depend on the sequence with which the inputs are applied, nor on any
past input values. We now consider sequential logic circuits. Sequential logic circuits are
digital circuits whose output depends on past as well as present input values. That is, the
output depends on memorising previous input combinations as well as the present input
combination. Sequential circuits can be categorised as clocked (synchronous) and unclocked
(asynchronous).
This unit provides a brief introduction to some basic sequential circuits and proceeds to
describe the latch in more detail.

Multivibrators
The most common electronic circuit for storing a single binary digit, or bit, is a Flip-Flop.
The Flip-Flop belongs to a family of sequential logic circuits known as multivibrators. There
are three types of multivibrators:
1. The bistable
2. The mononstable
3. The astable

1. There are two categories of bistable devices, the Latch and the Flip-Flop. Bistable
devices have two stable states called SET and RESET and can remain in either state
indefinitely, making them useful as storage devices. The basic difference between a
Latch and a Flip-Flop is the way in which they are changed from one state to the
other. The Flip-Flop is the basic building block for registers, counters and memories.
2. The monostable multivibrator, commonly called a one-shot, has only one stable state.
It produces a single controlled-width pulse in response to a triggering input. It is
generally used as a timing device and is used in the triggering circuit of an
oscilloscope.
3. The astable multivibrator has two unstable states and switches constantly, or
oscillates, from one state to the other. In digital electronics it is used to generate clock
pulses.

Digital Electronic Systems Unit 11

The S-R (Set-Reset) Latch

The fundamental building block of asynchronous sequential systems is the S-R Latch. A
latch is a bistable multivibrator, that is, it has two stable states. A latch reacts to changes of
input logic levels as they occur. (A Flip-Flop only reacts to inputs after it is enabled by a
clock pulse).
There are two possible implementations of an S-R Latch:

Active LOW S R Latch

The Active LOW implementation involves cross connecting two NAND gates.

Active HIGH S-R Latch

The Active HIGH implementation involves cross-connecting two NOR gates.

Active LOW

SR

Latch
S

Q
R

Active-Low Input

SR

Latch

The output from one gate is fed back into the input of the other gate. This produces
regenerative feedback. This means that the next state of the output is dependent on the
present state.
Let Q0 represent the present output state and let Q represent the next output state. Let Q 0
represent the inverse of the present output state and let Q represent the inverse of the next
output state.
Now consider the set of four input conditions.

Digital Electronic Systems Unit 11

Case 1:

S 1, R 1

Q=?
Q0

Q0

Q?

Then

Q 1.Q0 Q0 Q0

Case 2:

and

Q 1.Q0 Q0

. Therefore the outputs remain unchanged.

S 1, R 0

Q=?
Q0

Q0

Q?

The output of the lower NAND is Q 0.Q0 1 . This output is fed back as an input to the
upper NAND gate Q 1.Q0 1.1 0 . Therefore the latch is RESET.
Case 3:

S 0, R 1

Q=?

Q0

Q0

Q?

The output of the upper NAND is Q 0.Q0 1 . This output is fed back as an input to the
lower NAND gate Q 1.Q0 1.1 0 . Therefore the latch is SET.
Case 4:

S 0, R 0

Digital Electronic Systems Unit 11

Q=?
Q0

Q0

Q?

A low on either input to a 2-input NAND gate forces the output of that NAND gate to a logic
HIGH. Therefore, for the cross-coupled NAND gates, both outputs will go HIGH. (
Q 0.Q0 1 and Q 0.Q0 1 ).
The output is invalid because the complementary
operation of the outputs is violated.
Furthermore, if S and R change from the 00 condition to the 11 condition simultaneously,
the next state of the latch cannot be reliably predicted. As there is some small difference in
the propagation delay of the gates, one of the gates will dominate in its transition to the
LOW input state. This will force the output of the slower gate to remain high.
The operation of the Active Low
S
0
0
1
1

R
0
1
0
1

1
1
0
0

1
0
1
0

Q
NC
0
1
1

SR

NC
1
0
1

Latch may be summarised with a simple truth table.

Comments
No Change, Latch remains in current state
Latch RESET
Latch SET
INVALID condition

Active High S-R Latch

R
Q

A similar analysis can be performed on this circuit to produce the following truth table.

Digital Electronic Systems Unit 11

S
0
0
1
1

R
0
1
0
1

Q
NC
0
1
0

Comments
No Change, Latch remains in current state
Latch RESET
Latch SET
INVALID condition

NC
1
0
0

The only difference between this active high S-R latch and active low S R latch is for the
invalid condition the value of Q and Q is high for the former and low for the latter.
Consider now a sequence of actions carried out on an Active High S-R Latch.
ACTION
Assume
Apply 1 to S
Q0 becomes 1
Remove 1 from S
Apply 1 to S
Remove 1 from S
Apply 1 to R
Q0 becomes 0
Remove 1 from R
Apply 1 to S and R

Q0
0
0
1
1
1
1
1
0
0
0

S
0
1
1
0
1
0
0
0
0
1

R
0
0
0
0
0
0
1
1
0
1

Q
0
1
1
1
1
1
0
0
0
0

1
0
0
0
0
0
1
1
1
0

CONCLUSION
This is a stable state
Unstable; Q changes
This is a stable state
Stable state after SET
No change in Q
Stable state after SET
Unstable; Q changes
This is a stable state
Stable state after RESET
Unacceptable because Q = Q

These actions can be summarised in the following state diagram.

SR
01

SR
00
01

A
0

B
1

SR
10

SR
00
10

Digital Electronic Systems Unit 11

An example of a timing diagram for an S-R latch is given below.

S

Timing Diagram for an S-R latch

Summary symbols for an S-R latch are as follows. The latch on the left has active high
inputs and the latch on the right has active low inputs.

S
R

S
R

Gated S-R Latch

This latch is identical to an S-R latch except that the latch has an extra enable input. The
control inputs (S and R) are only allowed to change the state of the latch when the enable
input is asserted. Shown below are two implementations of a Gated S-R Latch.

Enable

Gate

Latch

Digital Electronic Systems Unit 11

#3

#1

Enable

#2

#4

Gate

Latch

Shown below are the truth table and an example of a timing diagram for the Gated S-R Latch.
En
0
1
1
1
1

S
X
0
0
1
1

R
X
0
1
0
1

Q
NC
NC
0
1
1

NC
NC
1
0
1

Note that for the invalid condition,

Comments
No Enable, this implies no response from the Latch
No Change, Latch remains in current state
Latch RESET
Latch SET
INVALID CONDITION
QQ0

if built using the AND-NOR configuration.

EN

Timing Diagram for a gated S-R latch

Digital Electronic Systems Unit 11

As can be seen from the timing diagram when the Gated S-R Latch is enabled, it acts
identically to the ungated Latch. The point of interest in this timing diagram is the stage at
which the Enable is Low and the S control input goes HIGH and there is no response from
the output Q. Then when the Enable goes HIGH the output Q is able to respond to the
current control input status. Like before, the Gated S-R Latch has a summarised symbol,
which is shown below.

EN
Q

Gated D latch
The gated D latch is the same as the gated S-R latch except that the set and reset inputs are
combined into one data input, D.
D

EN
R

Enable

Digital Electronic Systems Unit 11

Shown below are the truth table and an example of a timing diagram for a gated D latch.
En
0

D
X

Q
NC

NC

1
1

0
1

0
1

1
0

Comments
No Enable, this implies no response from the Latch.
The output remains in the current state
Latch RESET
Latch SET

EN

Timing Diagram for a gated D-latch

The gated D latch has a summary symbol, which is shown below.

D
Q
EN
Q