Family Data Sheet

MachXO Family Data Sheet
DS1002 Version 03.0, June 2013

Introduction
June 2013
Data Sheet DS1002
Flexible I/O Buffer
Features
Programmable sysIO buffer supports wide

range of interfaces:
LVCMOS 3.3/2.5/1.8/1.5/1.2
LVTTL
PCI
LVDS, Bus-LVDS, LVPECL, RSDS
Non-volatile, Infinitely Reconfigurable

Instant-on powers up in microseconds
Single chip, no external configuration memory
required
Excellent design security, no bit stream to
intercept
Reconfigure SRAM based logic in milliseconds
SRAM and non-volatile memory programmable
through JTAG port
Supports background programming of
non-volatile memory
sysCLOCK PLLs
Up to two analog PLLs per device
Clock multiply, divide, and phase shifting
System Level Support

IEEE Standard 1149.1 Boundary Scan
Onboard oscillator
Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
IEEE 1532 compliant in-system programming
Sleep Mode
Allows up to 100x static current reduction
TransFR Reconfiguration (TFR)

In-field logic update while system operates
Introduction
High I/O to Logic Density
256 to 2280 LUT4s

73 to 271 I/Os with extensive package options
Density migration supported
Lead free/RoHS compliant packaging
The MachXO is optimized to meet the requirements of

applications traditionally addressed by CPLDs and low
capacity FPGAs: glue logic, bus bridging, bus interfacing, power-up control, and control logic. These devices
bring together the best features of CPLD and FPGA
devices on a single chip.
Embedded and Distributed Memory

Up to 27.6 Kbits sysMEM Embedded Block
RAM
Up to 7.7 Kbits distributed RAM
Dedicated FIFO control logic
Table 1-1. MachXO Family Selection Guide
LCMXO256
LCMXO640
LCMXO1200
LCMXO2280
LUTs
Device
256
640
1200
2280
Dist. RAM (Kbits)
2.0
6.1
6.4
7.7
9.2
27.6
EBR SRAM (Kbits)

Number of EBR SRAM Blocks (9 Kbits)
VCC Voltage
1.2/1.8/2.5/3.3V
1.2/1.8/2.5/3.3V
1.2/1.8/2.5/3.3V
1.2/1.8/2.5/3.3V
Number of PLLs
Max. I/O
78
159
211
271
78
74
73
73
113
113
113
Packages
100-pin TQFP (14x14 mm)
144-pin TQFP (20x20 mm)
100-ball csBGA (8x8 mm)
78
74
132-ball csBGA (8x8 mm)
101
101
101
256-ball caBGA (14x14 mm)
159
211
211
256-ball ftBGA (17x17 mm)
159
211
324-ball ftBGA (19x19 mm)
211
271
2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1002 Introduction_01.5
Introduction
The devices use look-up tables (LUTs) and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, highsecurity, instant-on capabilities traditionally associated with CPLDs. Finally, advanced process technology and
careful design will provide the high pin-to-pin performance also associated with CPLDs.
The ispLEVER design tools from Lattice allow complex designs to be efficiently implemented using the MachXO
family of devices. Popular logic synthesis tools provide synthesis library support for MachXO. The ispLEVER tools
use the synthesis tool output along with the constraints from its floor planning tools to place and route the design in
the MachXO device. The ispLEVER tool extracts the timing from the routing and back-annotates it into the design
for timing verification.
1-2

Architecture
June 2013
Data Sheet DS1002
Architecture Overview
The MachXO family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). Some
devices in this family have sysCLOCK PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Figures 2-1,
2-2, and 2-3 show the block diagrams of the various family members.
The logic blocks are arranged in a two-dimensional grid with rows and columns. The EBR blocks are arranged in a
column to the left of the logic array. The PIO cells are located at the periphery of the device, arranged into Banks.
The PIOs utilize a flexible I/O buffer referred to as a sysIO interface that supports operation with a variety of interface standards. The blocks are connected with many vertical and horizontal routing channel resources. The place
and route software tool automatically allocates these routing resources.
There are two kinds of logic blocks, the Programmable Functional Unit (PFU) and the Programmable Functional
unit without RAM (PFF). The PFU contains the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PFF block contains building blocks for logic, arithmetic, ROM, and register functions. Both the PFU and
PFF blocks are optimized for flexibility, allowing complex designs to be implemented quickly and effectively. Logic
blocks are arranged in a two-dimensional array. Only one type of block is used per row.
In the MachXO family, the number of sysIO Banks varies by device. There are different types of I/O Buffers on different Banks. See the details in later sections of this document. The sysMEM EBRs are large, dedicated fast memory blocks; these blocks are found only in the larger devices. These blocks can be configured as RAM, ROM or
FIFO. FIFO support includes dedicated FIFO pointer and flag hard control logic to minimize LUT use.
The MachXO registers in PFU and sysI/O can be configured to be SET or RESET. After power up and device is
configured, the device enters into user mode with these registers SET/RESET according to the configuration setting, allowing device entering to a known state for predictable system function.
The MachXO architecture provides up to two sysCLOCK Phase Locked Loop (PLL) blocks on larger devices.
These blocks are located at either end of the memory blocks. The PLLs have multiply, divide, and phase shifting
capabilities that are used to manage the frequency and phase relationships of the clocks.
Every device in the family has a JTAG Port that supports programming and configuration of the device as well as
access to the user logic. The MachXO devices are available for operation from 3.3V, 2.5V, 1.8V, and 1.2V power
supplies, providing easy integration into the overall system.
www.latticesemi.com
2-1
DS1002 Architecture_01.5
Architecture
Figure 2-1. Top View of the MachXO1200 Device1
PIOs Arranged into
sysIO Banks
Programmable
Functional Units
with RAM (PFUs)
sysMEM Embedded
Block RAM (EBR)
Programmable
Functional Units
without RAM (PFFs)
sysCLOCK
PLL
JTAG Port
1. Top view of the MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks.
Figure 2-2. Top View of the MachXO640 Device

PIOs Arranged into
sysIO Banks
Programmable
Function Units
without RAM (PFFs)
Programmable
Function Units
with RAM (PFUs)
JTAG Port
2-2
Architecture
Figure 2-3. Top View of the MachXO256 Device
Programmable Function
Units without RAM (PFFs)
JTAG Port
PIOs Arranged
into sysIO Banks
Programmable
Function
Units with
RAM (PFUs)
PFU Blocks
The core of the MachXO devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM, and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic, and Distributed ROM functions. Except where necessary, the remainder of this data sheet will
use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected Slices, numbered 0-3 as shown in Figure 2-4. There are 53 inputs
and 25 outputs associated with each PFU block.
Figure 2-4. PFU Diagram
From
Routing
FCIN
LUT4 &
CARRY
LUT4 &
CARRY
LUT4 &
CARRY
Slice 0
D
FF/
Latch
D
FF/
Latch
LUT4 &
CARRY
LUT4 &
CARRY
Slice 1
D
FF/
Latch
LUT4 &
CARRY
LUT4 &
CARRY
D
FF/
Latch
FCO
Slice 3
Slice 2
D
FF/
Latch
LUT4 &
CARRY
D
FF/
Latch
D
FF/
Latch
D
FF/
Latch
To
Routing
Slice
Each Slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to perform functions such as LUT5, LUT6, LUT7, and
LUT8. There is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock
select, chip-select, and wider RAM/ROM functions. Figure 2-5 shows an overview of the internal logic of the Slice.
The registers in the Slice can be configured for positive/negative and edge/level clocks.
2-3
Architecture
There are 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent Slice/PFU).
There are 7 outputs: 6 to the routing and one to the carry-chain (to the adjacent Slice/PFU). Table 2-1 lists the signals associated with each Slice.
Figure 2-5. Slice Diagram
To Adjacent Slice/PFU
Slice
OFX1
A1
B1
C1
D1
CO
LUT4 &
CARRY
F1
F
D
SUM
FF/
Latch
Fast Connection
to I/O Cell*
Q1
CI
From
Routing
To
Routing
M1
M0
CO
A0
OFX0
Fast Connection
to I/O Cell*
LUT
Expansion
Mux
B0
C0
D0
LUT4 &
CARRY
F0
F
SUM
OFX0
CI
Control Signals
selected and
inverted per
Slice in routing
FF/
Latch
Q0
CE
CLK
LSR
From Adjacent Slice/PFU

Notes:
Some inter-Slice signals are not shown.
* Only PFUs at the edges have fast connections to the I/O cell.
Table 2-1. Slice Signal Descriptions

Function
Type
Signal Names
Description
Input
Data signal
A0, B0, C0, D0 Inputs to LUT4
Input
Data signal
A1, B1, C1, D1 Inputs to LUT4
Input
Multi-purpose
M0/M1
Input
Control signal
CE
Multipurpose Input
Clock Enable
Input
Control signal
LSR
Local Set/Reset
Input
Control signal
CLK
System Clock
Input
Inter-PFU signal
FCIN
Fast Carry In1
Output
Data signals
F0, F1
LUT4 output register bypass signals
Output
Data signals
Q0, Q1
Output
Data signals
OFX0
Output of a LUT5 MUX
Output
Data signals
OFX1
Output of a LUT6, LUT7, LUT82 MUX depending on the Slice
Output
Inter-PFU signal
FCO
Fast Carry Out1
Register Outputs
1. See Figure 2-4 for connection details.

2. Requires two PFUs.
2-4
Architecture
Modes of Operation
Each Slice is capable of four modes of operation: Logic, Ripple, RAM, and ROM. The Slice in the PFF is capable of
all modes except RAM. Table 2-2 lists the modes and the capability of the Slice blocks.
Table 2-2. Slice Modes
Logic
Ripple
RAM
ROM
PFU Slice
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
SP 16x2
ROM 16x1 x 2
PFF Slice
LUT 4x2 or LUT 5x1
2-bit Arithmetic Unit
N/A
ROM 16x1 x 2
Logic Mode: In this mode, the LUTs in each Slice are configured as 4-input combinatorial lookup tables (LUT4). A
LUT4 can have 16 possible input combinations. Any logic function with four inputs can be generated by programming this lookup table. Since there are two LUT4s per Slice, a LUT5 can be constructed within one Slice. Larger
lookup tables such as LUT6, LUT7, and LUT8 can be constructed by concatenating other Slices.
Ripple Mode: Ripple mode allows the efficient implementation of small arithmetic functions. In ripple mode, the following functions can be implemented by each Slice:
Addition 2-bit
Subtraction 2-bit
Add/Subtract 2-bit using dynamic control
Up counter 2-bit
Down counter 2-bit
Ripple mode multiplier building block
Comparator functions of A and B inputs
- A greater-than-or-equal-to B
- A not-equal-to B
- A less-than-or-equal-to B
Two additional signals, Carry Generate and Carry Propagate, are generated per Slice in this mode, allowing fast
arithmetic functions to be constructed by concatenating Slices.
RAM Mode: In this mode, distributed RAM can be constructed using each LUT block as a 16x2-bit memory.
Through the combination of LUTs and Slices, a variety of different memories can be constructed.
The ispLEVER design tool supports the creation of a variety of different size memories. Where appropriate, the
software will construct these using distributed memory primitives that represent the capabilities of the PFU.
Table 2-3 shows the number of Slices required to implement different distributed RAM primitives. Figure 2-6 shows
the distributed memory primitive block diagrams. Dual port memories involve the pairing of two Slices. One Slice
functions as the read-write port, while the other companion Slice supports the read-only port. For more information
on RAM mode in MachXO devices, please see details of additional technical documentation at the end of this data
sheet.
Table 2-3. Number of Slices Required For Implementing Distributed RAM
SPR16x2
DPR16x2
Number of Slices
Note: SPR = Single Port RAM, DPR = Dual Port RAM
2-5
Architecture
Figure 2-6. Distributed Memory Primitives
SPR16x2
AD0
AD1
AD2
AD3
DPR16x2
DO0
DI0
DI1
WRE
CK
DO1
WAD0
WAD1
WAD2
WAD3
RAD0
RAD1
RAD2
RAD3
DI0
DI1
WCK
WRE
RDO0
RDO1
WDO0
WDO1
ROM16x1
AD0
AD1
AD2
AD3
DO0
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
Ripple
RAM
ROM
LUT 4x8 or
MUX 2x1 x 8
Logic
2-bit Add x 4
SPR16x2 x 4
DPR16x2 x 2
ROM16x1 x 8
LUT 5x4 or
MUX 4x1 x 4
2-bit Sub x 4
SPR16x4 x 2
DPR16x4 x 1
ROM16x2 x 4
LUT 6x 2 or
MUX 8x1 x 2
2-bit Counter x 4
SPR16x8 x 1
ROM16x4 x 2
LUT 7x1 or
MUX 16x1 x 1
2-bit Comp x 4
ROM16x8 x 1
Routing
There are many resources provided in the MachXO devices to route signals individually or as buses with related
control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments.
The inter-PFU connections are made with three different types of routing resources: x1 (spans two PFUs), x2
(spans three PFUs) and x6 (spans seven PFUs). The x1, x2, and x6 connections provide fast and efficient connections in the horizontal and vertical directions.
2-6
Architecture
The ispLEVER design tool takes the output of the synthesis tool and places and routes the design. Generally, the
place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock/Control Distribution Network

The MachXO family of devices provides global signals that are available to all PFUs. These signals consist of four
primary clocks and four secondary clocks. Primary clock signals are generated from four 16:1 muxes as shown in
Figure 2-7 and Figure 2-8. The available clock sources for the MachXO256 and MachXO640 devices are four dual
function clock pins and 12 internal routing signals. The available clock sources for the MachXO1200 and
MachXO2280 devices are four dual function clock pins, up to nine internal routing signals and up to six PLL outputs.
Figure 2-7. Primary Clocks for MachXO256 and MachXO640 Devices
12
16:1
16:1
16:1
16:1
Routing
Clock
Pads
2-7
Primary Clock 0
Primary Clock 1
Primary Clock 2
Primary Clock 3
Architecture
Figure 2-8. Primary Clocks for MachXO1200 and MachXO2280 Devices
Up to 9
Up to 6
16:1
Primary Clock 0
Primary Clock 1
16:1
16:1
16:1
Routing
Clock
Pads
Primary Clock 2
Primary Clock 3
PLL
Outputs
Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock
sources come from dual function clock pins and 12 come from internal routing.
Figure 2-9. Secondary Clocks for MachXO Devices
12
16:1
16:1
Secondary (Control)
Clocks
16:1
16:1
Routing
Clock
Pads
2-8
Architecture
sysCLOCK Phase Locked Loops (PLLs)
The MachXO1200 and MachXO2280 provide PLL support. The source of the PLL input divider can come from an
external pin or from internal routing. There are four sources of feedback signals to the feedback divider: from
CLKINTFB (internal feedback port), from the global clock nets, from the output of the post scalar divider, and from
the routing (or from an external pin). There is a PLL_LOCK signal to indicate that the PLL has locked on to the input
clock signal. Figure 2-10 shows the sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either programmed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block
allows the user to adjust the phase and duty cycle of the CLKOS output.
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider, post scalar divider, and secondary clock divider. The input clock divider
is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post
scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the frequency range. The secondary divider is used to derive lower frequency outputs.
Figure 2-10. PLL Diagram
Dynamic Delay Adjustment
LOCK
RST
CLKI
(from routing or
external pin)
Input Clock
Divider
(CLKI)
Delay
Adjust
Voltage
Controlled
VCO
Oscillator
Post Scalar
Divider
(CLKOP)
Phase/Duty
Select
CLKOS
CLKOP
CLKFB
(from Post Scalar
Divider output,
clock net,
routing/external
pin or CLKINTFB
port
Secondary
Clock
Divider
(CLKOK)
Feedback
Divider
(CLKFB)
CLKOK
CLKINTFB
(internal feedback)
Figure 2-11 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.
Figure 2-11. PLL Primitive
RST
CLKI
CLKOP
CLKFB
CLKOS
DDA MODE
EHXPLLC
DDAIZR
CLKOK
LOCK
DDAILAG
CLKINTFB
DDAIDEL[2:0]
2-9
Architecture
Table 2-5. PLL Signal Descriptions
Signal
CLKI
I/O
Description
Clock input from external pin or routing
PLL feedback input from PLL output, clock net, routing/external pin or internal feedback from
CLKINTFB port
RST
1 to reset the input clock divider
CLKOS
PLL output clock to clock tree (phase shifted/duty cycle changed)
CLKFB
CLKOP
PLL output clock to clock tree (No phase shift)
CLKOK
PLL output to clock tree through secondary clock divider
LOCK
1 indicates PLL LOCK to CLKI
CLKINTFB
Internal feedback source, CLKOP divider output before CLOCKTREE
DDAMODE
Dynamic Delay Enable. 1: Pin control (dynamic), 0: Fuse Control (static)
DDAIZR
Dynamic Delay Zero. 1: delay = 0, 0: delay = on
DDAILAG
Dynamic Delay Lag/Lead. 1: Lag, 0: Lead
DDAIDEL[2:0]
Dynamic Delay Input
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
sysMEM Memory
The MachXO1200 and MachXO2280 devices contain sysMEM Embedded Block RAMs (EBRs). The EBR consists
of a 9-Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port, pseudo dual port, or FIFO memories. Each block can be
used in a variety of depths and widths as shown in Table 2-6.
Table 2-6. sysMEM Block Configurations
Memory Mode
Configurations
Single Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
True Dual Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
Pseudo Dual Port
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
FIFO
8,192 x 1
4,096 x 2
2,048 x 4
1,024 x 9
512 x 18
256 x 36
2-10
Architecture
Bus Size Matching
All of the multi-port memory modes support different widths on each of the ports. The RAM bits are mapped LSB
word 0 to MSB word 0, LSB word 1 to MSB word 1 and so on. Although the word size and number of words for
each port varies, this mapping scheme applies to each port.
RAM Initialization and ROM Operation
If desired, the contents of the RAM can be pre-loaded during device configuration. By preloading the RAM block
during the chip configuration cycle and disabling the write controls, the sysMEM block can also be utilized as a
ROM.
Memory Cascading
Larger and deeper blocks of RAMs can be created using EBR sysMEM Blocks. Typically, the Lattice design tools
cascade memory transparently, based on specific design inputs.
Single, Dual, Pseudo-Dual Port and FIFO Modes
Figure 2-12 shows the five basic memory configurations and their input/output names. In all the sysMEM RAM
modes, the input data and address for the ports are registered at the input of the memory array. The output data of
the memory is optionally registered at the memory array output.
Figure 2-12. sysMEM Memory Primitives
AD[12:0]
DI[35:0]
CLK
CE
RST
WE
CS[2:0]
EBR
ADA[12:0]
DIA[17:0]
CLKA
CEA
DO[35:0]
RSTA
WEA
CSA[2:0]
DOA[17:0]
True Dual Port RAM
Single Port RAM
AD[12:0]
CLK
CE
RST
CS[2:0]
EBR
ADW[12:0]
DI[35:0]
CLKW
CEW
DO[35:0]
WE
RST
CS[2:0]
ROM
DI[35:0]
CLKW
RSTA
WE
CEW
EBR
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
ADR[12:0]
EBR
DO[35:0]
CER
CLKR
Pseudo-Dual Port RAM
EBR
FIFO
2-11
DO[35:0]
CLKR
RSTB
RE
RCE
FF
AF
EF
AE
Architecture
The EBR memory supports three forms of write behavior for single or dual port operation:
1. Normal data on the output appears only during the read cycle. During a write cycle, the data (at the current
address) does not appear on the output. This mode is supported for all data widths.
2. Write Through a copy of the input data appears at the output of the same port. This mode is supported for
all data widths.
3. Read-Before-Write when new data is being written, the old contents of the address appears at the output.
This mode is supported for x9, x18 and x36 data widths.
FIFO Configuration
The FIFO has a write port with Data-in, CEW, WE and CLKW signals. There is a separate read port with Data-out,
RCE, RE and CLKR signals. The FIFO internally generates Almost Full, Full, Almost Empty and Empty Flags. The
Full and Almost Full flags are registered with CLKW. The Empty and Almost Empty flags are registered with CLKR.
The range of programming values for these flags are in Table 2-7.
Table 2-7. Programmable FIFO Flag Ranges
Flag Name
Programming Range
1 to (up to 2N-1)
Full (FF)
Almost Full (AF)
1 to Full-1
Almost Empty (AE)
1 to Full-1
Empty (EF)
N = Address bit width
The FIFO state machine supports two types of reset signals: RSTA and RSTB. The RSTA signal is a global reset
that clears the contents of the FIFO by resetting the read/write pointer and puts the FIFO flags in their initial reset
state. The RSTB signal is used to reset the read pointer. The purpose of this reset is to retransmit the data that is in
the FIFO. In these applications it is important to keep careful track of when a packet is written into or read from the
FIFO.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A and Port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated resets for both
ports are as shown in Figure 2-13.
2-12
Architecture
Figure 2-13. Memory Core Reset
Memory Core
SET
Port A[17:0]
LCLR
Output Data
Latches
D
SET
Port B[17:0]
LCLR
RSTA
RSTB
GSRN
Programmable Disable
For further information on the sysMEM EBR block, see the details of additional technical documentation at the end
of this data sheet.
EBR Asynchronous Reset
EBR asynchronous reset or GSR (if used) can only be applied if all clock enables are low for a clock cycle before the
reset is applied and released a clock cycle after the reset is released, as shown in Figure 2-14. The GSR input to the
EBR is always asynchronous.
Figure 2-14. EBR Asynchronous Reset (Including GSR) Timing Diagram
Reset
Clock
Clock
Enable
If all clock enables remain enabled, the EBR asynchronous reset or GSR may only be applied and released after
the EBR read and write clock inputs are in a steady state condition for a minimum of 1/fMAX (EBR clock). The reset
release must adhere to the EBR synchronous reset setup time before the next active read or write clock edge.
If an EBR is pre-loaded during configuration, the GSR input must be disabled or the release of the GSR during
device Wake Up must occur before the release of the device I/Os becoming active.
These instructions apply to all EBR RAM, ROM and FIFO implementations. For the EBR FIFO mode, the GSR signal is always enabled and the WE and RE signals act like the clock enable signals in Figure 2-14. The reset timing
rules apply to the RPReset input vs the RE input and the RST input vs. the WE and RE inputs. Both RST and
RPReset are always asynchronous EBR inputs.
Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled
2-13
Architecture
PIO Groups
On the MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO cells
and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while PIO
groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respective
sysIO buffers and PADs.
On all MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/O
pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins.
The MachXO1200 and MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger
devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these
devices can be configured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI
support.
Figure 2-15. Group of Four Programmable I/O Cells
This structure is used on the
left and right of MachXO devices
PIO A
PADA "T"
PIO B
PADB "C"
PIO C
PADC "T"
PIO D
PADD "C"
Four PIOs
Figure 2-16. Group ofSix Programmable I/O Cells

This structure is used on the top
and bottom of MachXO devices
PIO A
PADA "T"
PIO B
PADB "C"
PIO C
PADC "T"
PIO D
PADD "C"
PIO E
PADE "T"
PIO F
PADF "C"
Six PIOs
PIO
The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks
receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast
2-14
Architecture
output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17
shows the MachXO PIO logic.
The tristate control signal is multiplexed from the output data signals and their complements. In addition a global
signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer.
The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device.
In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times.
Figure 2-17. MachXO PIO Block Diagram
From Routing
TS
TSALL
From Routing
TO
sysIO
Buffer
Fast Output
Data signal
DO
PAD
1
Input
Data Signal
Programmable
Delay Elements
3
+
4-
Note: Buffer 1 tracks with VCCAUX

Buffer 2 tracks with VCCIO.
Buffer 3 tracks with internal 1.2V VREF.
Buffer 4 is available in MachXO1200 and MachXO2280 devices only.
From Complementary
Pad
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in todays systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL.
In the MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are powered using VCCIO. In addition to the Bank VCCIO supplies, the MachXO devices have a VCC core logic power supply,
and a VCCAUX supply that powers up a variety of internal circuits including all the differential and referenced input buffers.
MachXO256 and MachXO640 devices contain single-ended input buffers and single-ended output buffers with
complementary outputs on all the I/O Banks.
MachXO1200 and MachXO2280 devices contain two types of sysIO buffer pairs.
1. Top and Bottom sysIO Buffer Pairs
The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom
2-15
Architecture
of the devices also support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The
PCI clamp is enabled after VCC, VCCAUX, and VCCIO are at valid operating levels and the device has been configured.
The two pads in the pair are described as true and comp, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
2. Left and Right sysIO Buffer Pairs
The sysIO buffer pairs in the left and right Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (supporting ratioed and absolute input levels). The devices also have a
differential driver per output pair. The referenced input buffer can also be configured as a differential input buffer. In these Banks the two pads in the pair are described as true and comp, where the true pad is associated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the
negative side of the differential I/O.
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels.
After the POR signal is deactivated, the FPGA core logic becomes active. It is the users responsibility to ensure
that all VCCIO Banks are active with valid input logic levels to properly control the output logic states of all the I/O
Banks that are critical to the application. The default configuration of the I/O pins in a blank device is tri-state with a
weak pull-up to VCCIO. The I/O pins will maintain the blank configuration until VCC, VCCAUX and VCCIO have
reached satisfactory levels at which time the I/Os will take on the user-configured settings.
The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buffers. In order to simplify system design while providing consistent and predictable I/O behavior, the I/O buffers
should be powered up along with the FPGA core fabric. Therefore, VCCIO supplies should be powered up before or
together with the VCC and VCCAUX supplies
Supported Standards
The MachXO sysIO buffer supports both single-ended and differential standards. Single-ended standards can be
further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5, and 3.3V
standards. In the LVCMOS and LVTTL modes, the buffer has individually configurable options for drive strength,
bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS and LVPECL
output emulation is supported on all devices. The MachXO1200 and MachXO2280 support on-chip LVDS output
buffers on approximately 50% of the I/Os on the left and right Banks. Differential receivers for LVDS, BLVDS and
LVPECL are supported on all Banks of MachXO1200 and MachXO2280 devices. PCI support is provided in the top
Banks of the MachXO1200 and MachXO2280 devices. Table 2-8 summarizes the I/O characteristics of the devices
in the MachXO family.
Tables 2-9 and 2-10 show the I/O standards (together with their supply and reference voltages) supported by the
MachXO devices. For further information on utilizing the sysIO buffer to support a variety of standards please see
the details of additional technical documentation at the end of this data sheet.
2-16
Architecture
Table 2-8. I/O Support Device by Device
MachXO256
Number of I/O Banks
MachXO640
MachXO1200
MachXO2280
Single-ended
(all I/O Banks)
Single-ended
(all I/O Banks)
Single-ended
(all I/O Banks)
Single-ended
(all I/O Banks)
Differential Receivers
(all I/O Banks)
Differential Receivers
(all I/O Banks)
Single-ended buffers
with complementary
outputs (all I/O Banks)
with complementary
Type of Input Buffers
with complementary
with complementary
Types of Output Buffers

Differential buffers with Differential buffers with
true LVDS outputs (50% true LVDS outputs (50%
on left and right side)
on left and right side)
Differential Output
Emulation Capability
All I/O Banks
All I/O Banks
All I/O Banks
All I/O Banks
PCI Support
No
No
Top side only
Top side only
Table 2-9. Supported Input Standards

VCCIO (Typ.)
Input Standard
3.3V
2.5V
1.8V
1.5V
1.2V
Single Ended Interfaces

LVTTL
Yes
Yes
Yes
Yes
Yes
LVCMOS33
Yes
Yes
Yes
Yes
Yes
LVCMOS25
Yes
Yes
Yes
Yes
Yes
LVCMOS18
Yes
LVCMOS15
LVCMOS12
1
PCI
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Differential Interfaces
BLVDS2, LVDS2, LVPECL2, RSDS2
Yes
1. Top Banks of MachXO1200 and MachXO2280 devices only.

2. MachXO1200 and MachXO2280 devices only.
2-17
Architecture
Table 2-10. Supported Output Standards
Output Standard
Drive
VCCIO (Typ.)
Single-ended Interfaces
LVTTL
4mA, 8mA, 12mA, 16mA
3.3
LVCMOS33
3.3
LVCMOS25
2.5
LVCMOS18
1.8
LVCMOS15
4mA, 8mA
1.5
LVCMOS12
2mA, 6mA
1.2
LVCMOS33, Open Drain
4mA, 8mA
2mA, 6mA
N/A
3.3
N/A
2.5
BLVDS, RSDS
N/A
2.5
LVPECL2
N/A
3.3
PCI333
Differential Interfaces
LVDS1, 2
2
1. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers.

2. These interfaces can be emulated with external resistors in all devices.
3. Top Banks of MachXO1200 and MachXO2280 devices only.
sysIO Buffer Banks

The number of Banks vary between the devices of this family. Eight Banks surround the two larger devices, the
MachXO1200 and MachXO2280 (two Banks per side). The MachXO640 has four Banks (one Bank per side). The
smallest member of this family, the MachXO256, has only two Banks.
Each sysIO buffer Bank is capable of supporting multiple I/O standards. Each Bank has its own I/O supply voltage
(VCCIO) which allows it to be completely independent from the other Banks. Figure 2-18, Figure 2-18, Figure 2-20
and Figure 2-21 shows the sysIO Banks and their associated supplies for all devices.
2-18
Architecture
Figure 2-18. MachXO2280 Banks
Bank 7
Bank 1
36
1
34
Bank 6
34
Bank 4
GND
31
VCCIO4
Bank 5
VCCIO1
GND
VCCIO5
GND
33
Bank 3
GND
Bank 2
VCCIO6
35
GND
GND
Bank 0
VCCIO1
VCCIO7
GND
VCCIO0
1
1
VCCIO2
GND
VCCIO3
GND
33
35
Bank 7
Bank 1
30
1
26
Bank 6
Bank 5
20
2-19
Bank 4
GND
VCCIO4
28
GND
GND
Bank 3
VCCIO6
24
26
VCCIO5
GND
Bank 0
Bank 2
VCCIO7
GND
VCCIO0
1
1
28
29
VCCIO2
GND
VCCIO3
GND
Architecture
Bank 3
40
VCCO2
GND
40
37
Bank 2
V CCO1
GND
GND
42
1
Bank 0
Bank 1
V CCO3
GND
V CCO0
1
1
V CCO0
1
1
Bank 0
Bank 1
GND
41
37
GND
V CCO1
Hot Socketing
The MachXO devices have been carefully designed to ensure predictable behavior during power-up and powerdown. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of
2-20
Architecture
the system. These capabilities make the MachXO ideal for many multiple power supply and hot-swap applications.
Sleep Mode
The MachXO C devices (VCC = 1.8/2.5/3.3V) have a sleep mode that allows standby current to be reduced dramatically during periods of system inactivity. Entry and exit to Sleep mode is controlled by the SLEEPN pin.
During Sleep mode, the logic is non-operational, registers and EBR contents are not maintained, and I/Os are tristated. Do not enter Sleep mode during device programming or configuration operation. In Sleep mode, power supplies are in their normal operating range, eliminating the need for external switching of power supplies. Table 2-11
compares the characteristics of Normal, Off and Sleep modes.
Table 2-11. Characteristics of Normal, Off and Sleep Modes
Characteristic
SLEEPN Pin
Static Icc
I/O Leakage
Power Supplies VCC/VCCIO/VCCAUX
Normal
Off
Sleep
High
Low
Typical <10mA
Typical <100uA
<10A
<1mA
<10A
Normal Range
Normal Range
Logic Operation
User Defined
Non Operational
Non operational
I/O Operation
User Defined
Tri-state
Tri-state
JTAG and Programming circuitry
Operational
Non-operational
Non-operational
EBR Contents and Registers
Maintained
Non-maintained
Non-maintained
SLEEPN Pin Characteristics

The SLEEPN pin behaves as an LVCMOS input with the voltage standard appropriate to the VCC supply for the
device. This pin also has a weak pull-up, along with a Schmidt trigger and glitch filter to prevent false triggering. An
external pull-up to VCC is recommended when Sleep Mode is not used to ensure the device stays in normal operation mode. Typically, the device enters sleep mode several hundred nanoseconds after SLEEPN is held at a valid
low and restarts normal operation as specified in the Sleep Mode Timing table. The AC and DC specifications portion of this data sheet shows a detailed timing diagram.
Oscillator
Every MachXO device has an internal CMOS oscillator. The oscillator can be routed as an input clock to the clock
tree or to general routing resources. The oscillator frequency can be divided by internal logic. There is a dedicated
programming bit to enable/disable the oscillator. The oscillator frequency ranges from 18MHz to 26MHz.
Configuration and Testing

The following section describes the configuration and testing features of the MachXO family of devices.
IEEE 1149.1-Compliant Boundary Scan Testability

All MachXO devices have boundary scan cells that are accessed through an IEEE 1149.1 compliant test access
port (TAP). This allows functional testing of the circuit board, on which the device is mounted, through a serial scan
path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port shares its power supply with one of the
VCCIO Banks (MachXO256: VCCIO1; MachXO640: VCCIO2; MachXO1200 and MachXO2280: VCCIO5) and can
operate with LVCMOS3.3, 2.5, 1.8, 1.5, and 1.2 standards.
For more details on boundary scan test, please see information regarding additional technical documentation at
the end of this data sheet.
2-21
Architecture
Device Configuration
All MachXO devices contain a test access port that can be used for device configuration and programming.
The non-volatile memory in the MachXO can be configured in two different modes:
In IEEE 1532 mode via the IEEE 1149.1 port. In this mode, the device is off-line and I/Os are controlled by
BSCAN registers.
In background mode via the IEEE 1149.1 port. This allows the device to remain operational in user mode
while reprogramming takes place.
The SRAM configuration memory can be configured in three different ways:
At power-up via the on-chip non-volatile memory.
After a refresh command is issued via the IEEE 1149.1 port.
In IEEE 1532 mode via the IEEE 1149.1 port.
Figure 2-22 provides a pictorial representation of the different programming modes available in the MachXO
devices. On power-up, the SRAM is ready to be configured with IEEE 1149.1 serial TAP port using IEEE 1532 protocols.
Leave Alone I/O
When using IEEE 1532 mode for non-volatile memory programming, SRAM configuration, or issuing a refresh
command, users may specify I/Os as high, low, tristated or held at current value. This provides excellent flexibility
for implementing systems where reconfiguration or reprogramming occurs on-the-fly.
TransFR (Transparent Field Reconfiguration)
TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting
system operation using a single ispVM command. See TN1087, Minimizing System Interruption During Configuration Using TransFR Technology for details.
Security
The MachXO devices contain security bits that, when set, prevent the readback of the SRAM configuration and
non-volatile memory spaces. Once set, the only way to clear the security bits is to erase the memory space.
For more information on device configuration, please see details of additional technical documentation at the end
of this data sheet.
2-22
Architecture
Figure 2-22. MachXO Configuration and Programming
ISP 1149.1 TAP Port

Port
Background
1532
Mode
Program in seconds
Power-up
Non-Volatile
Memory Space
Configure in milliseconds
SRAM Memory
Space
Refresh
Download in
microseconds
Density Shifting
The MachXO family has been designed to enable density migration in the same package. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density
parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a
lower density device. However, the exact details of the final resource utilization will impact the likely success in
each case.
2-23

DC and Switching Characteristics
June 2013
Data Sheet DS1002
Absolute Maximum Ratings1, 2, 3

LCMXO E (1.2V)
LCMXO C (1.8V/2.5V/3.3V)
Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32V . . . . . . . . . . . . . . . -0.5 to 3.75V
Supply Voltage VCCAUX . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
Output Supply Voltage VCCIO . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
I/O Tristate Voltage Applied 4 . . . . . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 3.75V
Dedicated Input Voltage Applied4 . . . . . . . . . . . . . -0.5 to 3.75V . . . . . . . . . . . . . . . -0.5 to 4.25V
Storage Temperature (ambient). . . . . . . . . . . . . . . -65 to 150C . . . . . . . . . . . . . . . -65 to 150C
Junction Temp. (Tj) . . . . . . . . . . . . . . . . . . . . . . . . . . +125C . . . . . . . . . . . . . . . . . . . +125C
1. Stress above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
2. Compliance with the Lattice Thermal Management document is required.
3. All voltages referenced to GND.
4. Overshoot and undershoot of -2V to (VIHMAX + 2) volts is permitted for a duration of <20ns.
Recommended Operating Conditions1

Symbol
Parameter
Min.
Max.
Units
Core Supply Voltage for 1.2V Devices
1.14
1.26
Core Supply Voltage for 1.8V/2.5V/3.3V Devices
1.71
3.465
VCCAUX
Auxiliary Supply Voltage
3.135
3.465
VCCIO2
I/O Driver Supply Voltage
1.14
3.465
VCC
3
tJCOM
Junction Temperature Commercial Operation
tJIND
Junction Temperature Industrial Operation
tJFLASHCOM
Junction Temperature, Flash Programming, Commercial
tJFLASHIND
Junction Temperature, Flash Programming, Industrial
+85
-40
100
+85
-40
100
C
C
C
C
1. Like power supplies must be tied together. For example, if VCCIO and VCC are both 2.5V, they must also be the same supply. 3.3V VCCIO
and 1.2V VCCIO should be tied to VCCAUX or 1.2V VCC respectively.
2. See recommended voltages by I/O standard in subsequent table.
3. VCC must reach minimum VCC value before VCCAUX reaches 2.5V.
MachXO Programming/Erase Specifications

Symbol
NPROGCYC
tRETENTION
Parameter
Min.
Flash Programming Cycles per tRETENTION

Flash Functional Programming Cycles
Data Retention at 125o Junction Temperature
10
Max.
Units
1,000
Cycles
10,000
Cycles
Years
www.latticesemi.com
3-1
DS1002 DC and Switching_01.8

MachXO256 and MachXO640 Hot Socketing Specifications1, 2, 3

Symbol
IDK
Parameter
Condition
0 VIN VIH (MAX)
Input or I/O leakage Current
Min.
Typ.
Max
Units
+/-1000
1. Insensitive to sequence of VCC, VCCAUX, and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX, and VCCIO.
2. 0 VCC VCC (MAX), 0 VCCIO VCCIO (MAX) and 0 VCCAUX VCCAUX (MAX).
3. IDK is additive to IPU, IPD or IBH.
MachXO1200 and MachXO2280 Hot Socketing Specifications1, 2, 3

Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
0 VIN VIH (MAX.)
+/-1000
VIN VCCIO
+/-1000
VIN > VCCIO
35
mA
Non-LVDS General Purpose sysIOs

IDK
Input or I/O Leakage Current
LVDS General Purpose sysIOs

IDK_LVDS
Input or I/O Leakage Current
1. Insensitive to sequence of VCC, VCCAUX, and VCCIO. However, assumes monotonic rise/fall rates for VCC, VCCAUX, and VCCIO.
2. 0 VCC VCC (MAX), 0 VCCIO VCCIO (MAX), and 0 VCCAUX VCCAUX (MAX).
3. IDK is additive to IPU, IPW or IBH.
DC Electrical Characteristics
Over Recommended Operating Conditions
Symbol
Parameter
IIL, IIH1, 4, 5 Input or I/O Leakage
Condition
0 VIN (VCCIO - 0.2V)
Min.
Typ.
Max.
Units
10
(VCCIO - 0.2V) < VIN 3.6V
40
IPU
I/O Active Pull-up Current
0 VIN 0.7 VCCIO
-30
-150
IPD
I/O Active Pull-down Current
VIL (MAX) VIN VIH (MAX)
30
150
IBHLS
Bus Hold Low sustaining current
VIN = VIL (MAX)
30
IBHHS
Bus Hold High sustaining current VIN = 0.7VCCIO
-30
IBHLO
Bus Hold Low Overdrive current
0 VIN VIH (MAX)
150
IBHHO
Bus Hold High Overdrive current
0 VIN VIH (MAX)
-150
VBHT3
Bus Hold trip Points
0 VIN VIH (MAX)
VIL (MAX)
VIH (MIN)
C1
I/O Capacitance2
VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

VCC = Typ., VIO = 0 to VIH (MAX)
pf
C2
Dedicated Input Capacitance2
VCCIO = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V,

VCC = Typ., VIO = 0 to VIH (MAX)
pf
1. Input or I/O leakage current is measured with the pin configured as an input or as an I/O with the output driver tri-stated. It is not measured
with the output driver active. Bus maintenance circuits are disabled.
2. TA 25C, f = 1.0MHz
3. Please refer to VIL and VIH in the sysIO Single-Ended DC Electrical Characteristics table of this document.
4. Not applicable to SLEEPN pin.
5. When VIH is higher than VCCIO, a transient current typically of 30ns in duration or less with a peak current of 6mA can occur on the high-tolow transition. For MachXO1200 and MachXO2280 true LVDS output pins, VIH must be less than or equal to VCCIO.
3-2

Supply Current (Sleep Mode)1, 2

Symbol
ICC
Max.
Units
LCMXO256C
12
25
LCMXO640C
12
25
LCMXO1200C
12
25
LCMXO2280C
12
25
LCMXO256C
15
Device
Core Power Supply
ICCAUX
Auxiliary Power Supply
ICCIO
Bank Power Supply4
1.
2.
3.
4.
Typ.3
Parameter
LCMXO640C
25
LCMXO1200C
45
LCMXO2280C
85
All LCMXO C Devices
30
Assumes all inputs are configured as LVCMOS and held at the VCCIO or GND.
Frequency = 0MHz.
TA = 25C, power supplies at nominal voltage.
Per Bank.
Supply Current (Standby)1, 2, 3, 4

Symbol
ICC
ICCAUX
ICCIO
1.
2.
3.
4.
5.
6.
Typ.5
Units
LCMXO256C
mA
LCMXO640C
mA
LCMXO1200C
14
mA
LCMXO2280C
20
mA
LCMXO256E
mA
Parameter
Core Power Supply

VCCAUX = 3.3V
6
Bank Power Supply
Device
LCMXO640E
mA
LCMXO1200E
10
mA
LCMXO2280E
12
mA
LCMXO256E/C
mA
LCMXO640E/C
mA
LCMXO1200E/C
12
mA
LCMXO2280E/C
13
mA
All devices
mA
For further information on supply current, please see details of additional technical documentation at the end of this data sheet.
Assumes all outputs are tristated, all inputs are configured as LVCMOS and held at VCCIO or GND.
Frequency = 0MHz.
User pattern = blank.
TJ = 25oC, power supplies at nominal voltage.
Per Bank. VCCIO = 2.5V. Does not include pull-up/pull-down.
3-3

Initialization Supply Current1, 2, 3, 4

Symbol
Parameter
Device
LCMXO256C
ICC
Core Power Supply

VCCAUX = 3.3V
ICCAUX
Bank Power Supply6
ICCIO
1.
2.
3.
4.
5.
6.
Typ.5
Units
13
mA
LCMXO640C
17
mA
LCMXO1200C
21
mA
LCMXO2280C
23
mA
LCMXO256E
10
mA
LCMXO640E
14
mA
LCMXO1200E
18
mA
LCMXO2280E
20
mA
LCMXO256E/C
10
mA
LCMXO640E/C
13
mA
LCMXO1200E/C
24
mA
LCMXO2280E/C
25
mA
All devices
mA
Assumes all I/O pins are held at VCCIO or GND.
Frequency = 0MHz.
Typical user pattern.
TJ = 25oC, power supplies at nominal voltage.
Per Bank, VCCIO = 2.5V. Does not include pull-up/pull-down.
Programming and Erase Flash Supply Current1, 2, 3, 4

Symbol
ICC
ICCAUX
ICCIO
1.
2.
3.
4.
5.
6.
Parameter
Core Power Supply

VCCAUX = 3.3V
Bank Power Supply
Typ.5
Units
LCMXO256C
mA
LCMXO640C
11
mA
LCMXO1200C
16
mA
LCMXO2280C
22
mA
LCMXO256E
mA
LCMXO640E
mA
LCMXO1200E
12
mA
LCMXO2280E
14
mA
LCMXO256C/E
mA
LCMXO640C/E
10
mA
LCMXO1200/E
15
mA
LCMXO2280C/E
16
mA
All devices
mA
Device
Assumes all I/O pins are held at VCCIO or GND.
Typical user pattern.
JTAG programming is at 25MHz.
TJ = 25C, power supplies at nominal voltage.
Per Bank. VCCIO = 2.5V. Does not include pull-up/pull-down.
3-4

sysIO Recommended Operating Conditions

VCCIO (V)
Min.
Typ.
Max.
LVCMOS 3.3
3.135
3.3
3.465
LVCMOS 2.5
2.375
2.5
2.625
Standard
LVCMOS 1.8
1.71
1.8
1.89
LVCMOS 1.5
1.425
1.5
1.575
LVCMOS 1.2
1.14
1.2
1.26
LVTTL
3.135
3.3
3.465
PCI3
3.135
3.3
3.465
2.375
2.5
2.625
LVPECL
3.135
3.3
3.465
BLVDS1
2.375
2.5
2.625
RSDS1
2.375
2.5
2.625
LVDS1, 2
1
1. Inputs on chip. Outputs are implemented with the addition of external resistors.
2. MachXO1200 and MachXO2280 devices have dedicated LVDS buffers
3. Input on the top bank of the MachXO1200 and MachXO2280 only.
sysIO Single-Ended DC Electrical Characteristics

Input/Output
Standard
LVCMOS 3.3
LVTTL
LVCMOS 2.5
VIH
VIL
Min. (V)
Max. (V)
Min. (V)
Max. (V)
-0.3
0.8
2.0
3.6
-0.3
-0.3
0.8
0.7
2.0
1.7
3.6
3.6
LVCMOS 1.8
-0.3
0.35VCCIO
0.65VCCIO
3.6
LVCMOS 1.5
-0.3
0.35VCCIO
0.65VCCIO
3.6
LVCMOS 1.2
(C Version)
-0.3
0.42
0.78
3.6
LVCMOS 1.2
(E Version)
-0.3
0.35VCC
0.65VCC
3.6
PCI
-0.3
0.3VCCIO
0.5VCCIO
3.6
VOL Max.
(V)
VOH Min.
(V)
IOL1
(mA)
IOH1
(mA)
0.4
VCCIO - 0.4
16, 12, 8, 4
-14, -12, -8, -4
0.2
VCCIO - 0.2
0.1
-0.1
0.4
2.4
16
-16
0.4
VCCIO - 0.4
12, 8, 4
-12, -8, -4
0.2
VCCIO - 0.2
0.1
-0.1
0.4
VCCIO - 0.4
16, 12, 8, 4
-14, -12, -8, -4
0.2
VCCIO - 0.2
0.1
-0.1
0.4
VCCIO - 0.4
16, 12, 8, 4
-14, -12, -8, -4
0.2
VCCIO - 0.2
0.1
-0.1
0.4
VCCIO - 0.4
8, 4
-8, -4
0.2
VCCIO - 0.2
0.1
-0.1
0.4
VCCIO - 0.4
6, 2
-6, -2
0.2
VCCIO - 0.2
0.1
-0.1
0.4
VCCIO - 0.4
6, 2
-6, -2
0.2
VCCIO - 0.2
0.1
-0.1
0.1VCCIO
0.9VCCIO
1.5
-0.5
1. The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O Bank and the end of an I/O Bank, as
shown in the logic signal connections table shall not exceed n * 8mA. Where n is the number of I/Os between Bank GND connections or
between the last GND in a Bank and the end of a Bank.
3-5

sysIO Differential Electrical Characteristics

LVDS
Parameter
Symbol
Parameter Description
Test Conditions
VINP, VINM
Input Voltage
VTHD
Differential Input Threshold
VCM
Input Common Mode Voltage
IIN
Input current
Power on
Min.
Typ.
Max.
Units
2.4
+/-100
mV
100mV VTHD
VTHD/2
1.2
1.8
200mV VTHD
VTHD/2
1.2
1.9
350mV VTHD
VTHD/2
1.2
2.0
+/-10
VOH
Output high voltage for VOP or VOM
RT = 100 Ohm
1.38
1.60
VOL
Output low voltage for VOP or VOM
RT = 100 Ohm
0.9V
1.03
VOD
Output voltage differential
(VOP - VOM), RT = 100 Ohm
250
350
450
mV
VOD
Change in VOD between high and

low
50
mV
VOS
Output voltage offset
1.125
1.25
1.375
VOS
Change in VOS between H and L
50
mV
mA
IOSD
(VOP - VOM)/2, RT = 100 Ohm

VOD = 0V Driver outputs
shorted
Output short circuit current
LVDS Emulation
MachXO devices can support LVDS outputs via emulation (LVDS25E), in addition to the LVDS support that is available on-chip on certain devices. The output is emulated using complementary LVCMOS outputs in conjunction with
resistors across the driver outputs on all devices. The scheme shown in Figure 3-1 is one possible solution for
LVDS standard implementation. Resistor values in Figure 3-1 are industry standard values for 1% resistors.
Figure 3-1. LVDS Using External Resistors (LVDS25E)
VCCIO = 2.5
158
8mA
Zo = 100
VCCIO = 2.5
158
140
+
100
8mA
On-chip
Off-chip
Off-chip
Emulated
LVDS
Buffer
Note: All resistors are 1%.
The LVDS differential input buffers are available on certain devices in the MachXO family.
3-6
On-chip

Table 3-1. LVDS DC Conditions
Parameter
Description
Typical
Units
ZOUT
Output impedance
20
RS
Driver series resistor
294
RP
Driver parallel resistor
121
RT
Receiver termination
100
VOH
Output high voltage
1.43
VOL
Output low voltage
1.07
VOD
Output differential voltage
0.35
VCM
Output common mode voltage
1.25
ZBACK
Back impedance
100
IDC
DC output current
3.66
mA
BLVDS
The MachXO family supports the BLVDS standard through emulation. The output is emulated using complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. The input standard
is supported by the LVDS differential input buffer on certain devices. BLVDS is intended for use when multi-drop
and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible
solution for bi-directional multi-point differential signals.
Figure 3-2. BLVDS Multi-point Output Example
Heavily loaded backplane, effective Zo ~ 45 to 90 ohms differential
2.5V
2.5V
80
45-90 ohms
45-90 ohms
16mA
16mA
80
2.5V
2.5V
80
16mA
16mA
80
...
2.5V
+
-
2.5V
16mA
16mA
3-7
80
2.5V
16mA
80
+
-
2.5V
16mA
80

Table 3-2. BLVDS DC Conditions1
Nominal
Symbol
Description
Zo = 45
Zo = 90
Units
ZOUT
Output impedance
100
100
Ohms
RTLEFT
Left end termination
45
90
Ohms
RTRIGHT
Right end termination
45
90
Ohms
VOH
Output high voltage
1.375
1.48
VOL
Output low voltage
1.125
1.02
VOD
0.25
0.46
VCM
1.25
1.25
IDC
DC output current
11.2
10.2
mA
1. For input buffer, see LVDS table.
LVPECL
The MachXO family supports the differential LVPECL standard through emulation. This output standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all
the devices. The LVPECL input standard is supported by the LVDS differential input buffer on certain devices. The
scheme shown in Figure 3-3 is one possible solution for point-to-point signals.
Figure 3-3. Differential LVPECL
VCCIO = 3.3V
100 ohms
16mA
+
VCCIO = 3.3V
150 ohms
100 ohms
100 ohms
16mA
Transmission line, Zo = 100 ohm differential
On-chip
Off-chip
Off-chip
On-chip
Table 3-3. LVPECL DC Conditions1

Symbol
Description
Nominal
Units
ZOUT
Output impedance
100
Ohms
RP
150
Ohms
RT
100
Ohms
VOH
Output high voltage
2.03
VOL
Output low voltage
1.27
VOD
0.76
VCM
1.65
ZBACK
Back impedance
85.7
Ohms
IDC
DC output current
12.7
mA
1. For input buffer, see LVDS table.
3-8

For further information on LVPECL, BLVDS and other differential interfaces please see details of additional technical documentation at the end of the data sheet.
RSDS
The MachXO family supports the differential RSDS standard. The output standard is emulated using complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs on all the devices. The RSDS
input standard is supported by the LVDS differential input buffer on certain devices. The scheme shown in Figure 34 is one possible solution for RSDS standard implementation. Use LVDS25E mode with suggested resistors for
RSDS operation. Resistor values in Figure 3-4 are industry standard values for 1% resistors.
Figure 3-4. RSDS (Reduced Swing Differential Standard)
VCCIO = 2.5V
294
8mA
Zo = 100
+
VCCIO = 2.5V
121
100
294
8mA
On-chip
Off-chip
Off-chip
On-chip
Emulated
RSDS Buffer
Table 3-4. RSDS DC Conditions

Parameter
Description
Typical
Units
ZOUT
Output impedance
20
Ohms
RS
Driver series resistor
294
Ohms
RP
121
Ohms
RT
100
Ohms
VOH
Output high voltage
1.35
VOL
Output low voltage
1.15
VOD
0.20
VCM
1.25
ZBACK
Back impedance
101.5
Ohms
IDC
DC output current
3.66
mA
3-9

Typical Building Block Function Performance1

Pin-to-Pin Performance (LVCMOS25 12mA Drive)
Function
-5 Timing
Units
Basic Functions
16-bit decoder
6.7
ns
4:1 MUX
4.5
ns
16:1 MUX
5.1
ns
-5 Timing
Units
16:1 MUX
487
MHz
16-bit adder
292
MHz
16-bit counter
388
MHz
64-bit counter
200
MHz
Register-to-Register Performance
Function
Basic Functions
Embedded Memory Functions (1200 and 2280 Devices Only)

256x36 Single Port RAM
284
MHz
512x18 True-Dual Port RAM
284
MHz
434
MHz
Distributed Memory Functions

320
MHz
261
MHz
32x2 Pseudo-Dual Port RAM
314
MHz
64x4 Pseudo-Dual Port RAM
271
MHz
1. The above timing numbers are generated using the ispLEVER design tool. Exact performance may vary with device and
tool version. The tool uses internal parameters that have been characterized but are not tested on every device.
Rev. A 0.19
Derating Logic Timing

Logic Timing provided in the following sections of the data sheet and the ispLEVER design tools are worst case
numbers in the operating range. Actual delays may be much faster. The ispLEVER design tool from Lattice can
provide logic timing numbers at a particular temperature and voltage.
3-10

MachXO External Switching Characteristics1

-5
Parameter
Description
Device
-4
-3
Min.
Max.
Min.
Max.
Min.
Max.
Units
LCMXO256
3.5
4.2
4.9
ns
LCMXO640
3.5
4.2
4.9
ns
LCMXO1200
3.6
4.4
5.1
ns
LCMXO2280
3.6
4.4
5.1
ns
LCMXO256
4.0
4.8
5.6
ns
LCMXO640
4.0
4.8
5.7
ns
LCMXO1200
4.3
5.2
6.1
ns
LCMXO2280
4.3
5.2
6.1
ns
LCMXO256
1.3
1.6
1.8
ns
LCMXO640
1.1
1.3
1.5
ns
LCMXO1200
1.1
1.3
1.6
ns
LCMXO2280
1.1
1.3
1.5
ns
LCMXO256
-0.3
-0.3
-0.3
ns
LCMXO640
-0.1
-0.1
-0.1
ns
General I/O Pin Parameters (Using Global Clock without PLL)
tPD
tCO
tSU
tH
fMAX_IO
tSKEW_PRI
Best Case tPD Through 1 LUT
Best Case Clock to Output - From PFU
Clock to Data Setup - To PFU
Clock to Data Hold - To PFU
Clock Frequency of I/O and PFU Register
Global Clock Skew Across Device
LCMXO1200
0.0
0.0
0.0
ns
LCMXO2280
-0.4
-0.4
-0.4
ns
LCMXO256
600
550
500
MHz
LCMXO640
600
550
500
MHz
LCMXO1200
600
550
500
MHz
LCMXO2280
600
550
500
MHz
LCMXO256
200
220
240
ps
LCMXO640
200
220
240
ps
LCMXO1200
220
240
260
ps
LCMXO2280
220
240
260
ps
1. General timing numbers based on LVCMOS2.5V, 12 mA.

Rev. A 0.19
3-11

MachXO Internal Timing Parameters1

-5
Parameter
Description
-4
Min.
Max.
Min.
-3
Max.
Min.
Max.
Units
PFU/PFF Logic Mode Timing

tLUT4_PFU
LUT4 delay (A to D inputs to F output)
0.28
0.34
0.39
ns
tLUT6_PFU
LUT6 delay (A to D inputs to OFX output)
0.44
0.53
0.62
ns
tLSR_PFU
Set/Reset to output of PFU
0.90
1.08
1.26
ns
tSUM_PFU
Clock to Mux (M0,M1) input setup time
0.10
0.13
0.15
ns
tHM_PFU
Clock to Mux (M0,M1) input hold time
-0.05
-0.06
-0.07
ns
0.16
0.18
ns
tSUD_PFU
Clock to D input setup time
0.13
tHD_PFU
Clock to D input hold time
-0.03
-0.03
-0.04
ns
tCK2Q_PFU
Clock to Q delay, D-type register configuration
0.40
0.48
0.56
ns
tLE2Q_PFU
Clock to Q delay latch configuration
0.53
0.64
0.74
ns
tLD2Q_PFU
D to Q throughput delay when latch is enabled
0.55
0.66
0.77
ns
0.40
0.48
0.56
ns
PFU Dual Port Memory Mode Timing

tCORAM_PFU
Clock to Output
tSUDATA_PFU
Data Setup Time
-0.18
-0.22
-0.25
ns
tHDATA_PFU
Data Hold Time
0.28
0.34
0.39
ns
tSUADDR_PFU Address Setup Time
-0.46
-0.56
-0.65
ns
tHADDR_PFU
0.71
0.85
0.99
ns
tSUWREN_PFU Write/Read Enable Setup Time
-0.22
-0.26
-0.30
ns
tHWREN_PFU
0.33
0.40
0.47
ns
Address Hold Time

Write/Read Enable Hold Time
PIO Input/Output Buffer Timing

tIN_PIO
Input Buffer Delay
0.75
0.90
1.06
ns
tOUT_PIO
Output Buffer Delay
1.29
1.54
1.80
ns
EBR Timing (1200 and 2280 Devices Only)

tCO_EBR
Clock to output from Address or Data with no output

register
2.24
2.69
3.14
ns
tCOO_EBR
Clock to output from EBR output Register
0.54
0.64
0.75
ns
tSUDATA_EBR
Setup Data to EBR Memory
-0.26
-0.31
-0.37
ns
tHDATA_EBR
Hold Data to EBR Memory
0.41
0.49
0.57
ns
-0.26
-0.31
-0.37
ns
ns
tSUADDR_EBR Setup Address to EBR Memory

tHADDR_EBR
0.41
0.49
0.57
tSUWREN_EBR Setup Write/Read Enable to EBR Memory
Hold Address to EBR Memory
-0.17
-0.20
-0.23
ns
tHWREN_EBR
Hold Write/Read Enable to EBR Memory
0.26
0.31
0.36
ns
tSUCE_EBR
Clock Enable Setup Time to EBR Output Register
0.19
0.23
0.27
ns
tHCE_EBR
Clock Enable Hold Time to EBR Output Register
-0.13
-0.16
-0.18
ns
tRSTO_EBR
Reset To Output Delay Time from EBR Output Register
1.03
1.23
1.44
ns
PLL Parameters (1200 and 2280 Devices Only)

tRSTREC
Reset Recovery to Rising Clock
1.00
1.00
1.00
ns
tRSTSU
Reset Signal Setup Time
1.00
1.00
1.00
ns
1. Internal parameters are characterized but not tested on every device.

Rev. A 0.19
3-12

MachXO Family Timing Adders1, 2, 3

Buffer Type
Description
-5
-4
-3
Units
0.44
0.53
0.61
ns
Input Adjusters
LVDS254
LVDS
BLVDS254
BLVDS
0.44
0.53
0.61
ns
LVPECL334
LVPECL
0.42
0.50
0.59
ns
LVTTL33
LVTTL
0.01
0.01
0.01
ns
LVCMOS33
LVCMOS 3.3
0.01
0.01
0.01
ns
LVCMOS25
LVCMOS 2.5
0.00
0.00
0.00
ns
LVCMOS18
LVCMOS 1.8
0.07
0.08
0.10
ns
LVCMOS15
LVCMOS 1.5
0.14
0.17
0.19
ns
LVCMOS12
LVCMOS 1.2
0.40
0.48
0.56
ns
PCI
0.01
0.01
0.01
ns
LVDS 2.5 E
-0.13
-0.15
-0.18
ns
LVDS25
LVDS 2.5
-0.21
-0.26
-0.30
ns
BLVDS25
BLVDS 2.5
-0.03
-0.03
-0.04
ns
LVPECL33
LVPECL 3.3
0.04
0.04
0.05
ns
LVTTL33_4mA
LVTTL 4mA drive
0.04
0.04
0.05
ns
LVTTL33_8mA
LVTTL 8mA drive
0.06
0.07
0.08
ns
LVTTL33_12mA
LVTTL 12mA drive
-0.01
-0.01
-0.01
ns
LVTTL33_16mA
LVTTL 16mA drive
0.50
0.60
0.70
ns
LVCMOS33_4mA
LVCMOS 3.3 4mA drive
0.04
0.04
0.05
ns
LVCMOS33_8mA
0.06
0.07
0.08
ns
LVCMOS33_12mA
-0.01
-0.01
-0.01
ns
LVCMOS33_14mA
0.50
0.60
0.70
ns
LVCMOS25_4mA
0.05
0.06
0.07
ns
LVCMOS25_8mA
0.10
0.12
0.13
ns
LVCMOS25_12mA
0.00
0.00
0.00
ns
LVCMOS25_14mA
0.34
0.40
0.47
ns
LVCMOS18_4mA
0.11
0.13
0.15
ns
LVCMOS18_8mA
0.05
0.06
0.06
ns
LVCMOS18_12mA
-0.06
-0.07
-0.08
ns
PCI33
Output Adjusters
LVDS25E
4
LVCMOS18_14mA
0.06
0.07
0.09
ns
LVCMOS15_4mA
0.15
0.19
0.22
ns
LVCMOS15_8mA
0.05
0.06
0.07
ns
LVCMOS12_2mA
0.26
0.31
0.36
ns
LVCMOS12_6mA
0.05
0.06
0.07
ns
PCI334
PCI33
1.85
2.22
2.59
ns
1. Timing adders are characterized but not tested on every device.

2. LVCMOS timing is measured with the load specified in Switching Test Conditions table.
3. All other standards tested according to the appropriate specifications.
4. I/O standard only available in LCMXO1200 and LCMXO2280 devices.
Rev. A 0.19
3-13

sysCLOCK PLL Timing

Parameter
Descriptions
Conditions
fIN
Input Clock Frequency (CLKI, CLKFB)
fOUT
Output Clock Frequency (CLKOP, CLKOS)
fOUT2
K-Divider Output Frequency (CLKOK)
fVCO
PLL VCO Frequency
fPFD
Phase Detector Input Frequency
Input Divider (M) = 1;

Feedback Divider (N) <= 45, 6
Min.
Max.
Units
25
420
MHz
18
25
MHz
25
420
MHz
0.195
210
MHz
420
840
MHz
25
MHz
Input Divider (M) = 1;

Feedback Divider (N) <= 45, 6
18
25
MHz
Default duty cycle selected3
45
55
0.05
UI
AC Characteristics
tDT
Output Clock Duty Cycle

4
tPH
Output Phase Accuracy
tOPJIT1
Output Clock Period Jitter
tSK
tW
tLOCK2
PLL Lock-in Time
tPA
Programmable Delay Unit
tIPJIT
Input Clock Period Jitter
tFBKDLY
External Feedback Delay
tHI
fOUT >= 100 MHz
+/-120
ps
fOUT < 100 MHz
0.02
UIPP
Input Clock to Output Clock Skew
Divider ratio = integer
+/-200
ps
Output Clock Pulse Width
At 90% or 10%3
ns
150
100
450
ps
fOUT 100 MHz
+/-200
ps
fOUT < 100 MHz
0.02
UI
10
ns
Input Clock High Time
90% to 90%
0.5
ns
tLO
Input Clock Low Time
10% to 10%
0.5
ns
tRST
RST Pulse Width
10
ns
1.
2.
3.
4.
5.
6.
Jitter sample is taken over 10,000 samples of the primary PLL output with a clean reference clock.
Output clock is valid after tLOCK for PLL reset and dynamic delay adjustment.
Using LVDS output buffers.
CLKOS as compared to CLKOP output.
When using an input frequency less than 25 MHz the output frequency must be less than or equal to 4 times the input frequency.
The on-chip oscillator can be used to provide reference clock input to the PLL provided the output frequency restriction for clock
inputs below 25 MHz are followed.
Rev. A 0.19
3-14

MachXO C Sleep Mode Timing

Symbol
tPWRDN
tPWRUP
Parameter
Device
SLEEPN Low to Power Down
SLEEPN High to Power Up
Min.
Typ.
Max
Units
All
400
ns
LCMXO256
400
LCMXO640
600
LCMXO1200
800
LCMXO2280
1000
tWSLEEPN
SLEEPN Pulse Width
All
400
ns
tWAWAKE
SLEEPN Pulse Rejection
All
100
ns
Rev. A 0.19
Flash Download Time

Power Down Mode
I/O
tPWRUP
tPWRDN
SLEEPN
tWSLEEPN or tWAWAKE
Symbol
Parameter
LCMXO256
tREFRESH
Minimum VCC or VCCAUX LCMXO640

(later of the two supplies)
LCMXO1200
to Device I/O Active
LCMXO2280
Min.
Typ.
Max.
Units
0.4
ms
0.6
ms
0.8
ms
1.0
ms
JTAG Port Timing Specifications

Min.
Max.
Units
fMAX
Symbol
TCK [BSCAN] clock frequency
Parameter
25
MHz
tBTCP
TCK [BSCAN] clock pulse width
40
ns
tBTCPH
TCK [BSCAN] clock pulse width high
20
ns
tBTCPL
TCK [BSCAN] clock pulse width low
20
ns
tBTS
TCK [BSCAN] setup time
ns
tBTH
TCK [BSCAN] hold time
10
ns
tBTRF
TCK [BSCAN] rise/fall time
50
mV/ns
tBTCO
TAP controller falling edge of clock to output valid
10
ns
tBTCODIS
TAP controller falling edge of clock to output disabled
10
ns
tBTCOEN
TAP controller falling edge of clock to output enabled
10
ns
tBTCRS
BSCAN test capture register setup time
ns
tBTCRH
BSCAN test capture register hold time
25
ns
tBUTCO
BSCAN test update register, falling edge of clock to output valid
25
ns
tBTUODIS
BSCAN test update register, falling edge of clock to output disabled
25
ns
tBTUPOEN
BSCAN test update register, falling edge of clock to output enabled
25
ns
Rev. A 0.19
3-15

Figure 3-5. JTAG Port Timing Waveforms
TMS
TDI
tBTS
tBTCPH
tBTH
tBTCP
tBTCPL
TCK
tBTCO
tBTCOEN
TDO
Valid Data
tBTCRS
Data to be
captured
from I/O
tBTCODIS
Valid Data
tBTCRH
Data Captured
tBTUPOEN
tBUTCO
Data to be
driven out
to I/O
Valid Data
3-16
tBTUODIS
Valid Data

Switching Test Conditions

Figure 3-6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Figure 3-5.
Figure 3-6. Output Test Load, LVTTL and LVCMOS Standards
VT
R1
DUT
Test Point
CL
Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition
LVTTL and LVCMOS settings (L -> H, H -> L)
R1
CL
0pF
Timing Ref.
VT
LVTTL, LVCMOS 3.3 = 1.5V
LVCMOS 2.5 = VCCIO/2

LVTTL and LVCMOS 3.3 (Z -> H)
1.5
LVTTL and LVCMOS 3.3 (Z -> L)

Other LVCMOS (Z -> H)
Other LVCMOS (Z -> L)
188
0pF
VOL
VOH
VCCIO/2
VOL
VCCIO/2
VOH
LVTTL + LVCMOS (H -> Z)
VOH - 0.15
VOL
LVTTL + LVCMOS (L -> Z)
VOL - 0.15
VOH
Note: Output test conditions for all other interfaces are determined by the respective standards.
3-17

Pinout Information
June 2013
Data Sheet DS1002
Signal Descriptions
Signal Name
I/O
Descriptions
General Purpose
[Edge] indicates the edge of the device on which the pad is located. Valid edge designations are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on which the
PIO Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number.
When Edge is L (Left) or R (Right), only need to specify Column Number.
P[Edge] [Row/Column
Number]_[A/B/C/D/E/F]
[A/B/C/D/E/F] indicates the PIO within the group to which the pad is connected.
I/O
Some of these user programmable pins are shared with special function pins. When not
used as special function pins, these pins can be programmed as I/Os for user logic.
During configuration of the user-programmable I/Os, the user has an option to tri-state the
I/Os and enable an internal pull-up resistor. This option also applies to unused pins (or
those not bonded to a package pin). The default during configuration is for user-programmable I/Os to be tri-stated with an internal pull-up resistor enabled. When the device is
erased, I/Os will be tri-stated with an internal pull-up resistor enabled.
GSRN
Global RESET signal (active low). Dedicated pad, when not in use it can be used as an I/O
pin.
TSALL
TSALL is a dedicated pad for the global output enable signal. When TSALL is high all the
outputs are tristated. It is a dual function pin. When not in use, it can be used as an I/O pin.
NC
No connect.
GND
GND - Ground. Dedicated pins.
VCC
VCC - The power supply pins for core logic. Dedicated pins.
VCCAUX
VCCAUX - the Auxiliary power supply pin. This pin powers up a variety of internal circuits
including all the differential and referenced input buffers. Dedicated pins.
VCCIOx
VCCIO - The power supply pins for I/O Bank x. Dedicated pins.
SLEEPN
Sleep Mode pin - Active low sleep pin. When this pin is held high, the device operates
normally. This pin has a weak internal pull-up, but when unused, an external pull-up to
VCC is recommended. When driven low, the device moves into Sleep mode after a specified time.
PLL and Clock Functions (Used as user programmable I/O pins when not used for PLL or clock pins)
[LOC][0]_PLL[T, C]_IN
Reference clock (PLL) input Pads: [LOC] indicates location. Valid designations are ULM
(Upper PLL) and LLM (Lower PLL). T = true and C = complement.
[LOC][0]_PLL[T, C]_FB
Optional feedback (PLL) input Pads: [LOC] indicates location. Valid designations are ULM
(Upper PLL) and LLM (Lower PLL). T = true and C = complement.
PCLK [n]_[1:0]
Primary Clock Pads, n per side.
Test and Programming (Dedicated pins)

TMS
Test Mode Select input pin, used to control the 1149.1 state machine.
TCK
Test Clock input pin, used to clock the 1149.1 state machine.
TDI
Test Data input pin, used to load data into the device using an 1149.1 state machine.
TDO
Output pin -Test Data output pin used to shift data out of the device using 1149.1.
1. Applies to MachXO C devices only. NC for E devices.
www.latticesemi.com
4-1
DS1002 Pinouts_01.9
Pinout Information
Pin Information Summary

LCMXO256C/E
LCMXO640C/E
100 TQFP
100 csBGA
100 TQFP
144 TQFP
100 csBGA
132 csBGA
256 caBGA /
256 ftBGA
Single Ended User I/O
78
78
74
113
74
101
159
Differential Pair User I/O1
38
38
17
43
17
42
79
Muxed
TAP
Pin Type
Dedicated (Total Without Supplies)
VCC
VCCAUX
VCCIO
Bank0
Bank1
Bank2
Bank3
10
12
10
12
18
GND
NC
Single Ended/Differential I/O

per Bank
52
Bank0
41/20
41/20
18/5
29/10
18/5
26/11
42/21
Bank1
37/18
37/18
21/4
30/11
21/4
27/12
40/20
Bank2
14/2
24/9
14/2
21/9
36/18
Bank3
21/6
30/13
21/6
27/10
40/20
1. These devices support emulated LVDS outputs.LVDS inputs are not supported.
LCMXO1200C/E
Pin Type
LCMXO2280C/E
256 caBGA /
132 csBGA 256 ftBGA
100 TQFP
144 TQFP
Single Ended User I/O
73
113
101
Differential Pair User I/O1
27
48
42
100 TQFP
144 TQFP
132 csBGA
256 caBGA /
256 ftBGA
211
73
113
101
211
271
105
30
47
41
105
134
324 ftBGA
Muxed
TAP
Dedicated (Total Without Supplies)
VCC
VCCAUX
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
12
12
18
12
12
18
24
VCCIO
GND
NC
10/3
14/6
13/5
26/13
9/3
13/6
12/5
24/12
34/17
Bank1
8/2
15/7
13/5
28/14
9/3
16/7
14/5
30/15
36/18
Bank2
10/4
15/7
13/6
26/13
10/4
15/7
13/6
26/13
34/17
Bank3
11/5
15/7
14/7
28/14
11/5
15/7
14/7
28/14
34/17
Bank4
8/3
14/5
13/5
27/13
8/3
14/4
13/4
29/14
35/17
Bank5
5/2
10/4
8/2
22/11
5/2
10/4
8/2
20/10
30/15
Bank6
10/3
15/6
13/6
28/14
10/4
15/6
13/6
28/14
34/17
Bank7
11/5
15/6
14/6
26/13
11/5
15/6
14/6
26/13
34/17
Bank0
Single Ended/Differential I/O

per Bank
1. These devices support on-chip LVDS buffers for left and right I/O Banks.
4-2
Pinout Information
Power Supply and NC

Signal
100 TQFP1
144 TQFP1
100 csBGA2
VCC
LCMXO256/640: 35, 90
LCMXO1200/2280: 17, 35, 66, 91
21, 52, 93, 129
P7, B6
VCCIO0
LCMXO256: 60, 74, 92

LCMXO640: 80, 92
LCMXO1200/2280: 94
LCMXO640: 117, 135

LCMXO1200/2280: 135
LCMXO256: H14, A14, B5

LCMXO640: B12, B5
VCCIO1
LCMXO256: 10, 24, 41

LCMXO640: 60, 74
LCMXO1200/2280: 80
LCMXO640: 82, 98
LCMXO1200/2280: 117
LCMXO256: G1, P1, P10

LCMXO640: H14, A14
VCCIO2
LCMXO256: None
LCMXO640: 29, 41
LCMXO1200/2280: 70
LCMXO640: 38, 63
LCMXO1200/2280: 98
LCMXO256: None
LCMXO640: P4, P10
VCCIO3
LCMXO256: None
LCMXO640: 10, 24
LCMXO1200/2280: 56
LCMXO640: 10, 26
LCMXO1200/2280: 82
LCMXO256: None
LCMXO640: G1, P1
VCCIO4
LCMXO256/640: None
LCMXO1200/2280: 44
LCMXO640: None
LCMXO1200/2280: 63
VCCIO5
LCMXO256/640: None
LCMXO1200/2280: 27
LCMXO640: None
LCMXO1200/2280: 38
VCCIO6
LCMXO256/640: None
LCMXO1200/2280: 20
LCMXO640: None
LCMXO1200/2280: 26
VCCIO7
LCMXO256/640: None
LCMXO1200/2280: 6
LCMXO640: None
LCMXO1200/2280: 10
VCCAUX
LCMXO256/640: 88
LCMXO1200/2280: 36, 90
53, 128
B7
GND3
LCMXO256: 40, 84, 62, 75, 93, 12, 16, 59, 88, 123, 118, 136, 83, 99,
25, 42
37, 64, 11, 27
LCMXO640: 40, 84, 81, 93, 62, 75,
30, 42, 12, 25
LCMXO1200/2280: 9, 41, 59, 83,
100, 76, 50, 26
NC4
LCMXO256: N9, B9, G14, B13,

A4, H1, N2, N10
LCMXO640: N9, B9, A10, A4,
G14, B13, N3, N10, H1, N2
1. Pin orientation follows the conventional order from pin 1 marking of the top side view and counter-clockwise.
2. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.
3. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of
GND logic connections from the die to the common package GND plane.
4. NC pins should not be connected to any active signals, VCC or GND.
4-3
Pinout Information
Power Supply and NC (Cont.)

132 csBGA1
Signal
256 caBGA / 256 ftBGA1
324 ftBGA1
VCC
H3, P6, G12, C7
G7, G10, K7, K10
F14, G11, G9, H7, L7, M9
VCCIO0
LCMXO640: B11, C5
LCMXO1200/2280: C5
LCMXO640: F8, F7, F9, F10

LCMXO1200/2280: F8, F7
G8, G7
VCCIO1
LCMXO640: L12, E12

LCMXO1200/2280: B11
LCMXO640: H11, G11, K11, J11

LCMXO1200/2280: F9, F10
G12, G10
VCCIO2
LCMXO640: N2, M10

LCMXO1200/2280: E12
LCMXO640: L9, L10, L8, L7

LCMXO1200/2280: H11, G11
J12, H12
VCCIO3
LCMXO640: D2, K3
LCMXO1200/2280: L12
LCMXO640: K6, J6, H6, G6

LCMXO1200/2280: K11, J11
L12, K12
VCCIO4
LCMXO640: None
LCMXO1200/2280: M10
LCMXO640: None
LCMXO1200/2280: L9, L10
M12, M11
VCCIO5
LCMXO640: None
LCMXO1200/2280: N2
LCMXO640: None
LCMXO1200/2280: L8, L7
M8, R9
VCCIO6
LCMXO640: None
LCMXO1200/2280: K3
LCMXO640: None
LCMXO1200/2280: K6, J6
M7, K7
VCCIO7
LCMXO640: None
LCMXO1200/2280: D2
LCMXO640: None
LCMXO1200/2280: H6, G6
H6, J7
M10, F9
VCCAUX
P7, A7
T9, A8
GND2
F1, P9, J14, C9, A10, B4, L13,

D13, P2, N11, E1, L2
A1, A16, F11, G8, G9, H7, H8, H9, E14, F16, H10, H11, H8, H9, J10,
H10, J7, J8, J9, J10, K8, K9, L6,
J11, J4, J8, J9, K10, K11, K17, K8,
T1, T16
K9, L10, L11, L8, L9, N2, P14, P5,
R7
NC3
LCMXO640: E4, E5, F5, F6, C3,

C2, G4, G5, H4, H5, K5, K4, M5,
M4, P2, P3, N5, N6, M7, M8, N10,
N11, R15, R16, P15, P16, M11,
L11, N12, N13, M13, M12, K12,
J12, F12, F13, E12, E13, D13,
D14, B15, A15, C14, B14, E11,
E10, E7, E6, D4, D3, B3, B2
LCMXO1200: None
LCMXO2280: None
1. Pin orientation A1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and numerical order ascending horizontally.
2. All grounds must be electrically connected at the board level. For fpBGA and ftBGA packages, the total number of GND balls is less than the actual number of
GND logic connections from the die to the common package GND plane.
3. NC pins should not be connected to any active signals, VCC or GND.
4-4
Pinout Information
LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP

LCMXO256
Pin Number
Ball
Function
Bank
PL2A
2
3
4
5
6
Dual
Function
LCMXO640
Differential
Ball
Function
Bank
PL2A
PL2B
PL2C
PL3A
PL2B
PL3B
PL2D
PL3C
PL3A
PL3D
PL3B
PL4A
PL3C
PL4B
PL3D
PL5A
PL4A
10
VCCIO1
11
PL5B
12
GNDIO1
VCCIO3
PL4C
GNDIO3
13
PL5C
14
PL5D
15
PL6A
16
PL6B
17
PL7A
18
PL7B
19
PL7C
PL9C
20
PL7D
PL10A
21
PL8A
PL10C
GSRN
TSALL
PL4D
PL5B
PL7B
PL8C
PL8D
PL9A
22
PL8B
PL11A
23
PL9A
PL11C
24
VCCIO1
VCCIO3
25
GNDIO1
26
TMS
27
PL9B
28
TCK
29
PB2A
30
PB2B
GNDIO3
TMS
PB2C
TCK
VCCIO2
GNDIO2
TDO
PB4C
TDI
PB4E
VCC
PB5B
PB5D
PB6B
PB6C
TMS
TCK
31
TDO
32
PB2C
TDO
33
TDI
34
PB2D
35
VCC
36
PB3A
37
PB3B
38
PB3C
39
PB3D
40
GND
GND
41
VCCIO1
VCCIO2
42
GNDIO1
GNDIO2
TDI
C
PCLK1_1**
PCLK1_0**
4-5
Dual
Function
Differential
T
T
C
GSRN
TSALL
T
C
TMS
TCK
TDO
TDI
PCLK2_1**
PCLK2_0**
Pinout Information
LCMXO256 and LCMXO640 Logic Signal Connections: 100 TQFP (Cont.)

LCMXO256
Pin Number
Ball
Function
Bank
43
PB4A
44
45
46
Differential
Ball
Function
Bank
PB8B
PB4B
PB8C
PB4C
PB8D
PB4D
PB9A
47
PB5A
48*
SLEEPN
49
PB5C
Dual
Function
LCMXO640
SLEEPN
T
PB9C
SLEEPN
PB9D
Dual
Function
Differential
T
SLEEPN
C
50
PB5D
PB9F
51
PR9B
PR11D
52
PR9A
PR11B
53
PR8B
PR11C
54
PR8A
PR11A
55
PR7D
PR10D
56
PR7C
PR10C
57
PR7B
PR10B
58
PR7A
PR10A
59
PR6B
60
VCCIO0
61
PR6A
62
GNDIO0
GNDIO1
63
PR5D
PR7B
64
PR5C
PR6C
65
PR5B
PR6B
66
PR5A
PR5D
67
PR4B
PR5B
68
PR4A
PR4D
69
PR3D
PR4B
70
PR3C
PR3D
71
PR3B
PR3B
72
PR3A
PR2D
73
PR2B
PR2B
74
VCCIO0
VCCIO1
75
GNDIO0
GNDIO1
76
PR2A
PT9F
77
PT5C
PT9E
78
PT5B
PT9C
79
PT5A
PT9A
80
PT4F
VCCIO0
81
PT4E
GNDIO0
82
PT4D
PT7E
83
PT4C
PT7A
84
GND
GND
4-6
PR9D
VCCIO1
PR9B
Pinout Information

LCMXO256
LCMXO640
Pin Number
Ball
Function
Bank
Dual
Function
Differential
Ball
Function
Bank
Dual
Function
85
PT4B
PCLK0_1**
PT6B
PCLK0_1**
PCLK0_0**
PCLK0_0**
86
PT4A
87
PT3D
88
VCCAUX
89
PT3C
90
VCC
91
PT3B
92
VCCIO0
93
GNDIO0
94
PT3A
95
PT2F
96
PT2E
97
Differential
PT5B
PT5A
VCCAUX
PT4F
VCC
PT3F
VCCIO0
GNDIO0
PT3B
PT3A
PT2F
PT2D
PT2E
98
PT2C
PT2B
99
PT2B
PT2C
100
PT2A
PT2A
T
C
* NC for E devices.
** Primary clock inputs are single-ended.
4-7
C
T
Pinout Information
LCMXO1200 and LCMXO2280 Logic Signal Connections: 100 TQFP

LCMXO1200
Pin
Number
Ball
Function
Bank
PL2A
Dual
Function
LCMXO2280
Differential
Ball
Function
Bank
Dual
Function
Differential
PL2A
LUM0_PLLT_FB_A
PL2B
PL2B
LUM0_PLLC_FB_A
PL3C
PL3C
LUM0_PLLT_IN_A
PL3D
PL3D
LUM0_PLLC_IN_A
PL4B
PL4B
VCCIO7
VCCIO7
PL6A
T*
PL7A
PL6B
C*
PL7B
GSRN
C*
GND
GND
10
PL7C
PL9C
11
PL7D
PL9D
12
PL8C
PL10C
13
PL8D
PL10D
14
PL9C
PL11C
15
PL10A
T*
PL13A
T*
16
PL10B
C*
PL13B
C*
17
VCC
VCC
18
PL11B
PL14D
GSRN
19
PL11C
PL14C
20
VCCIO6
TSALL
VCCIO6
21
PL13C
PL16C
T*
C
TSALL
22
PL14A
LLM0_PLLT_FB_A
T*
PL17A
LLM0_PLLT_FB_A
T*
23
PL14B
LLM0_PLLC_FB_A
C*
PL17B
LLM0_PLLC_FB_A
C*
24
PL15A
LLM0_PLLT_IN_A
T*
PL18A
LLM0_PLLT_IN_A
T*
25
PL15B
LLM0_PLLC_IN_A
C*
LLM0_PLLC_IN_A
C*
26**
GNDIO6
GNDIO5
27
VCCIO5
28
TMS
TMS
TCK
PL18B
GNDIO6
GNDIO5
VCCIO5
TMS
TMS
TCK
29
TCK
30
PB3B
TCK
PB3B
31
PB4A
PB4A
32
PB4B
33
TDO
TDO
PB4B
TDO
TDO
34
TDI
TDI
TDI
TDI
35
VCC
VCC
36
VCCAUX
VCCAUX
37
PB6E
PB8E
38
PB6F
PB8F
39
PB7B
PCLK4_1****
PB10F
PCLK4_1****
40
PB7F
PCLK4_0****
PB10B
PCLK4_0****
41
GND
GND
T
C
4-8
T
C
T
C
Pinout Information

LCMXO1200
Pin
Number
Ball
Function
Bank
42
PB9A
Differential
Ball
Function
Bank
PB12A
43
PB9B
44
VCCIO4
45
PB10A
Dual
Function
LCMXO2280
46
PB10B
47***
SLEEPN
48
PB11A
49
PB11B
50**
GNDIO3
GNDIO4
51
PR16B
52
PR15B
SLEEPN
PB12B
VCCIO4
PB13A
Dual
Function
Differential
PB13B
SLEEPN
PB16A
PB16B
GNDIO3
GNDIO4
PR19B
C*
PR18B
C
SLEEPN
C*
53
PR15A
T*
PR18A
T*
54
PR14B
C*
PR17B
C*
55
PR14A
T*
PR17A
T*
56
VCCIO3
VCCIO3
57
PR12B
C*
PR15B
C*
58
PR12A
T*
PR15A
T*
59
GND
GND
60
PR10B
C*
PR13B
C*
61
PR10A
T*
PR13A
T*
62
PR9B
C*
PR11B
C*
63
PR9A
T*
PR11A
T*
64
PR8B
C*
PR10B
C*
65
PR8A
T*
PR10A
T*
66
VCC
VCC
67
PR6C
PR8C
68
PR6B
C*
PR8B
C*
69
PR6A
T*
PR8A
T*
70
VCCIO2
VCCIO2
71
PR4D
PR5D
72
PR4B
C*
PR5B
C*
73
PR4A
T*
PR5A
T*
74
PR2B
PR3B
C*
75
PR2A
PR3A
T*
76**
GNDIO1
GNDIO2
GNDIO1
GNDIO2
77
PT11C
PT15C
78
PT11B
PT14B
79
PT11A
PT14A
80
VCCIO1
VCCIO1
81
PT9E
PT12D
4-9
Pinout Information

LCMXO1200
Pin
Number
Ball
Function
Bank
82
PT9A
Dual
Function
LCMXO2280
Differential
Ball
Function
Bank
PT12C
Dual
Function
Differential
T
83
GND
GND
84
PT8B
PT11B
85
PT8A
PT11A
86
PT7D
PCLK1_1****
PT10B
PCLK1_1****
87
PT6F
PCLK0_0****
PT9B
PCLK1_0****
88
PT6D
PT8F
89
PT6C
PT8E
90
VCCAUX
VCCAUX
91
VCC
VCC
92
PT5B
PT6D
93
PT4B
PT6F
94
VCCIO0
VCCIO0
95
PT3D
PT4B
96
PT3C
PT4A
97
PT3B
PT3B
98
PT2B
PT2B
99
PT2A
PT2A
100**
GNDIO0
GNDIO7
GNDIO0
GNDIO7
*Supports true LVDS outputs.

**Double bonded to the pin.
***NC for "E" devices.
****Primary clock inputs are single-ended.
4-10
Pinout Information
LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA

LCMXO256
Ball
Number
Ball
Function
Bank
B1
PL2A
C1
D2
LCMXO640
Dual
Function
Differential
Ball
Number
Ball
Function
Bank
Dual
Function
Differential
B1
PL2A
PL2B
C1
PL2C
PL3A
D2
PL2B
D1
PL3B
D1
PL2D
C2
PL3C
C2
PL3A
E1
PL3D
E1
PL3B
E2
PL4A
E2
PL3C
F1
PL4B
F1
PL3D
F2
PL5A
F2
PL4A
G2
PL5B
G2
PL4C
H1
GNDIO1
H1
GNDIO3
H2
PL5C
H2
PL4D
J1
PL5D
J2
PL6A
K1
PL6B
K2
PL7A
L1
PL7B
L2
PL7C
M1
M2
N1
T
C
J1
PL5B
J2
PL7B
K1
PL8C
K2
PL8D
L1
PL9A
L2
PL9C
PL7D
M1
PL10A
PL8A
M2
PL10C
PL8B
N1
PL11A
M3
PL9A
M3
PL11C
N2
GNDIO1
N2
GNDIO3
P2
TMS
P2
TMS
P3
PL9B
N4
TCK
P4
PB2A
N3
PB2B
P5
TDO
N5
PB2C
P6
TDI
N6
PB2D
P7
VCC
N7
PB3A
P8
PB3B
N8
PB3C
P9
PB3D
N10
GNDIO1
GSRN
TSALL
TMS
C
P3
PB2C
N4
TCK
P4
VCCIO2
N3
GNDIO2
P5
TDO
N5
PB4C
P6
TDI
N6
PB4E
P7
VCC
TCK
TDO
TDI
PCLK1_1**
PCLK1_0**
N7
PB5B
P8
PB5D
N8
PB6B
P9
PB6C
N10
GNDIO2
T
C
GSRN
TSALL
T
C
TMS
TCK
TDO
TDI
PCLK2_1**
PCLK2_0**
P11
PB4A
P11
PB8B
N11
PB4B
N11
PB8C
P12
PB4C
P12
PB8D
N12
PB4D
N12
PB9A
4-11
Pinout Information
LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.)

LCMXO256
LCMXO640
Ball
Number
Ball
Function
Dual
Function
Differential
Bank
P13
PB5A
M12*
SLEEPN
P14
PB5C
N13
PB5D
Ball
Number
Ball
Function
Bank
P13
PB9C
M12*
SLEEPN
P14
PB9D
N13
PB9F
SLEEPN
Dual
Function
Differential
T
SLEEPN
C
N14
PR9B
N14
PR11D
M14
PR9A
M14
PR11B
L13
PR8B
L13
PR11C
L14
PR8A
L14
PR11A
M13
PR7D
M13
PR10D
K14
PR7C
K14
PR10C
K13
PR7B
K13
PR10B
J14
PR7A
J14
PR10A
J13
PR6B
J13
PR9D
H13
PR6A
G14
GNDIO0
H13
PR9B
G14
GNDIO1
G13
PR5D
G13
PR7B
F14
PR5C
F13
PR5B
F14
PR6C
F13
PR6B
E14
PR5A
E14
PR5D
E13
PR4B
E13
PR5B
D14
PR4A
D14
PR4D
D13
PR3D
D13
PR4B
C14
PR3C
C14
PR3D
C13
PR3B
C13
PR3B
B14
PR3A
B14
PR2D
C12
PR2B
C12
PR2B
B13
GNDIO0
B13
GNDIO1
A13
PR2A
A13
PT9F
A12
PT5C
A12
PT9E
B11
PT5B
B11
PT9C
A11
PT5A
A11
PT9A
B12
PT4F
B12
VCCIO0
A10
PT4E
A10
GNDIO0
B10
PT4D
B10
PT7E
A9
PT4C
A9
PT7A
A8
PT4B
PCLK0_1**
A8
PT6B
PCLK0_1**
B8
PT4A
PCLK0_0**
B8
PT5B
PCLK0_0**
A7
PT3D
A7
PT5A
B7
VCCAUX
B7
VCCAUX
A6
PT3C
A6
PT4F
B6
VCC
B6
VCC
A5
PT3B
A5
PT3F
T
C
4-12
C
T
Pinout Information
LCMXO256 and LCMXO640 Logic Signal Connections: 100 csBGA (Cont.)

LCMXO256
LCMXO640
Ball
Number
Ball
Function
Dual
Function
Differential
Ball
Number
Ball
Function
Bank
Bank
A4
GNDIO0
B4
PT3A
A3
PT2F
B3
PT2E
Dual
Function
Differential
A4
GNDIO0
B4
PT3B
A3
PT3A
B3
PT2F
A2
PT2D
A2
PT2E
C3
PT2C
C3
PT2B
A1
PT2B
A1
PT2C
B2
PT2A
B2
PT2A
N9
GND
N9
GND
B9
GND
B9
GND
B5
VCCIO0
B5
VCCIO0
A14
VCCIO0
A14
VCCIO1
H14
VCCIO0
H14
VCCIO1
P10
VCCIO1
P10
VCCIO2
G1
VCCIO1
G1
VCCIO3
P1
VCCIO1
P1
VCCIO3
*NC for E devices.

**Primary clock inputs are single-ended.
4-13
Pinout Information
LCMXO640, LCMXO1200 and LCMXO2280 Logic Signal Connections:

132 csBGA
LCMXO640
Ball
Ball # Function Bank
Dual
Function
LCMXO1200
Ball
Differential Ball # Function Bank
Dual
Function
LCMXO2280
Ball
Dual
Function
Differential
T
B1
PL2A
B1
PL2A
B1
PL2A
LUM0_PLLT_FB_A
C1
PL2B
C1
PL3C
C1
PL3C
LUM0_PLLT_IN_A
B2
PL2C
B2
PL2B
B2
PL2B
LUM0_PLLC_FB_A
C2
PL2D
C2
PL4A
T*
C2
PL4A
C3
PL3A
C3
PL3D
C3
PL3D
D1
PL3B
D1
PL4B
C*
D1
PL4B
D3
PL3D
D3
PL4C
D3
PL4C
E1
GNDIO3
E1
GNDIO7
E1
GNDIO7
E2
PL5A
E2
PL6A
E3
PL5B
E3
PL6B
F2
PL5D
F2
PL6D
F3
PL6B
F3
PL7C
G1
PL6C
G1
G2
PL6D
G3
PL7A
H2
PL7B
H1
PL7C
GSRN
T*
E2
PL7A
E3
PL7B
F2
PL7D
F3
PL9C
PL7D
G1
PL9D
G2
PL8C
G2
PL10C
G3
PL8D
G3
PL10D
H2
PL10A
T*
H2
PL12A
T*
H1
PL10B
C*
H1
PL12B
C*
VCC
H3
VCC
H3
VCC
J1
PL8A
J1
PL11B
J1
PL14D
J2
PL8C
J2
PL11C
J2
PL14C
J3
PL9A
J3
PL11D
J3
PL14B
K2
PL9B
K1
PL9C
L2
GNDIO3
L1
PL10A
L3
PL10B
M1
PL11A
N1
PL11B
M2
PL11C
C
C*
C*
GSRN
H3
TSALL
T*
LUM0_PLLC_IN_A
TSALL
T*
GSRN
C*
C
TSALL
K2
PL12A
T*
K2
PL15A
T*
K1
PL12B
C*
K1
PL15B
C*
L2
GNDIO6
L2
GNDIO6
L1
PL14A
LLM0_PLLT_FB_A
T*
L1
PL17A
LLM0_PLLT_FB_A
T*
L3
PL14B
LLM0_PLLC_FB_A
C*
L3
PL17B
LLM0_PLLC_FB_A
C*
M1
PL15A
LLM0_PLLT_IN_A
T*
M1
PL18A
LLM0_PLLT_IN_A
T*
N1
PL16A
N1
PL19A
M2
PL15B
C*
M2
PL18B
LLM0_PLLC_IN_A
C*
P1
PL11D
P2
GNDIO2
PL16B
GNDIO5
PL19B
GNDIO5
P3
TMS
P3
TMS
P3
TMS
PB2C
M3
PB2C
M3
PB2A
N3
PB2D
N3
PB2D
N3
PB2B
P4
TCK
PB3B
N4
PB3C
P5
PB3D
TCK
P4
TCK
M4
PB3B
N4
PB4A
P5
PB4B
TMS
P1
P2
M3
M4
TMS
P1
P2
LLM0_PLLC_IN_A
TCK
TMS
P4
TCK
M4
PB3B
TCK
N4
PB4A
P5
PB4B
N5
TDO
TDO
N5
TDO
TDO
N5
TDO
TDO
M5
TDI
TDI
M5
TDI
TDI
M5
TDI
TDI
N6
PB4E
N6
PB5C
N6
PB6C
P6
VCC
P6
VCC
M6
PB6A
M6
PB8A
P7
VCCAUX
P7
VCCAUX
N7
PB6F
N7
PB8F
M7
PB7B
M7
PB10F
N8
PB7C
N8
PB10C
P8
PB7D
P8
PB10D
M8
PB7F
N9
PB9A
P6
VCC
M6
PB4F
P7
VCCAUX
N7
PB5A
M7
PB5B
N8
PB5D
P8
PB6A
M8
PB6B
N9
PB7A
PCLK2_1***
PCLK2_0***
PCLK4_1***
PCLK4_0***
T
4-14
M8
PB10B
N9
PB12A
PCLK4_1***
PCLK4_0***
T
Pinout Information

132 csBGA (Cont.)
LCMXO640
Ball
Dual
Function
LCMXO1200
Ball
Dual
Function
LCMXO2280
Ball
Dual
Function
Differential
M9
PB7B
M9
PB9B
M9
PB12B
N10
PB7E
N10
PB9C
N10
PB12C
P10
PB7F
P10
PB9D
P10
PB12D
N11
GNDIO2
N11
GNDIO4
N11
GNDIO4
P11
PB8C
P11
PB10A
P11
PB13C
M11
PB8D
M11
PB10B
M11
PB13D
P12
PB9C
P12
PB10C
P12
PB15B
P13
PB9D
P13
PB11C
P13
PB16C
N12**
SLEEPN
N12**
SLEEPN
N12**
SLEEPN
P14
PB9F
N14
PR11D
M14
PR11C
N13
PR11B
M12
PR11A
M13
L14
SLEEPN
T
SLEEPN
T
SLEEPN
P14
PB11D
P14
PB16D
N14
PR16B
N14
PR19B
M14
PR15B
C*
M14
PR18B
C*
N13
PR16A
N13
PR19A
M12
PR15A
T*
M12
PR18A
T*
PR10B
M13
PR14B
C*
M13
PR17B
C*
PR10A
L14
PR14A
T*
L14
PR17A
T*
L13
GNDIO1
L13
GNDIO3
L13
GNDIO3
K14
PR8D
K14
PR12B
C*
K14
PR15B
K13
PR8C
K13
PR12A
T*
K13
PR15A
T*
K12
PR8B
K12
PR11B
C*
K12
PR14B
C*
J13
PR8A
J13
PR11A
T*
J13
PR14A
T*
J12
PR7C
J12
PR10B
C*
J12
PR13B
C*
H14
PR7B
H14
PR10A
T*
H14
PR13A
T*
H13
PR7A
H13
PR9B
C*
H13
PR11B
C*
C*
H12
PR6D
H12
PR9A
T*
H12
PR11A
T*
G13
PR6C
G13
PR8B
C*
G13
PR10B
C*
G14
PR6B
G14
PR8A
T*
G14
PR10A
T*
G12
VCC
G12
VCC
G12
VCC
F14
PR5D
F14
PR6C
F14
PR8C
F13
PR5C
F13
PR6B
C*
F13
PR8B
F12
PR4D
F12
PR6A
T*
F12
PR8A
T*
E13
PR4C
E13
PR5B
C*
E13
PR7B
C*
T*
T*
E14
PR4B
E14
PR5A
D13
GNDIO1
D13
GNDIO2
D14
PR3D
D14
PR4B
D12
PR3C
D12
PR4A
C14
PR2D
C14
PR3D
B14
PR2C
B14
C13
PR2B
A14
PR2A
C*
E14
PR7A
D13
GNDIO2
C*
D14
PR5B
C*
T*
D12
PR5A
T*
C14
PR4D
PR2B
B14
PR3B
C*
C13
PR3C
C13
PR4C
A14
PR2A
A14
PR3A
T*
A13
PT9F
A13
PT11D
A13
PT16D
A12
PT9E
A12
PT11B
A12
PT16B
B13
PT9D
B13
PT11C
B12
PT9C
B12
PT10F
C12
PT9B
C12
PT11A
A11
PT9A
A11
PT10D
C11
PT8C
C11
PT10C
A10
GNDIO0
A10
GNDIO1
B13
PT16C
B12
PT15D
C12
PT16A
A11
PT14B
C11
PT14A
A10
GNDIO1
B10
PT7F
B10
PT9F
B10
PT12F
C10
PT7E
C10
PT9E
C10
PT12E
4-15
Pinout Information

132 csBGA (Cont.)
LCMXO640
Ball
Dual
Function
LCMXO1200
Ball
Dual
Function
LCMXO2280
Ball
B9
PT7B
B9
PT9B
B9
PT12D
A9
PT7A
A9
PT9A
A9
PT12C
A8
PT6B
PCLK0_1***
A8
PT7D
PCLK1_1***
A8
PT10B
B8
PT7B
B8
PT9D
PCLK0_0***
C8
PT6F
PCLK1_0***
C8
PT9B
B7
PT6D
B7
PT8D
0
-
B8
PT6A
C8
PT5B
B7
PT5A
Dual
Function
Differential
C
T
PCLK1_1***
PCLK1_0***
A7
VCCAUX
A7
VCCAUX
A7
VCCAUX
C7
VCC
C7
VCC
C7
VCC
A6
PT4D
A6
PT5D
A6
PT7B
B6
PT4C
B6
PT5C
B6
PT7A
C6
PT3F
C6
PT5B
C6
PT6D
B5
PT3E
A5
PT3D
B5
PT5A
A5
PT4B
B4
GNDIO0
A4
PT3B
C4
PT2F
A3
PT2D
B4
GNDIO0
A4
PT3D
C4
PT3C
A3
PT3B
A2
PT2C
A2
B3
PT2B
B3
PT2B
A2
PT3A
B3
A1
PT2A
A1
PT2A
A1
F1
GND
F1
GND
B5
PT6E
A5
PT6F
B4
GNDIO0
A4
PT4B
C4
PT4A
A3
PT3B
PT2B
PT3A
PT2A
F1
GND
P9
GND
P9
GND
P9
GND
J14
GND
J14
GND
J14
GND
C9
GND
C9
GND
C9
GND
C5
VCCIO0
C5
VCCIO0
C5
VCCIO0
B11
VCCIO0
B11
VCCIO1
B11
VCCIO1
E12
VCCIO1
E12
VCCIO2
E12
VCCIO2
L12
VCCIO1
L12
VCCIO3
L12
VCCIO3
M10
VCCIO2
M10
VCCIO4
M10
VCCIO4
N2
VCCIO2
N2
VCCIO5
N2
VCCIO5
D2
VCCIO3
D2
VCCIO7
D2
VCCIO7
K3
VCCIO3
K3
VCCIO6
K3
VCCIO6

**NC for E devices.
***Primary clock inputs arer single-ended.
4-16
Pinout Information

144 TQFP
LCMXO640
Pin
Number
Ball
Function
Bank
PL2A
Dual
Function
LCMXO1200
Dual
Function
LCMXO2280
Differential
Ball
Function
Differential
Ball
Function
Bank
Bank
Dual
Function
PL2A
PL2A
LUM0_PLLT_FB_A
PL2C
PL2B
PL2B
LUM0_PLLC_FB_A
PL2B
PL3A
T*
PL3A
T*
PL3A
PL3B
C*
PL3B
C*
PL2D
PL3C
PL3C
LUM0_PLLT_IN_A
PL3B
PL3D
PL3D
LUM0_PLLC_IN_A
PL3C
PL4A
T*
PL4A
T*
PL3D
PL4B
C*
PL4B
C*
Differential
PL4A
PL4C
PL4C
10
VCCIO3
VCCIO7
VCCIO7
11
GNDIO3
GNDIO7
GNDIO7
12
PL4D
PL6C
13
PL5A
14
PL5B
15
PL5D
16
GND
17
PL6C
18
PL6D
19
PL7A
PL10A
T*
PL13A
T*
20
PL7B
PL10B
C*
PL13B
C*
VCC
VCC
PL11A
T*
PL13D
PL5C
PL6A
PL6B
PL6D
GND
T
PL7C
PL7D
21
VCC
22
PL8A
23
PL8B
24
PL8C
25
PL9C
GSRN
C
TSALL
T
T*
PL7A
C*
PL7B
PL7D
GND
PL9C
PL9D
PL11B
PL11C
PL12B
GSRN
C*
TSALL
PL14D
PL14C
PL15B
T*
GSRN
C*
C
TSALL
26
VCCIO3
VCCIO6
VCCIO6
27
GNDIO3
GNDIO6
GNDIO6
28
PL9D
PL13D
PL16D
29
PL10A
PL14A
LLM0_PLLT_FB_A
T*
PL17A
LLM0_PLLT_FB_A
T*
30
PL10B
PL14B
LLM0_PLLC_FB_A
C*
PL17B
LLM0_PLLC_FB_A
C*
31
PL10C
PL14C
PL17C
32
PL11A
PL14D
PL17D
33
PL10D
PL15A
LLM0_PLLT_IN_A
T*
PL18A
LLM0_PLLT_IN_A
T*
34
PL11C
PL15B
LLM0_PLLC_IN_A
C*
PL18B
LLM0_PLLC_IN_A
C*
35
PL11B
PL16A
PL19A
36
PL11D
PL16B
PL19B
37
GNDIO2
GNDIO5
GNDIO5
38
VCCIO2
VCCIO5
VCCIO5
39
TMS
TMS
TMS
40
PB2C
PB2C
PB2A
41
PB3A
PB2D
PB2B
TMS
TCK
TCK
TCK
43
PB3B
PB3A
PB3A
44
PB3C
PB3B
PB3B
45
PB3D
PB4A
PB4A
46
PB4A
PB4B
PB4B
TDO
TDO
PB4D
PB4D
TDO
48
PB4B
TDO
TCK
TMS
42
47
TCK
TMS
TDO
TCK
TDO
49
PB4C
PB5A
PB5A
50
PB4D
PB5B
PB5B
4-17
Pinout Information

144 TQFP (Cont.)
LCMXO640
LCMXO1200
LCMXO2280
Pin
Number
Ball
Function
Bank
Dual
Function
Ball
Function
Bank
Dual
Function
51
TDI
TDI
TDI
TDI
52
VCC
53
VCCAUX
VCC
VCC
VCCAUX
VCCAUX
54
PB5A
55
PB5B
56
PB5D
57
PB6A
58
PB6B
59
GND
60
PB7C
61
PB7E
62
PB8A
63
VCCIO2
64
GNDIO2
GNDIO4
65
PB8C
PB10A
PB13A
66
PB8D
PB10B
PB13B
Differential
Differential
Ball
Function
Bank
Dual
Function
TDI
TDI
PB6F
PB7B
PB7C
PB7D
PB7F
GND
PB9A
PB9B
PB9E
PB12E
VCCIO4
VCCIO4
GNDIO4
PCLKT2_1***
PCLKT2_0***
Differential
PB8F
PB10F
PB10C
PB10D
PB10B
GND
PB12A
PB12B
PCLK4_1***
PCLK4_0***
PCLK4_1***
PCLK4_0***
67
PB9A
PB10C
PB13C
68
PB9C
PB10D
PB13D
PB14D
69
PB9B
70**
SLEEPN
71
PB9D
72
PB9F
73
PR11D
74
PR11B
75
PR11C
76
77
PB10F
SLEEPN
PB11C
PB11D
C
C
PR10D
PR11A
SLEEPN
SLEEPN
PB16C
PB16D
PR16B
PR20B
PR16A
PR20A
PR15B
C*
PR19B
PR15A
T*
PR19A
PR14D
PR17D
SLEEPN
SLEEPN
78
PR10B
PR14C
PR17C
79
PR10C
PR14B
C*
PR17B
C*
80
PR10A
PR14A
T*
PR17A
T*
81
PR9D
PR13D
PR16D
82
VCCIO1
VCCIO3
VCCIO3
83
GNDIO1
GNDIO3
GNDIO3
84
PR9A
PR12B
C*
PR15B
85
PR8C
PR12A
T*
PR15A
T*
86
PR8A
PR11B
C*
PR14B
C*
87
PR7D
PR11A
T*
PR14A
T*
88
GND
GND
GND
89
PR7B
PR10B
C*
PR13B
90
PR7A
PR10A
T*
PR13A
T*
91
PR6D
PR8B
C*
PR10B
C*
92
PR6C
PR8A
T*
PR10A
T*
93
VCC
VCC
VCC
94
PR5D
PR6B
C*
PR8B
95
PR5B
PR6A
T*
PR8A
T*
96
PR4D
PR5B
C*
PR7B
C*
T*
T*
97
PR4B
98
VCCIO1
99
GNDIO1
100
PR4A
PR5A
PR7A
VCCIO2
VCCIO2
GNDIO2
GNDIO2
PR4C
PR5C
4-18
C*
C*
C*
Pinout Information

144 TQFP (Cont.)
LCMXO640
Pin
Number
Ball
Function
Bank
101
PR3D
102
Dual
Function
LCMXO1200
Differential
Ball
Function
Bank
PR4B
PR3C
103
PR3B
104
PR2D
105
PR3A
Dual
Function
LCMXO2280
Differential
Ball
Function
Bank
Dual
Function
C*
PR5B
C*
PR4A
T*
PR5A
T*
PR3D
PR4D
PR3C
PR4C
PR3B
C*
PR4B
C*
Differential
106
PR2B
PR3A
T*
PR4A
T*
107
PR2C
PR2B
PR3B
C*
108
PR2A
PR2A
PR3A
T*
109
PT9F
PT11D
PT16D
110
PT9D
PT11C
PT16C
111
PT9E
PT11B
PT16B
112
PT9B
PT11A
PT16A
113
PT9C
PT10F
PT15D
114
PT9A
115
PT8C
116
PT8B
117
VCCIO0
118
GNDIO0
119
PT8A
120
PT7E
121
PT10E
PT15C
PT10D
PT14B
PT10C
PT14A
VCCIO1
VCCIO1
GNDIO1
GNDIO1
PT9F
PT12F
PT9E
PT12E
PT7C
PT9B
PT12D
122
PT7A
PT9A
PT12C
123
GND
GND
GND
124
PT6B
125
PT6A
126
PT5C
127
PT5B
128
VCCAUX
VCCAUX
VCCAUX
129
VCC
VCC
VCC
130
PT4D
PT5D
PT7B
131
PT4B
PT5C
PT7A
132
PT4A
PT5B
PT6D
PT6E
PT6F
PCLK0_1***
PT7D
PT10B
PT7B
PT9D
PT7A
PT9C
PT6F
PT9B
PCLK0_0***
133
PT3F
PT5A
134
PT3D
PT4B
PCLK1_1***
PCLK1_0***
PCLK1_1***
C
T
PCLK1_0***
135
VCCIO0
VCCIO0
VCCIO0
136
GNDIO0
GNDIO0
GNDIO0
137
PT3B
PT3D
PT4B
138
PT2F
PT3C
PT4A
C
C
139
PT3A
PT3B
PT3B
140
PT2D
PT3A
PT3A
141
PT2E
PT2D
PT2D
142
PT2B
PT2C
PT2C
143
PT2C
PT2B
PT2B
144
PT2A
PT2A
PT2A

**NC for E devices.
***Primary clock inputs arer single-ended.
4-19
Pinout Information

256 caBGA / 256 ftBGA
LCMXO640
Ball
Ball
Number Function Bank
Dual
Function
LCMXO1200
Ball
Ball
Differential Number Function Bank
Dual
Function
LCMXO2280
Ball
Ball
GND
GNDIO3
GND
GNDIO7
VCCIO3
VCCIO3
VCCIO7
VCCIO7
E4
NC
E4
PL2A
E5
NC
E5
PL2B
Dual
Function
Differential
GND
GNDIO7
VCCIO7
VCCIO7
E4
PL2A
LUM0_PLLT_FB_A
E5
PL2B
LUM0_PLLC_FB_A
F5
NC
F5
PL3A
T*
F5
PL3A
T*
F6
NC
F6
PL3B
C*
F6
PL3B
C*
F3
PL3A
F3
PL3C
F3
PL3C
LUM0_PLLT_IN_A
F4
PL3B
F4
PL3D
F4
PL3D
LUM0_PLLC_IN_A
E3
PL2C
E3
PL4A
T*
E3
PL4A
T*
E2
PL2D
E2
PL4B
C*
E2
PL4B
C*
C3
NC
C3
PL4C
C3
PL4C
C2
NC
C2
PL4D
C2
PL4D
B1
PL2A
B1
PL5A
T*
B1
PL5A
T*
C1
PL2B
C1
PL5B
C*
C1
PL5B
C*
VCCIO3
VCCIO3
VCCIO7
VCCIO7
VCCIO7
VCCIO7
GND
GNDIO3
GND
GNDIO7
GND
GNDIO7
D2
PL3C
D2
PL5C
D2
PL6C
D1
PL3D
D1
PL5D
D1
PL6D
F2
PL5A
G2
PL5B
GSRN
F2
PL6A
G2
PL6B
GSRN
T*
F2
PL7A
C*
G2
PL7B
T*
GSRN
C*
E1
PL4A
E1
PL6C
E1
PL7C
F1
PL4B
F1
PL6D
F1
PL7D
G4
NC
G4
PL7A
T*
G4
PL8A
T*
G5
NC
G5
PL7B
C*
G5
PL8B
C*
GND
GND
GND
GND
GND
GND
G3
PL4C
G3
PL7C
G3
PL8C
H3
PL4D
H3
PL7D
H3
PL8D
H4
NC
H4
PL8A
T*
H4
PL9A
T*
H5
NC
H5
PL8B
C*
H5
PL9B
C*
VCCIO7
VCCIO7
VCCIO7
VCCIO7
GND
GNDIO7
GND
GNDIO7
G1
PL5C
G1
PL8C
G1
PL10C
H1
PL5D
H1
PL8D
H1
PL10D
H2
PL6A
H2
PL9A
T*
H2
PL11A
T*
J2
PL6B
J2
PL9B
C*
J2
PL11B
C*
J3
PL7C
J3
PL9C
J3
PL11C
K3
PL7D
K3
PL9D
K3
PL11D
J1
PL6C
T*
T*
J1
PL10A
VCCIO6
VCCIO6
J1
PL12A
VCCIO6
VCCIO6
6
6
GND
GNDIO6
GND
GNDIO6
K1
PL6D
K1
PL10B
C*
K1
PL12B
K2
PL9A
K2
PL10C
K2
PL12C
L2
PL9B
L2
PL10D
L2
PL12D
C*
L1
PL7A
L1
PL11A
T*
L1
PL13A
T*
M1
PL7B
M1
PL11B
C*
M1
PL13B
C*
P1
PL8D
N1
PL8C
P1
PL11D
N1
PL11C
L3
PL10A
L3
PL12A
M3
M2
PL10B
M3
PL9C
M2
N2
PL9D
N2
TSALL
P1
PL14D
N1
PL14C
T*
L3
PL15A
T*
PL12B
C*
M3
PL15B
C*
PL12C
M2
PL15C
PL12D
N2
PL15D
TSALL
VCCIO3
VCCIO3
VCCIO6
VCCIO6
VCCIO6
VCCIO6
GND
GNDIO3
GND
GNDIO6
GND
GNDIO6
4-20
C
TSALL
Pinout Information

256 caBGA / 256 ftBGA (Cont.)
LCMXO640
Ball
Ball
Dual
Function
LCMXO1200
Ball
Ball
Dual
Function
LCMXO2280
Ball
Ball
Dual
Function
Differential
J4
PL8A
J4
PL13A
T*
J4
PL16A
T*
J5
PL8B
J5
PL13B
C*
J5
PL16B
C*
R1
PL11A
R1
PL13C
R1
PL16C
R2
PL11B
R2
PL13D
R2
PL16D
GND
GND
K5
NC
K5
PL14A
LLM0_PLLT_FB_A
T*
K5
PL17A
LLM0_PLLT_FB_A
T*
K4
NC
K4
PL14B
LLM0_PLLC_FB_A
C*
K4
PL17B
LLM0_PLLC_FB_A
C*
L5
PL10C
L5
PL14C
L5
PL17C
L4
PL10D
L4
PL14D
L4
PL17D
M5
NC
M5
PL15A
LLM0_PLLT_IN_A
T*
M5
PL18A
LLM0_PLLT_IN_A
T*
M4
NC
M4
PL15B
LLM0_PLLC_IN_A
C*
M4
PL18B
LLM0_PLLC_IN_A
C*
N4
PL11C
N4
PL16A
N4
PL19A
N3
PL11D
N3
PL16B
N3
PL19B
VCCIO3
VCCIO3
VCCIO6
VCCIO6
VCCIO6
VCCIO6
GND
GNDIO3
GND
GNDIO6
GND
GNDIO6
GND
GNDIO2
GND
GNDIO5
GND
GNDIO5
VCCIO2
VCCIO2
VCCIO5
VCCIO5
VCCIO5
VCCIO5
P4
TMS
P4
TMS
P4
TMS
P2
NC
P2
PB2A
P2
PB2A
P3
NC
P3
PB2B
P3
PB2B
N5
NC
R3
TCK
TMS
TCK
N5
PB2C
R3
TCK
TMS
T
TCK
N5
PB2C
R3
TCK
TMS
T
TCK
N6
NC
N6
PB2D
N6
PB2D
T2
PB2A
T2
PB3A
T2
PB3A
T3
PB2B
T3
PB3B
T3
PB3B
R4
PB2C
R4
PB3C
R4
PB3C
R5
PB2D
R5
PB3D
R5
PB3D
P5
PB3A
P5
PB4A
P5
PB4A
P6
PB3B
P6
PB4B
P6
PB4B
T5
PB3C
M6
TDO
T
TDO
T5
PB4C
M6
TDO
T
TDO
T5
PB4C
M6
TDO
T
TDO
T4
PB3D
T4
PB4D
T4
PB4D
R6
PB4A
R6
PB5A
R6
PB5A
GND
GNDIO2
GND
GNDIO5
GND
GNDIO5
VCCIO2
VCCIO2
VCCIO5
VCCIO5
VCCIO5
VCCIO5
T6
PB4B
T6
PB5B
T6
PB5B
N7
TDI
N7
TDI
N7
TDI
T8
PB4C
T8
PB5C
T8
PB6A
T7
PB4D
T7
PB5D
T7
PB6B
M7
NC
M7
PB6A
M7
PB7C
M8
NC
M8
PB6B
M8
PB7D
C
TDI
C
TDI
C
TDI
T9
VCCAUX
T9
VCCAUX
T9
VCCAUX
R7
PB4E
R7
PB6C
R7
PB8C
R8
PB4F
R8
PB6D
R8
PB8D
VCCIO5
VCCIO5
VCCIO5
VCCIO5
GND
GNDIO5
GND
GNDIO5
P7
PB5C
P7
PB6E
P7
PB9A
P8
PB5D
P8
PB6F
P8
PB9B
N8
PB5A
N9
PB5B
P10
PB7B
P9
PB7A
M9
PB6B
N8
PB7A
N9
PB7B
P10
PB7D
P9
PB7C
M9
PB7F
PCLK2_1***
PCLK2_0***
N8
PB10E
N9
PB10F
P10
PB10D
P9
PB10C
M9
PB10B
PCLK4_1***
PCLK4_0***
4-21
T
PCLK4_1***
C
C
T
PCLK4_0***
Pinout Information

LCMXO640
Ball
Ball
-
Dual
Function
LCMXO1200
Ball
Ball
VCCIO4
VCCIO4
Dual
Function
LCMXO2280
Ball
Ball
VCCIO4
VCCIO4
Dual
Function
Differential
GND
GNDIO4
GND
GNDIO4
M10
PB6A
M10
PB7E
M10
PB10A
R9
PB6C
R9
PB8A
R9
PB11C
R10
PB6D
R10
PB8B
R10
PB11D
T10
PB7C
T10
PB8C
T10
PB12A
T11
PB7D
T11
PB8D
T11
PB12B
N10
NC
N10
PB8E
N10
PB12C
N11
NC
N11
PB8F
N11
PB12D
VCCIO2
VCCIO2
VCCIO4
VCCIO4
VCCIO4
VCCIO4
GND
GNDIO2
GND
GNDIO4
GND
GNDIO4
R11
PB7E
R11
PB9A
R11
PB13A
R12
PB7F
R12
PB9B
R12
PB13B
P11
PB8A
P11
PB9C
P11
PB13C
P12
PB8B
P12
PB9D
P12
PB13D
T13
PB8C
T13
PB9E
T13
PB14A
T12
PB8D
T12
PB9F
T12
PB14B
R13
PB9A
R13
PB10A
R13
PB14C
R14
PB9B
R14
PB10B
R14
PB14D
GND
GND
GND
GND
GND
GND
T14
PB9C
T14
PB10C
T14
PB15A
T15
PB9D
T15
PB10D
T15
PB15B
P13**
SLEEPN
P13**
SLEEPN
P13**
SLEEPN
P14
PB9F
P14
PB10F
P14
PB15D
R15
NC
R15
PB11A
R15
PB16A
R16
NC
R16
PB11B
R16
PB16B
P15
NC
P15
PB11C
P15
PB16C
P16
NC
P16
PB11D
P16
PB16D
SLEEPN
SLEEPN
SLEEPN
VCCIO2
VCCIO2
VCCIO4
VCCIO4
VCCIO4
VCCIO4
GND
GNDIO2
GND
GNDIO4
GND
GNDIO4
GND
GNDIO1
GND
GNDIO3
GND
GNDIO3
VCCIO1
VCCIO1
VCCIO3
VCCIO3
VCCIO3
VCCIO3
M11
NC
M11
PR16B
M11
PR20B
L11
NC
L11
PR16A
L11
PR20A
N12
NC
N12
PR15B
C*
N12
PR18B
C*
N13
NC
N13
PR15A
T*
N13
PR18A
T*
M13
NC
M13
PR14D
M13
PR17D
M12
NC
M12
PR14C
M12
PR17C
N14
PR11D
N14
PR14B
C*
N14
PR17B
C*
N15
PR11C
N15
PR14A
T*
N15
PR17A
T*
L13
PR11B
L13
PR13D
L13
PR16D
L12
PR11A
L12
PR13C
L12
PR16C
M14
PR10B
M14
PR13B
C*
M14
PR16B
C*
VCCIO1
VCCIO1
VCCIO3
VCCIO3
VCCIO3
VCCIO3
GND
GNDIO1
GND
GNDIO3
GND
GNDIO3
L14
PR10A
L14
PR13A
T*
L14
PR16A
T*
N16
PR10D
N16
PR12D
N16
PR15D
M16
PR10C
M16
PR12C
M16
PR15C
M15
PR9D
M15
PR12B
C*
M15
PR15B
C*
L15
PR9C
L15
PR12A
T*
L15
PR15A
T*
L16
PR9B
L16
PR11D
L16
PR14D
K16
PR9A
K16
PR11C
K16
PR14C
K13
PR8D
K13
PR11B
C*
K13
PR14B
C*
4-22
Pinout Information

LCMXO640
Ball
Ball
J13
PR8C
GND
GND
K14
PR8B
J14
PR8A
K15
PR7D
J15
PR7C
Dual
Function
LCMXO1200
Ball
Ball
T
J13
PR11A
GND
GND
K14
PR10D
J14
PR10C
K15
PR10B
J15
GND
Dual
Function
LCMXO2280
Ball
Ball
T*
Dual
Function
Differential
J13
PR14A
GND
GND
K14
PR13D
J14
PR13C
C*
K15
PR13B
C*
PR10A
T*
T*
GNDIO3
J15
PR13A
GND
GNDIO3
T*
VCCIO3
VCCIO3
VCCIO3
VCCIO3
K12
NC
K12
PR9D
K12
PR11D
J12
NC
J12
PR9C
J12
PR11C
J16
PR7B
J16
PR9B
C*
J16
PR11B
C*
H16
PR7A
H16
PR9A
T*
H16
PR11A
T*
H15
PR6B
H15
PR8D
H15
PR10D
G15
PR6A
G15
PR8C
G15
PR10C
H14
PR5D
H14
PR8B
C*
H14
PR10B
C*
T*
T*
G14
PR5C
GND
GNDIO1
G14
PR8A
GND
GNDIO2
G14
PR10A
GND
GNDIO2
VCCIO1
VCCIO1
H13
PR6D
VCCIO2
VCCIO2
H13
PR7D
VCCIO2
VCCIO2
H13
PR9D
H12
PR6C
H12
PR7C
H12
PR9C
G13
PR4D
G13
PR7B
C*
G13
PR9B
C*
G12
PR4C
G16
PR5B
G12
G16
PR7A
T*
G12
PR9A
T*
PR6D
G16
PR7D
F16
PR5A
F16
PR6C
F16
PR7C
F15
PR4B
F15
PR6B
C*
F15
PR7B
C*
E15
PR4A
E16
PR3B
E15
PR6A
T*
E15
PR7A
T*
E16
PR5D
E16
PR6D
D16
PR3A
D16
PR5C
D16
PR6C
VCCIO1
VCCIO1
VCCIO2
VCCIO2
VCCIO2
VCCIO2
GND
GNDIO1
D15
PR2D
GND
GNDIO2
GND
GNDIO2
D15
PR5B
C*
D15
PR6B
C15
PR2C
C*
C15
PR5A
T*
C15
PR6A
C16
PR2B
T*
C16
PR4D
C16
PR5D
B16
PR2A
B16
PR4C
B16
PR5C
F14
PR3D
F14
PR4B
C*
F14
PR5B
C*
E14
PR3C
E14
PR4A
T*
T*
F12
NC
F12
PR3D
F13
NC
F13
PR3C
E12
NC
E12
PR3B
E13
NC
E13
D13
NC
D13
E14
PR5A
GND
GND
F12
PR4D
F13
PR4C
C*
E12
PR4B
C*
PR3A
T*
E13
PR4A
T*
PR2B
D13
PR3B
C*
T*
D14
NC
D14
PR2A
D14
PR3A
VCCIO0
VCCIO0
VCCIO2
VCCIO2
VCCIO2
VCCIO2
GND
GNDIO0
GND
GNDIO2
GND
GNDIO2
GND
GNDIO0
GND
GNDIO1
GND
GNDIO1
VCCIO0
VCCIO0
VCCIO1
VCCIO1
VCCIO1
VCCIO1
B15
NC
B15
PT11D
B15
PT16D
A15
NC
A15
PT11C
A15
PT16C
C14
NC
C14
PT11B
C14
PT16B
B14
NC
B14
PT11A
B14
PT16A
C13
PT9F
C13
PT10F
C13
PT15D
B13
PT9E
B13
PT10E
B13
PT15C
4-23
Pinout Information

LCMXO640
Ball
Ball
Dual
Function
LCMXO1200
Ball
Ball
Dual
Function
LCMXO2280
Ball
Ball
Dual
Function
Differential
E11
NC
E11
PT10D
E11
PT15B
E10
NC
E10
PT10C
E10
PT15A
C
T
D12
PT9D
D12
PT10B
D12
PT14D
D11
PT9C
D11
PT10A
D11
PT14C
A14
PT7F
A14
PT9F
A14
PT14B
A13
PT7E
A13
PT9E
A13
PT14A
C12
PT8B
C12
PT9D
C12
PT13D
C11
PT8A
C11
PT9C
VCCIO1
VCCIO1
C11
PT13C
VCCIO1
VCCIO1
GND
GNDIO1
GND
GNDIO1
B12
PT7B
B12
PT9B
B12
PT12D
B11
PT7A
B11
PT9A
B11
PT12C
A12
PT7D
A12
PT8F
A12
PT12B
A11
PT7C
A11
PT8E
GND
GND
GND
GND
A11
PT12A
GND
GND
B10
PT5D
B10
PT8D
B10
PT11B
B9
PT5C
B9
PT8C
B9
PT11A
D10
PT8D
D10
PT8B
D10
PT10F
D9
PT8C
D9
PT8A
VCCIO1
VCCIO1
D9
PT10E
VCCIO1
VCCIO1
GND
GNDIO1
GND
GNDIO1
C10
PT6D
C10
PT7F
C10
PT10D
C9
PT6C
C9
PT7E
C9
PT10C
A9
PT6B
A9
PT7D
A9
PT10B
PCLK0_1***
PCLK1_1***
C
T
PCLK1_1***
A10
PT6A
A10
PT7C
A10
PT10A
E9
PT9B
E9
PT7B
E9
PT9D
E8
PT7A
E8
PT9C
D7
PT6F
D7
PT9B
E8
PT9A
D7
PT5B
PCLK0_0***
PCLK1_0***
D8
PT5A
VCCIO0
VCCIO0
D8
PT6E
VCCIO0
VCCIO0
GND
GNDIO0
C8
PT4F
GND
GNDIO0
C8
PT6D
B8
PT4E
B8
PT6C
A8
VCCAUX
A8
VCCAUX
A7
PT4D
A6
PT4C
A7
PT6B
A6
PT6A
VCC
VCC
VCC
VCC
B7
PT4B
B7
PT5F
B6
PT4A
B6
PT5E
C6
PT3C
C6
PT5C
C7
PT3D
C7
PT5D
A5
PT3E
A5
PT5A
A4
PT3F
A4
PT5B
E7
NC
E7
PT4C
E6
NC
E6
PT4D
B5
PT3B
B5
B4
PT3A
B4
D5
PT2D
D5
D6
PT2C
C4
PT2E
C5
PT2F
D4
NC
D8
PT9A
VCCIO0
VCCIO0
GND
GNDIO0
C8
PT8D
B8
PT8C
A8
VCCAUX
A7
PT7D
A6
PT7C
VCC
VCC
B7
PT7B
B6
PT7A
C6
PT6A
C7
PT6B
A5
PT6C
A4
PT6D
E7
PT6E
E6
PT6F
PT3F
B5
PT5D
PT3E
B4
PT5C
PT3D
D5
PT5B
D6
PT3C
D6
PT5A
C4
PT4A
C4
PT4A
C5
PT4B
C5
PT4B
D4
PT2D
T
PCLK1_0***
4-24
GND
GND
D4
PT3D
Pinout Information

LCMXO640
Ball
Ball
D3
NC
A3
PT2B
A2
PT2A
B3
NC
Dual
Function
LCMXO1200
Ball
Ball
Dual
Function
LCMXO2280
Ball
Ball
Dual
Function
Differential
D3
PT2C
D3
PT3C
A3
PT3B
A3
PT3B
A2
PT3A
A2
PT3A
B3
PT2B
B3
PT2D
B2
NC
B2
PT2A
B2
PT2C
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
VCCIO0
GND
GNDIO0
GND
GNDIO0
GND
GNDIO0
A1
GND
A1
GND
A1
GND
A16
GND
A16
GND
A16
GND
F11
GND
F11
GND
F11
GND
G8
GND
G8
GND
G8
GND
G9
GND
G9
GND
G9
GND
H7
GND
H7
GND
H7
GND
H8
GND
H8
GND
H8
GND
H9
GND
H9
GND
H9
GND
H10
GND
H10
GND
H10
GND
J7
GND
J7
GND
J7
GND
J8
GND
J8
GND
J8
GND
J9
GND
J9
GND
J9
GND
J10
GND
J10
GND
J10
GND
K8
GND
K8
GND
K8
GND
K9
GND
K9
GND
K9
GND
L6
GND
L6
GND
L6
GND
T1
GND
T1
GND
T1
GND
T16
GND
T16
GND
T16
GND
G7
VCC
G7
VCC
G7
VCC
G10
VCC
G10
VCC
G10
VCC
K7
VCC
K7
VCC
K7
VCC
K10
VCC
K10
VCC
K10
VCC
H6
VCCIO3
H6
VCCIO7
H6
VCCIO7
G6
VCCIO3
G6
VCCIO7
G6
VCCIO7
K6
VCCIO3
K6
VCCIO6
K6
VCCIO6
J6
VCCIO3
J6
VCCIO6
J6
VCCIO6
L8
VCCIO2
L8
VCCIO5
L8
VCCIO5
L7
VCCIO2
L7
VCCIO5
L7
VCCIO5
L9
VCCIO2
L9
VCCIO4
L9
VCCIO4
L10
VCCIO2
L10
VCCIO4
L10
VCCIO4
K11
VCCIO1
K11
VCCIO3
K11
VCCIO3
J11
VCCIO1
J11
VCCIO3
J11
VCCIO3
H11
VCCIO1
H11
VCCIO2
H11
VCCIO2
G11
VCCIO1
G11
VCCIO2
G11
VCCIO2
F9
VCCIO0
F9
VCCIO1
F9
VCCIO1
F10
VCCIO0
F10
VCCIO1
F10
VCCIO1
F8
VCCIO0
F8
VCCIO0
F8
VCCIO0
F7
VCCIO0
F7
VCCIO0
F7
VCCIO0
* Supports true LVDS outputs.

** NC for E devices.
*** Primary clock inputs are single-ended.
4-25
Pinout Information
LCMXO2280 Logic Signal Connections: 324 ftBGA

LCMXO2280
Ball Number
Ball Function
Bank
GND
GNDIO7
VCCIO7
VCCIO7
Dual Function
Differential
D4
PL2A
LUM0_PLLT_FB_A
F5
PL2B
LUM0_PLLC_FB_A
B3
PL3A
C3
PL3B
E4
PL3C
LUM0_PLLT_IN_A
G6
PL3D
LUM0_PLLC_IN_A
T*
C*
A1
PL4A
T*
B1
PL4B
C*
F4
PL4C
VCC
VCC
E3
PL4D
D2
PL5A
T*
D3
PL5B
C*
G5
PL5C
F3
PL5D
C
T*
C2
PL6A
VCCIO7
VCCIO7
GND
GNDIO7
C1
PL6B
C*
H5
PL6C
G4
PL6D
E2
PL7A
D1
PL7B
T*
J6
PL7C
H4
PL7D
F2
PL8A
T*
E1
PL8B
C*
GSRN
C*
T
GND
GND
J3
PL8C
J5
PL8D
G3
PL9A
T*
H3
PL9B
C*
K3
PL9C
K5
PL9D
F1
PL10A
T*
VCCIO7
VCCIO7
GND
GNDIO7
G1
PL10B
C*
K4
PL10C
K6
PL10D
4-26
Pinout Information
LCMXO2280 Logic Signal Connections: 324 ftBGA (Cont.)

LCMXO2280
Ball Number
Ball Function
Bank
G2
PL11A
Dual Function
Differential
T*
H2
PL11B
C*
L3
PL11C
L5
PL11D
H1
PL12A
T*
VCCIO6
VCCIO6
GND
GNDIO6
J2
PL12B
C*
L4
PL12C
L6
PL12D
K2
PL13A
T*
K1
PL13B
C*
T
J1
PL13C
VCC
VCC
L2
PL13D
M5
PL14D
M3
PL14C
L1
PL14B
C*
M2
PL14A
T*
M1
PL15A
T*
N1
PL15B
C*
M6
PL15C
M4
PL15D
VCCIO6
VCCIO6
GND
GNDIO6
P1
PL16A
T*
P2
PL16B
C*
N3
PL16C
N4
PL16D
GND
GND
TSALL
T1
PL17A
LLM0_PLLT_FB_A
T*
R1
PL17B
LLM0_PLLC_FB_A
C*
P3
PL17C
N5
PL17D
R3
PL18A
LLM0_PLLT_IN_A
T*
R2
PL18B
LLM0_PLLC_IN_A
C*
P4
PL19A
N6
PL19B
C
T
U1
PL20A
VCCIO6
VCCIO6
GND
GNDIO6
GND
GNDIO5
VCCIO5
VCCIO5
4-27
T
C
Pinout Information

LCMXO2280
Ball Number
Ball Function
Bank
T2
PL20B
Dual Function
Differential
P6
TMS
V1
PB2A
U2
PB2B
T3
PB2C
N7
TCK
R4
PB2D
R5
PB3A
T4
PB3B
C
TMS
TCK
C
VCC
VCC
R6
PB3C
P7
PB3D
U3
PB4A
T5
PB4B
V2
PB4C
N8
TDO
V3
PB4D
T6
PB5A
TDO
GND
GNDIO5
VCCIO5
VCCIO5
U4
PB5B
P8
PB5C
T7
PB5D
V4
TDI
R8
PB6A
N9
PB6B
U5
PB6C
TDI
V5
PB6D
U6
PB7A
VCC
VCC
V6
PB7B
P9
PB7C
T8
PB7D
U7
PB8A
V7
PB8B
M10
VCCAUX
U8
PB8C
V8
PB8D
VCCIO5
VCCIO5
GND
GNDIO5
T9
PB8E
U9
PB8F
V9
PB9A
4-28
Pinout Information

LCMXO2280
Ball Number
Ball Function
Bank
V10
PB9B
Dual Function
Differential
N10
PB9C
R10
PB9D
P10
PB10F
T10
PB10E
PCLK4_1***
C
T
U10
PB10D
V11
PB10C
U11
PB10B
VCCIO4
VCCIO4
GND
GNDIO4
T11
PB10A
U12
PB11A
T
C
PCLK4_0***
R11
PB11B
GND
GND
T12
PB11C
P11
PB11D
V12
PB12A
V13
PB12B
R12
PB12C
N11
PB12D
U13
PB12E
VCCIO4
VCCIO4
GND
GNDIO4
V14
PB12F
T13
PB13A
P12
PB13B
R13
PB13C
N12
PB13D
V15
PB14A
U14
PB14B
C
T
V16
PB14C
GND
GND
T14
PB14D
U15
PB15A
V17
PB15B
P13**
SLEEPN
T15
PB15D
U16
PB16A
T
C
SLEEPN
V18
PB16B
N13
PB16C
R14
PB16D
VCCIO4
VCCIO4
GND
GNDIO4
4-29
Pinout Information

LCMXO2280
Ball Number
Ball Function
Bank
GND
GNDIO3
Dual Function
Differential
VCCIO3
VCCIO3
P15
PR20B
N14
PR20A
N15
PR19B
M13
PR19A
R15
PR18B
C*
T16
PR18A
T*
N16
PR17D
M14
PR17C
U17
PR17B
C*
VCC
VCC
U18
PR17A
T*
R17
PR16D
R16
PR16C
T
C*
P16
PR16B
VCCIO3
VCCIO3
GND
GNDIO3
P17
PR16A
T*
L13
PR15D
M15
PR15C
T17
PR15B
C*
T18
PR15A
T*
L14
PR14D
L15
PR14C
R18
PR14B
C*
P18
PR14A
T*
GND
GND
K15
PR13D
K13
PR13C
N17
PR13B
C*
N18
PR13A
T*
K16
PR12D
K14
PR12C
M16
PR12B
C*
L16
PR12A
T*
GND
GNDIO3
VCCIO3
VCCIO3
J16
PR11D
J14
PR11C
M17
PR11B
C*
L17
PR11A
T*
J15
PR10D
4-30
Pinout Information

LCMXO2280
Ball Number
Ball Function
Bank
J13
PR10C
Dual Function
Differential
T
M18
PR10B
C*
L18
PR10A
T*
GND
GNDIO2
VCCIO2
VCCIO2
H16
PR9D
H14
PR9C
K18
PR9B
C*
J18
PR9A
T*
C
J17
PR8D
VCC
VCC
H18
PR8C
H17
PR8B
C*
G17
PR8A
T*
H13
PR7D
H15
PR7C
G18
PR7B
C*
F18
PR7A
T*
G14
PR6D
G16
PR6C
VCCIO2
VCCIO2
GND
GNDIO2
E18
PR6B
C*
F17
PR6A
T*
G13
PR5D
G15
PR5C
E17
PR5B
C*
T*
E16
PR5A
GND
GND
F15
PR4D
E15
PR4C
D17
PR4B
C*
D18
PR4A
T*
B18
PR3D
C18
PR3C
C16
PR3B
C*
D16
PR3A
T*
C17
PR2B
C
T
D15
PR2A
VCCIO2
VCCIO2
GND
GNDIO2
GND
GNDIO1
VCCIO1
VCCIO1
4-31
Pinout Information

LCMXO2280
Ball Number
Ball Function
Bank
E13
PT16D
Dual Function
Differential
C15
PT16C
F13
PT16B
D14
PT16A
A18
PT15D
B17
PT15C
A16
PT15B
A17
PT15A
VCC
VCC
D13
PT14D
F12
PT14C
C14
PT14B
E12
PT14A
C13
PT13D
B16
PT13C
B15
PT13B
A15
PT13A
VCCIO1
VCCIO1
GND
GNDIO1
B14
PT12F
A14
PT12E
D12
PT12D
F11
PT12C
B13
PT12B
A13
PT12A
C12
PT11D
GND
GND
B12
PT11C
E11
PT11B
D11
PT11A
C11
PT10F
A12
PT10E
VCCIO1
VCCIO1
GND
GNDIO1
F10
PT10D
D10
PT10C
B11
PT10B
A11
PT10A
PCLK1_1***
C
T
C
E10
PT9D
C10
PT9C
D9
PT9B
E9
PT9A
B10
PT8F
4-32
T
PCLK1_0***
Pinout Information

LCMXO2280
Ball Number
Ball Function
Bank
A10
PT8E
VCCIO0
VCCIO0
GND
GNDIO0
Dual Function
Differential
T
A9
PT8D
C9
PT8C
B9
PT8B
F9
VCCAUX
A8
PT8A
B8
PT7D
C
T
C8
PT7C
VCC
VCC
A7
PT7B
B7
PT7A
A6
PT6A
B6
PT6B
D8
PT6C
F8
PT6D
C7
PT6E
E8
PT6F
D7
PT5D
VCCIO0
VCCIO0
GND
GNDIO0
E7
PT5C
A5
PT5B
C6
PT5A
B5
PT4A
A4
PT4B
D6
PT4C
F7
PT4D
B4
PT4E
GND
GND
C5
PT4F
F6
PT3D
E5
PT3C
E6
PT3B
D5
PT3A
A3
PT2D
C4
PT2C
A2
PT2B
B2
PT2A
VCCIO0
VCCIO0
GND
GNDIO0
E14
GND
4-33
Pinout Information

LCMXO2280
Ball Number
Ball Function
Bank
F16
GND
H10
GND
H11
GND
H8
GND
H9
GND
J10
GND
J11
GND
J4
GND
J8
GND
J9
GND
K10
GND
K11
GND
K17
GND
K8
GND
K9
GND
L10
GND
L11
GND
L8
GND
L9
GND
N2
GND
P14
GND
P5
GND
R7
GND
F14
VCC
G11
VCC
G9
VCC
H7
VCC
L7
VCC
M9
VCC
H6
VCCIO7
J7
VCCIO7
M7
VCCIO6
K7
VCCIO6
M8
VCCIO5
R9
VCCIO5
M12
VCCIO4
M11
VCCIO4
L12
VCCIO3
K12
VCCIO3
J12
VCCIO2
H12
VCCIO2
G12
VCCIO1
G10
VCCIO1
4-34
Dual Function
Differential
Pinout Information

LCMXO2280
Ball Number
Ball Function
Bank
G8
VCCIO0
G7
VCCIO0
* Supports true LVDS outputs.

** NC for E devices.
*** Primary clock inputs are single-ended.
4-35
Dual Function
Differential
Pinout Information
Thermal Management
Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal
characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets.
Designers must complete a thermal analysis of their specific design to ensure that the device and package do not
exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package
specific thermal values.
For Further Information

For further information regarding Thermal Management, refer to the following:
Thermal Management document
TN1090 - Power Estimation and Management for MachXO Devices
Power Calculator tool included with the Lattice ispLEVER design tool, or as a standalone download from
www.latticesemi.com/software
4-36

Ordering Information
June 2013
Data Sheet DS1002
Part Number Description

LCMXO XXXX X X XXXXXX X XX
ES = Engineering Sample
Blank = Production Device
Device Family
MachXO PLD
Grade
C = Commercial
I = Industrial
Logic Capacity
256 LUTs = 256
640 LUTs = 640
1200 LUTs = 1200
2280 LUTs = 2280
Package
T100 = 100-pin TQFP
T144 = 144-pin TQFP
M100 = 100-ball csBGA
M132 = 132-ball csBGA
B256 = 256-ball caBGA
FT256 = 256-ball ftBGA
FT324 = 324-ball ftBGA
SupplyVoltage
C = 1.8V/2.5V/3.3V
E = 1.2V
Note: Parts dual marked as described.
TN100 = 100-pin Lead-Free TQFP

TN144 = 144-pin Lead-Free TQFP
MN100 = 100-ball Lead-Free csBGA
MN132 = 132-ball Lead-Free csBGA
BN256 = 256-ball Lead-Free caBGA
FTN256 = 256-ball Lead-Free ftBGA
FTN324 = 324-ball Lead-Free ftBGA
Speed
3 = Slowest
4
5 = Fastest
Note: MachXO devices are dual marked except the slowest commercial speed grade device.For example the
commercial speed grade LCMXO640E-4F256C is also marked with industrial grade -3I grade.The slowest commercial speed grade does not have industrial markings. The markings appears as follows:
LCMXO640E
4F256C-3I
Datecode
Dual Mark
www.latticesemi.com
5-1
DS1002 Ordering Information_01.8
Conventional Packaging
Commercial
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO256C-3T100C
256
1.8V/2.5V/3.3V
78
-3
TQFP
100
COM
LCMXO256C-4T100C
256
1.8V/2.5V/3.3V
78
-4
TQFP
100
COM
LCMXO256C-5T100C
256
1.8V/2.5V/3.3V
78
-5
TQFP
100
COM
LCMXO256C-3M100C
256
1.8V/2.5V/3.3V
78
-3
csBGA
100
COM
LCMXO256C-4M100C
256
1.8V/2.5V/3.3V
78
-4
csBGA
100
COM
LCMXO256C-5M100C
256
1.8V/2.5V/3.3V
78
-5
csBGA
100
COM
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO640C-3T100C
Part Number
640
1.8V/2.5V/3.3V
74
-3
TQFP
100
COM
LCMXO640C-4T100C
640
1.8V/2.5V/3.3V
74
-4
TQFP
100
COM
LCMXO640C-5T100C
640
1.8V/2.5V/3.3V
74
-5
TQFP
100
COM
LCMXO640C-3M100C
640
1.8V/2.5V/3.3V
74
-3
csBGA
100
COM
LCMXO640C-4M100C
640
1.8V/2.5V/3.3V
74
-4
csBGA
100
COM
LCMXO640C-5M100C
640
1.8V/2.5V/3.3V
74
-5
csBGA
100
COM
LCMXO640C-3T144C
640
1.8V/2.5V/3.3V
113
-3
TQFP
144
COM
LCMXO640C-4T144C
640
1.8V/2.5V/3.3V
113
-4
TQFP
144
COM
LCMXO640C-5T144C
640
1.8V/2.5V/3.3V
113
-5
TQFP
144
COM
LCMXO640C-3M132C
640
1.8V/2.5V/3.3V
101
-3
csBGA
132
COM
LCMXO640C-4M132C
640
1.8V/2.5V/3.3V
101
-4
csBGA
132
COM
LCMXO640C-5M132C
640
1.8V/2.5V/3.3V
101
-5
csBGA
132
COM
LCMXO640C-3B256C
640
1.8V/2.5V/3.3V
159
-3
caBGA
256
COM
LCMXO640C-4B256C
640
1.8V/2.5V/3.3V
159
-4
caBGA
256
COM
LCMXO640C-5B256C
640
1.8V/2.5V/3.3V
159
-5
caBGA
256
COM
LCMXO640C-3FT256C
640
1.8V/2.5V/3.3V
159
-3
ftBGA
256
COM
LCMXO640C-4FT256C
640
1.8V/2.5V/3.3V
159
-4
ftBGA
256
COM
LCMXO640C-5FT256C
640
1.8V/2.5V/3.3V
159
-5
ftBGA
256
COM
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO1200C-3T100C
1200
1.8V/2.5V/3.3V
73
-3
TQFP
100
COM
LCMXO1200C-4T100C
1200
1.8V/2.5V/3.3V
73
-4
TQFP
100
COM
LCMXO1200C-5T100C
1200
1.8V/2.5V/3.3V
73
-5
TQFP
100
COM
LCMXO1200C-3T144C
1200
1.8V/2.5V/3.3V
113
-3
TQFP
144
COM
LCMXO1200C-4T144C
1200
1.8V/2.5V/3.3V
113
-4
TQFP
144
COM
LCMXO1200C-5T144C
1200
1.8V/2.5V/3.3V
113
-5
TQFP
144
COM
LCMXO1200C-3M132C
1200
1.8V/2.5V/3.3V
101
-3
csBGA
132
COM
LCMXO1200C-4M132C
1200
1.8V/2.5V/3.3V
101
-4
csBGA
132
COM
LCMXO1200C-5M132C
1200
1.8V/2.5V/3.3V
101
-5
csBGA
132
COM
LCMXO1200C-3B256C
1200
1.8V/2.5V/3.3V
211
-3
caBGA
256
COM
LCMXO1200C-4B256C
1200
1.8V/2.5V/3.3V
211
-4
caBGA
256
COM
LCMXO1200C-5B256C
1200
1.8V/2.5V/3.3V
211
-5
caBGA
256
COM
LCMXO1200C-3FT256C
1200
1.8V/2.5V/3.3V
211
-3
ftBGA
256
COM
LCMXO1200C-4FT256C
1200
1.8V/2.5V/3.3V
211
-4
ftBGA
256
COM
LCMXO1200C-5FT256C
1200
1.8V/2.5V/3.3V
211
-5
ftBGA
256
COM
Part Number
5-2
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO2280C-3T100C
2280
1.8V/2.5V/3.3V
73
-3
TQFP
100
COM
LCMXO2280C-4T100C
2280
1.8V/2.5V/3.3V
73
-4
TQFP
100
COM
LCMXO2280C-5T100C
2280
1.8V/2.5V/3.3V
73
-5
TQFP
100
COM
LCMXO2280C-3T144C
2280
1.8V/2.5V/3.3V
113
-3
TQFP
144
COM
LCMXO2280C-4T144C
2280
1.8V/2.5V/3.3V
113
-4
TQFP
144
COM
LCMXO2280C-5T144C
2280
1.8V/2.5V/3.3V
113
-5
TQFP
144
COM
LCMXO2280C-3M132C
2280
1.8V/2.5V/3.3V
101
-3
csBGA
132
COM
LCMXO2280C-4M132C
2280
1.8V/2.5V/3.3V
101
-4
csBGA
132
COM
LCMXO2280C-5M132C
2280
1.8V/2.5V/3.3V
101
-5
csBGA
132
COM
LCMXO2280C-3B256C
2280
1.8V/2.5V/3.3V
211
-3
caBGA
256
COM
LCMXO2280C-4B256C
2280
1.8V/2.5V/3.3V
211
-4
caBGA
256
COM
LCMXO2280C-5B256C
2280
1.8V/2.5V/3.3V
211
-5
caBGA
256
COM
LCMXO2280C-3FT256C
2280
1.8V/2.5V/3.3V
211
-3
ftBGA
256
COM
LCMXO2280C-4FT256C
2280
1.8V/2.5V/3.3V
211
-4
ftBGA
256
COM
LCMXO2280C-5FT256C
2280
1.8V/2.5V/3.3V
211
-5
ftBGA
256
COM
LCMXO2280C-3FT324C
2280
1.8V/2.5V/3.3V
271
-3
ftBGA
324
COM
LCMXO2280C-4FT324C
2280
1.8V/2.5V/3.3V
271
-4
ftBGA
324
COM
LCMXO2280C-5FT324C
2280
1.8V/2.5V/3.3V
271
-5
ftBGA
324
COM
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO256E-3T100C
256
1.2V
78
-3
TQFP
100
COM
LCMXO256E-4T100C
256
1.2V
78
-4
TQFP
100
COM
LCMXO256E-5T100C
256
1.2V
78
-5
TQFP
100
COM
LCMXO256E-3M100C
256
1.2V
78
-3
csBGA
100
COM
LCMXO256E-4M100C
256
1.2V
78
-4
csBGA
100
COM
LCMXO256E-5M100C
256
1.2V
78
-5
csBGA
100
COM
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO640E-3T100C
Part Number
640
1.2V
74
-3
TQFP
100
COM
LCMXO640E-4T100C
640
1.2V
74
-4
TQFP
100
COM
LCMXO640E-5T100C
640
1.2V
74
-5
TQFP
100
COM
LCMXO640E-3M100C
640
1.2V
74
-3
csBGA
100
COM
LCMXO640E-4M100C
640
1.2V
74
-4
csBGA
100
COM
LCMXO640E-5M100C
640
1.2V
74
-5
csBGA
100
COM
LCMXO640E-3T144C
640
1.2V
113
-3
TQFP
144
COM
LCMXO640E-4T144C
640
1.2V
113
-4
TQFP
144
COM
LCMXO640E-5T144C
640
1.2V
113
-5
TQFP
144
COM
LCMXO640E-3M132C
640
1.2V
101
-3
csBGA
132
COM
LCMXO640E-4M132C
640
1.2V
101
-4
csBGA
132
COM
LCMXO640E-5M132C
640
1.2V
101
-5
csBGA
132
COM
LCMXO640E-3B256C
640
1.2V
159
-3
caBGA
256
COM
LCMXO640E-4B256C
640
1.2V
159
-4
caBGA
256
COM
LCMXO640E-5B256C
640
1.2V
159
-5
caBGA
256
COM
LCMXO640E-3FT256C
640
1.2V
159
-3
ftBGA
256
COM
LCMXO640E-4FT256C
640
1.2V
159
-4
ftBGA
256
COM
LCMXO640E-5FT256C
640
1.2V
159
-5
ftBGA
256
COM
5-3
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO1200E-3T100C
1200
1.2V
73
-3
TQFP
100
COM
LCMXO1200E-4T100C
1200
1.2V
73
-4
TQFP
100
COM
LCMXO1200E-5T100C
1200
1.2V
73
-5
TQFP
100
COM
LCMXO1200E-3T144C
1200
1.2V
113
-3
TQFP
144
COM
LCMXO1200E-4T144C
1200
1.2V
113
-4
TQFP
144
COM
LCMXO1200E-5T144C
1200
1.2V
113
-5
TQFP
144
COM
LCMXO1200E-3M132C
1200
1.2V
101
-3
csBGA
132
COM
LCMXO1200E-4M132C
1200
1.2V
101
-4
csBGA
132
COM
LCMXO1200E-5M132C
1200
1.2V
101
-5
csBGA
132
COM
LCMXO1200E-3B256C
1200
1.2V
211
-3
caBGA
256
COM
LCMXO1200E-4B256C
1200
1.2V
211
-4
caBGA
256
COM
LCMXO1200E-5B256C
1200
1.2V
211
-5
caBGA
256
COM
LCMXO1200E-3FT256C
1200
1.2V
211
-3
ftBGA
256
COM
LCMXO1200E-4FT256C
1200
1.2V
211
-4
ftBGA
256
COM
LCMXO1200E-5FT256C
1200
1.2V
211
-5
ftBGA
256
COM
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO2280E-3T100C
2280
1.2V
73
-3
TQFP
100
COM
LCMXO2280E-4T100C
2280
1.2V
73
-4
TQFP
100
COM
LCMXO2280E-5T100C
2280
1.2V
73
-5
TQFP
100
COM
LCMXO2280E-3T144C
2280
1.2V
113
-3
TQFP
144
COM
LCMXO2280E-4T144C
2280
1.2V
113
-4
TQFP
144
COM
LCMXO2280E-5T144C
2280
1.2V
113
-5
TQFP
144
COM
LCMXO2280E-3M132C
2280
1.2V
101
-3
csBGA
132
COM
LCMXO2280E-4M132C
2280
1.2V
101
-4
csBGA
132
COM
LCMXO2280E-5M132C
2280
1.2V
101
-5
csBGA
132
COM
LCMXO2280E-3B256C
2280
1.2V
211
-3
caBGA
256
COM
LCMXO2280E-4B256C
2280
1.2V
211
-4
caBGA
256
COM
LCMXO2280E-5B256C
2280
1.2V
211
-5
caBGA
256
COM
LCMXO2280E-3FT256C
2280
1.2V
211
-3
ftBGA
256
COM
LCMXO2280E-4FT256C
2280
1.2V
211
-4
ftBGA
256
COM
LCMXO2280E-5FT256C
2280
1.2V
211
-5
ftBGA
256
COM
LCMXO2280E-3FT324C
2280
1.2V
271
-3
ftBGA
324
COM
LCMXO2280E-4FT324C
2280
1.2V
271
-4
ftBGA
324
COM
LCMXO2280E-5FT324C
2280
1.2V
271
-5
ftBGA
324
COM
Part Number
5-4
Conventional Packaging
Industrial
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO256C-3T100I
256
1.8V/2.5V/3.3V
78
-3
TQFP
100
IND
LCMXO256C-4T100I
256
1.8V/2.5V/3.3V
78
-4
TQFP
100
IND
LCMXO256C-3M100I
256
1.8V/2.5V/3.3V
78
-3
csBGA
100
IND
LCMXO256C-4M100I
256
1.8V/2.5V/3.3V
78
-4
csBGA
100
IND
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
640
1.8V/2.5V/3.3V
74
-3
TQFP
100
IND
Part Number
LCMXO640C-3T100I
LCMXO640C-4T100I
640
1.8V/2.5V/3.3V
74
-4
TQFP
100
IND
LCMXO640C-3M100I
640
1.8V/2.5V/3.3V
74
-3
csBGA
100
IND
LCMXO640C-4M100I
640
1.8V/2.5V/3.3V
74
-4
csBGA
100
IND
LCMXO640C-3T144I
640
1.8V/2.5V/3.3V
113
-3
TQFP
144
IND
LCMXO640C-4T144I
640
1.8V/2.5V/3.3V
113
-4
TQFP
144
IND
LCMXO640C-3M132I
640
1.8V/2.5V/3.3V
101
-3
csBGA
132
IND
LCMXO640C-4M132I
640
1.8V/2.5V/3.3V
101
-4
csBGA
132
IND
LCMXO640C-3B256I
640
1.8V/2.5V/3.3V
159
-3
caBGA
256
IND
LCMXO640C-4B256I
640
1.8V/2.5V/3.3V
159
-4
caBGA
256
IND
LCMXO640C-3FT256I
640
1.8V/2.5V/3.3V
159
-3
ftBGA
256
IND
LCMXO640C-4FT256I
640
1.8V/2.5V/3.3V
159
-4
ftBGA
256
IND
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO1200C-3T100I
1200
1.8V/2.5V/3.3V
73
-3
TQFP
100
IND
LCMXO1200C-4T100I
1200
1.8V/2.5V/3.3V
73
-4
TQFP
100
IND
LCMXO1200C-3T144I
1200
1.8V/2.5V/3.3V
113
-3
TQFP
144
IND
LCMXO1200C-4T144I
1200
1.8V/2.5V/3.3V
113
-4
TQFP
144
IND
LCMXO1200C-3M132I
1200
1.8V/2.5V/3.3V
101
-3
csBGA
132
IND
LCMXO1200C-4M132I
1200
1.8V/2.5V/3.3V
101
-4
csBGA
132
IND
LCMXO1200C-3B256I
1200
1.8V/2.5V/3.3V
211
-3
caBGA
256
IND
LCMXO1200C-4B256I
1200
1.8V/2.5V/3.3V
211
-4
caBGA
256
IND
LCMXO1200C-3FT256I
1200
1.8V/2.5V/3.3V
211
-3
ftBGA
256
IND
LCMXO1200C-4FT256I
1200
1.8V/2.5V/3.3V
211
-4
ftBGA
256
IND
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
2280
1.8V/2.5V/3.3V
73
-3
TQFP
100
IND
Part Number
Part Number
LCMXO2280C-3T100I
LCMXO2280C-4T100I
2280
1.8V/2.5V/3.3V
73
-4
TQFP
100
IND
LCMXO2280C-3T144I
2280
1.8V/2.5V/3.3V
113
-3
TQFP
144
IND
LCMXO2280C-4T144I
2280
1.8V/2.5V/3.3V
113
-4
TQFP
144
IND
LCMXO2280C-3M132I
2280
1.8V/2.5V/3.3V
101
-3
csBGA
132
IND
LCMXO2280C-4M132I
2280
1.8V/2.5V/3.3V
101
-4
csBGA
132
IND
LCMXO2280C-3B256I
2280
1.8V/2.5V/3.3V
211
-3
caBGA
256
IND
LCMXO2280C-4B256I
2280
1.8V/2.5V/3.3V
211
-4
caBGA
256
IND
LCMXO2280C-3FT256I
2280
1.8V/2.5V/3.3V
211
-3
ftBGA
256
IND
LCMXO2280C-4FT256I
2280
1.8V/2.5V/3.3V
211
-4
ftBGA
256
IND
LCMXO2280C-3FT324I
2280
1.8V/2.5V/3.3V
271
-3
ftBGA
324
IND
LCMXO2280C-4FT324I
2280
1.8V/2.5V/3.3V
271
-4
ftBGA
324
IND
5-5
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO256E-3T100I
Part Number
256
1.2V
78
-3
TQFP
100
IND
LCMXO256E-4T100I
256
1.2V
78
-4
TQFP
100
IND
LCMXO256E-3M100I
256
1.2V
78
-3
csBGA
100
IND
LCMXO256E-4M100I
256
1.2V
78
-4
csBGA
100
IND
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO640E-3T100I
640
1.2V
74
-3
TQFP
100
IND
LCMXO640E-4T100I
640
1.2V
74
-4
TQFP
100
IND
LCMXO640E-3M100I
640
1.2V
74
-3
csBGA
100
IND
LCMXO640E-4M100I
640
1.2V
74
-4
csBGA
100
IND
LCMXO640E-3T144I
640
1.2V
113
-3
TQFP
144
IND
LCMXO640E-4T144I
640
1.2V
113
-4
TQFP
144
IND
LCMXO640E-3M132I
640
1.2V
101
-3
csBGA
132
IND
LCMXO640E-4M132I
640
1.2V
101
-4
csBGA
132
IND
LCMXO640E-3B256I
640
1.2V
159
-3
caBGA
256
IND
LCMXO640E-4B256I
640
1.2V
159
-4
caBGA
256
IND
LCMXO640E-3FT256I
640
1.2V
159
-3
ftBGA
256
IND
LCMXO640E-4FT256I
640
1.2V
159
-4
ftBGA
256
IND
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO1200E-3T100I
Part Number
1200
1.2V
73
-3
TQFP
100
IND
LCMXO1200E-4T100I
1200
1.2V
73
-4
TQFP
100
IND
LCMXO1200E-3T144I
1200
1.2V
113
-3
TQFP
144
IND
LCMXO1200E-4T144I
1200
1.2V
113
-4
TQFP
144
IND
LCMXO1200E-3M132I
1200
1.2V
101
-3
csBGA
132
IND
LCMXO1200E-4M132I
1200
1.2V
101
-4
csBGA
132
IND
LCMXO1200E-3B256I
1200
1.2V
211
-3
caBGA
256
IND
LCMXO1200E-4B256I
1200
1.2V
211
-4
caBGA
256
IND
LCMXO1200E-3FT256I
1200
1.2V
211
-3
ftBGA
256
IND
LCMXO1200E-4FT256I
1200
1.2V
211
-4
ftBGA
256
IND
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO2280E-3T100I
2280
1.2V
73
-3
TQFP
100
IND
LCMXO2280E-4T100I
2280
1.2V
73
-4
TQFP
100
IND
LCMXO2280E-3T144I
2280
1.2V
113
-3
TQFP
144
IND
LCMXO2280E-4T144I
2280
1.2V
113
-4
TQFP
144
IND
LCMXO2280E-3M132I
2280
1.2V
101
-3
csBGA
132
IND
LCMXO2280E-4M132I
2280
1.2V
101
-4
csBGA
132
IND
LCMXO2280E-3B256I
2280
1.2V
211
-3
caBGA
256
IND
LCMXO2280E-4B256I
2280
1.2V
211
-4
caBGA
256
IND
LCMXO2280E-3FT256I
2280
1.2V
211
-3
ftBGA
256
IND
LCMXO2280E-4FT256I
2280
1.2V
211
-4
ftBGA
256
IND
LCMXO2280E-3FT324I
2280
1.2V
271
-3
ftBGA
324
IND
LCMXO2280E-4FT324I
2280
1.2V
271
-4
ftBGA
324
IND
Part Number
5-6
Lead-Free Packaging
Commercial
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO256C-3TN100C
256
1.8V/2.5V/3.3V
78
-3
Lead-Free TQFP
100
COM
LCMXO256C-4TN100C
256
1.8V/2.5V/3.3V
78
-4
Lead-Free TQFP
100
COM
LCMXO256C-5TN100C
256
1.8V/2.5V/3.3V
78
-5
Lead-Free TQFP
100
COM
LCMXO256C-3MN100C
256
1.8V/2.5V/3.3V
78
-3
Lead-Free csBGA
100
COM
LCMXO256C-4MN100C
256
1.8V/2.5V/3.3V
78
-4
Lead-Free csBGA
100
COM
LCMXO256C-5MN100C
256
1.8V/2.5V/3.3V
78
-5
Lead-Free csBGA
100
COM
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO640C-3TN100C
Part Number
640
1.8V/2.5V/3.3V
74
-3
Lead-Free TQFP
100
COM
LCMXO640C-4TN100C
640
1.8V/2.5V/3.3V
74
-4
Lead-Free TQFP
100
COM
LCMXO640C-5TN100C
640
1.8V/2.5V/3.3V
74
-5
Lead-Free TQFP
100
COM
LCMXO640C-3MN100C
640
1.8V/2.5V/3.3V
74
-3
Lead-Free csBGA
100
COM
LCMXO640C-4MN100C
640
1.8V/2.5V/3.3V
74
-4
Lead-Free csBGA
100
COM
LCMXO640C-5MN100C
640
1.8V/2.5V/3.3V
74
-5
Lead-Free csBGA
100
COM
LCMXO640C-3TN144C
640
1.8V/2.5V/3.3V
113
-3
Lead-Free TQFP
144
COM
LCMXO640C-4TN144C
640
1.8V/2.5V/3.3V
113
-4
Lead-Free TQFP
144
COM
LCMXO640C-5TN144C
640
1.8V/2.5V/3.3V
113
-5
Lead-Free TQFP
144
COM
LCMXO640C-3MN132C
640
1.8V/2.5V/3.3V
101
-3
Lead-Free csBGA
132
COM
LCMXO640C-4MN132C
640
1.8V/2.5V/3.3V
101
-4
Lead-Free csBGA
132
COM
LCMXO640C-5MN132C
640
1.8V/2.5V/3.3V
101
-5
Lead-Free csBGA
132
COM
LCMXO640C-3BN256C
640
1.8V/2.5V/3.3V
159
-3
Lead-Free caBGA
256
COM
LCMXO640C-4BN256C
640
1.8V/2.5V/3.3V
159
-4
Lead-Free caBGA
256
COM
LCMXO640C-5BN256C
640
1.8V/2.5V/3.3V
159
-5
Lead-Free caBGA
256
COM
LCMXO640C-3FTN256C
640
1.8V/2.5V/3.3V
159
-3
Lead-Free ftBGA
256
COM
LCMXO640C-4FTN256C
640
1.8V/2.5V/3.3V
159
-4
Lead-Free ftBGA
256
COM
LCMXO640C-5FTN256C
640
1.8V/2.5V/3.3V
159
-5
Lead-Free ftBGA
256
COM
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO1200C-3TN100C
1200
1.8V/2.5V/3.3V
73
-3
Lead-Free TQFP
100
COM
LCMXO1200C-4TN100C
1200
1.8V/2.5V/3.3V
73
-4
Lead-Free TQFP
100
COM
LCMXO1200C-5TN100C
1200
1.8V/2.5V/3.3V
73
-5
Lead-Free TQFP
100
COM
LCMXO1200C-3TN144C
1200
1.8V/2.5V/3.3V
113
-3
Lead-Free TQFP
144
COM
LCMXO1200C-4TN144C
1200
1.8V/2.5V/3.3V
113
-4
Lead-Free TQFP
144
COM
LCMXO1200C-5TN144C
1200
1.8V/2.5V/3.3V
113
-5
Lead-Free TQFP
144
COM
LCMXO1200C-3MN132C
1200
1.8V/2.5V/3.3V
101
-3
Lead-Free csBGA
132
COM
LCMXO1200C-4MN132C
1200
1.8V/2.5V/3.3V
101
-4
Lead-Free csBGA
132
COM
LCMXO1200C-5MN132C
1200
1.8V/2.5V/3.3V
101
-5
Lead-Free csBGA
132
COM
LCMXO1200C-3BN256C
1200
1.8V/2.5V/3.3V
211
-3
Lead-Free caBGA
256
COM
LCMXO1200C-4BN256C
1200
1.8V/2.5V/3.3V
211
-4
Lead-Free caBGA
256
COM
LCMXO1200C-5BN256C
1200
1.8V/2.5V/3.3V
211
-5
Lead-Free caBGA
256
COM
LCMXO1200C-3FTN256C
1200
1.8V/2.5V/3.3V
211
-3
Lead-Free ftBGA
256
COM
LCMXO1200C-4FTN256C
1200
1.8V/2.5V/3.3V
211
-4
Lead-Free ftBGA
256
COM
LCMXO1200C-5FTN256C
1200
1.8V/2.5V/3.3V
211
-5
Lead-Free ftBGA
256
COM
Part Number
5-7
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO2280C-3TN100C
Part Number
2280
1.8V/2.5V/3.3V
73
-3
Lead-Free TQFP
100
COM
LCMXO2280C-4TN100C
2280
1.8V/2.5V/3.3V
73
-4
Lead-Free TQFP
100
COM
LCMXO2280C-5TN100C
2280
1.8V/2.5V/3.3V
73
-5
Lead-Free TQFP
100
COM
LCMXO2280C-3TN144C
2280
1.8V/2.5V/3.3V
113
-3
Lead-Free TQFP
144
COM
LCMXO2280C-4TN144C
2280
1.8V/2.5V/3.3V
113
-4
Lead-Free TQFP
144
COM
LCMXO2280C-5TN144C
2280
1.8V/2.5V/3.3V
113
-5
Lead-Free TQFP
144
COM
LCMXO2280C-3MN132C
2280
1.8V/2.5V/3.3V
101
-3
Lead-Free csBGA
132
COM
LCMXO2280C-4MN132C
2280
1.8V/2.5V/3.3V
101
-4
Lead-Free csBGA
132
COM
LCMXO2280C-5MN132C
2280
1.8V/2.5V/3.3V
101
-5
Lead-Free csBGA
132
COM
LCMXO2280C-3BN256C
2280
1.8V/2.5V/3.3V
211
-3
Lead-Free caBGA
256
COM
LCMXO2280C-4BN256C
2280
1.8V/2.5V/3.3V
211
-4
Lead-Free caBGA
256
COM
LCMXO2280C-5BN256C
2280
1.8V/2.5V/3.3V
211
-5
Lead-Free caBGA
256
COM
LCMXO2280C-3FTN256C
2280
1.8V/2.5V/3.3V
211
-3
Lead-Free ftBGA
256
COM
LCMXO2280C-4FTN256C
2280
1.8V/2.5V/3.3V
211
-4
Lead-Free ftBGA
256
COM
LCMXO2280C-5FTN256C
2280
1.8V/2.5V/3.3V
211
-5
Lead-Free ftBGA
256
COM
LCMXO2280C-3FTN324C
2280
1.8V/2.5V/3.3V
271
-3
Lead-Free ftBGA
324
COM
LCMXO2280C-4FTN324C
2280
1.8V/2.5V/3.3V
271
-4
Lead-Free ftBGA
324
COM
LCMXO2280C-5FTN324C
2280
1.8V/2.5V/3.3V
271
-5
Lead-Free ftBGA
324
COM
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO256E-3TN100C
256
1.2V
78
-3
Lead-Free TQFP
100
COM
LCMXO256E-4TN100C
256
1.2V
78
-4
Lead-Free TQFP
100
COM
LCMXO256E-5TN100C
256
1.2V
78
-5
Lead-Free TQFP
100
COM
LCMXO256E-3MN100C
256
1.2V
78
-3
Lead-Free csBGA
100
COM
LCMXO256E-4MN100C
256
1.2V
78
-4
Lead-Free csBGA
100
COM
LCMXO256E-5MN100C
256
1.2V
78
-5
Lead-Free csBGA
100
COM
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO640E-3TN100C
Part Number
640
1.2V
74
-3
Lead-Free TQFP
100
COM
LCMXO640E-4TN100C
640
1.2V
74
-4
Lead-Free TQFP
100
COM
LCMXO640E-5TN100C
640
1.2V
74
-5
Lead-Free TQFP
100
COM
LCMXO640E-3MN100C
640
1.2V
74
-3
Lead-Free csBGA
100
COM
LCMXO640E-4MN100C
640
1.2V
74
-4
Lead-Free csBGA
100
COM
LCMXO640E-5MN100C
640
1.2V
74
-5
Lead-Free csBGA
100
COM
LCMXO640E-3TN144C
640
1.2V
113
-3
Lead-Free TQFP
144
COM
LCMXO640E-4TN144C
640
1.2V
113
-4
Lead-Free TQFP
144
COM
LCMXO640E-5TN144C
640
1.2V
113
-5
Lead-Free TQFP
144
COM
LCMXO640E-3MN132C
640
1.2V
101
-3
Lead-Free csBGA
132
COM
LCMXO640E-4MN132C
640
1.2V
101
-4
Lead-Free csBGA
132
COM
LCMXO640E-5MN132C
640
1.2V
101
-5
Lead-Free csBGA
132
COM
LCMXO640E-3BN256C
640
1.2V
159
-3
Lead-Free caBGA
256
COM
LCMXO640E-4BN256C
640
1.2V
159
-4
Lead-Free caBGA
256
COM
LCMXO640E-5BN256C
640
1.2V
159
-5
Lead-Free caBGA
256
COM
LCMXO640E-3FTN256C
640
1.2V
159
-3
Lead-Free ftBGA
256
COM
LCMXO640E-4FTN256C
640
1.2V
159
-4
Lead-Free ftBGA
256
COM
LCMXO640E-5FTN256C
640
1.2V
159
-5
Lead-Free ftBGA
256
COM
5-8
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO1200E-3TN100C
Part Number
1200
1.2V
73
-3
Lead-Free TQFP
100
COM
LCMXO1200E-4TN100C
1200
1.2V
73
-4
Lead-Free TQFP
100
COM
LCMXO1200E-5TN100C
1200
1.2V
73
-5
Lead-Free TQFP
100
COM
LCMXO1200E-3TN144C
1200
1.2V
113
-3
Lead-Free TQFP
144
COM
LCMXO1200E-4TN144C
1200
1.2V
113
-4
Lead-Free TQFP
144
COM
LCMXO1200E-5TN144C
1200
1.2V
113
-5
Lead-Free TQFP
144
COM
LCMXO1200E-3MN132C
1200
1.2V
101
-3
Lead-Free csBGA
132
COM
LCMXO1200E-4MN132C
1200
1.2V
101
-4
Lead-Free csBGA
132
COM
LCMXO1200E-5MN132C
1200
1.2V
101
-5
Lead-Free csBGA
132
COM
LCMXO1200E-3BN256C
1200
1.2V
211
-3
Lead-Free caBGA
256
COM
LCMXO1200E-4BN256C
1200
1.2V
211
-4
Lead-Free caBGA
256
COM
LCMXO1200E-5BN256C
1200
1.2V
211
-5
Lead-Free caBGA
256
COM
LCMXO1200E-3FTN256C
1200
1.2V
211
-3
Lead-Free ftBGA
256
COM
LCMXO1200E-4FTN256C
1200
1.2V
211
-4
Lead-Free ftBGA
256
COM
LCMXO1200E-5FTN256C
1200
1.2V
211
-5
Lead-Free ftBGA
256
COM
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO2280E-3TN100C
2280
1.2V
73
-3
Lead-Free TQFP
100
COM
LCMXO2280E-4TN100C
2280
1.2V
73
-4
Lead-Free TQFP
100
COM
LCMXO2280E-5TN100C
2280
1.2V
73
-5
Lead-Free TQFP
100
COM
LCMXO2280E-3TN144C
2280
1.2V
113
-3
Lead-Free TQFP
144
COM
LCMXO2280E-4TN144C
2280
1.2V
113
-4
Lead-Free TQFP
144
COM
LCMXO2280E-5TN144C
2280
1.2V
113
-5
Lead-Free TQFP
144
COM
LCMXO2280E-3MN132C
2280
1.2V
101
-3
Lead-Free csBGA
132
COM
LCMXO2280E-4MN132C
2280
1.2V
101
-4
Lead-Free csBGA
132
COM
LCMXO2280E-5MN132C
2280
1.2V
101
-5
Lead-Free csBGA
132
COM
LCMXO2280E-3BN256C
2280
1.2V
211
-3
Lead-Free caBGA
256
COM
LCMXO2280E-4BN256C
2280
1.2V
211
-4
Lead-Free caBGA
256
COM
LCMXO2280E-5BN256C
2280
1.2V
211
-5
Lead-Free caBGA
256
COM
LCMXO2280E-3FTN256C
2280
1.2V
211
-3
Lead-Free ftBGA
256
COM
LCMXO2280E-4FTN256C
2280
1.2V
211
-4
Lead-Free ftBGA
256
COM
LCMXO2280E-5FTN256C
2280
1.2V
211
-5
Lead-Free ftBGA
256
COM
LCMXO2280E-3FTN324C
2280
1.2V
271
-3
Lead-Free ftBGA
324
COM
LCMXO2280E-4FTN324C
2280
1.2V
271
-4
Lead-Free ftBGA
324
COM
LCMXO2280E-5FTN324C
2280
1.2V
271
-5
Lead-Free ftBGA
324
COM
5-9
Lead-Free Packaging
Industrial
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO256C-3TN100I
256
1.8V/2.5V/3.3V
78
-3
Lead-Free TQFP
100
IND
LCMXO256C-4TN100I
256
1.8V/2.5V/3.3V
78
-4
Lead-Free TQFP
100
IND
LCMXO256C-3MN100I
256
1.8V/2.5V/3.3V
78
-3
Lead-Free csBGA
100
IND
LCMXO256C-4MN100I
256
1.8V/2.5V/3.3V
78
-4
Lead-Free csBGA
100
IND
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
640
1.8V/2.5V/3.3V
74
-3
Lead-Free TQFP
100
IND
Part Number
LCMXO640C-3TN100I
LCMXO640C-4TN100I
640
1.8V/2.5V/3.3V
74
-4
Lead-Free TQFP
100
IND
LCMXO640C-3MN100I
640
1.8V/2.5V/3.3V
74
-3
Lead-Free csBGA
100
IND
LCMXO640C-4MN100I
640
1.8V/2.5V/3.3V
74
-4
Lead-Free csBGA
100
IND
LCMXO640C-3TN144I
640
1.8V/2.5V/3.3V
113
-3
Lead-Free TQFP
144
IND
LCMXO640C-4TN144I
640
1.8V/2.5V/3.3V
113
-4
Lead-Free TQFP
144
IND
LCMXO640C-3MN132I
640
1.8V/2.5V/3.3V
101
-3
Lead-Free csBGA
132
IND
LCMXO640C-4MN132I
640
1.8V/2.5V/3.3V
101
-4
Lead-Free csBGA
132
IND
LCMXO640C-3BN256I
640
1.8V/2.5V/3.3V
159
-3
Lead-Free caBGA
256
IND
LCMXO640C-4BN256I
640
1.8V/2.5V/3.3V
159
-4
Lead-Free caBGA
256
IND
LCMXO640C-3FTN256I
640
1.8V/2.5V/3.3V
159
-3
Lead-Free ftBGA
256
IND
LCMXO640C-4FTN256I
640
1.8V/2.5V/3.3V
159
-4
Lead-Free ftBGA
256
IND
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO1200C-3TN100I
1200
1.8V/2.5V/3.3V
73
-3
Lead-Free TQFP
100
IND
LCMXO1200C-4TN100I
1200
1.8V/2.5V/3.3V
73
-4
Lead-Free TQFP
100
IND
LCMXO1200C-3TN144I
1200
1.8V/2.5V/3.3V
113
-3
Lead-Free TQFP
144
IND
LCMXO1200C-4TN144I
1200
1.8V/2.5V/3.3V
113
-4
Lead-Free TQFP
144
IND
LCMXO1200C-3MN132I
1200
1.8V/2.5V/3.3V
101
-3
Lead-Free csBGA
132
IND
LCMXO1200C-4MN132I
1200
1.8V/2.5V/3.3V
101
-4
Lead-Free csBGA
132
IND
LCMXO1200C-3BN256I
1200
1.8V/2.5V/3.3V
211
-3
Lead-Free caBGA
256
IND
LCMXO1200C-4BN256I
1200
1.8V/2.5V/3.3V
211
-4
Lead-Free caBGA
256
IND
LCMXO1200C-3FTN256I
1200
1.8V/2.5V/3.3V
211
-3
Lead-Free ftBGA
256
IND
LCMXO1200C-4FTN256I
1200
1.8V/2.5V/3.3V
211
-4
Lead-Free ftBGA
256
IND
Part Number
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO2280C-3TN100I
Part Number
2280
1.8V/2.5V/3.3V
73
-3
Lead-Free TQFP
100
IND
LCMXO2280C-4TN100I
2280
1.8V/2.5V/3.3V
73
-4
Lead-Free TQFP
100
IND
LCMXO2280C-3TN144I
2280
1.8V/2.5V/3.3V
113
-3
Lead-Free TQFP
144
IND
LCMXO2280C-4TN144I
2280
1.8V/2.5V/3.3V
113
-4
Lead-Free TQFP
144
IND
LCMXO2280C-3MN132I
2280
1.8V/2.5V/3.3V
101
-3
Lead-Free csBGA
132
IND
LCMXO2280C-4MN132I
2280
1.8V/2.5V/3.3V
101
-4
Lead-Free csBGA
132
IND
LCMXO2280C-3BN256I
2280
1.8V/2.5V/3.3V
211
-3
Lead-Free caBGA
256
IND
LCMXO2280C-4BN256I
2280
1.8V/2.5V/3.3V
211
-4
Lead-Free caBGA
256
IND
LCMXO2280C-3FTN256I
2280
1.8V/2.5V/3.3V
211
-3
Lead-Free ftBGA
256
IND
LCMXO2280C-4FTN256I
2280
1.8V/2.5V/3.3V
211
-4
Lead-Free ftBGA
256
IND
LCMXO2280C-3FTN324I
2280
1.8V/2.5V/3.3V
271
-3
Lead-Free ftBGA
324
IND
LCMXO2280C-4FTN324I
2280
1.8V/2.5V/3.3V
271
-4
Lead-Free ftBGA
324
IND
5-10
LUTs
Supply Voltage
I/Os
Grade
LCMXO256E-3TN100I
Part Number
256
1.2V
78
-3
Lead-Free TQFP
LCMXO256E-4TN100I
256
1.2V
78
-4
Lead-Free TQFP
100
IND
LCMXO256E-3MN100I
256
1.2V
78
-3
Lead-Free csBGA
100
IND
LCMXO256E-4MN100I
256
1.2V
78
-4
Lead-Free csBGA
100
IND
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO640E-3TN100I
640
1.2V
74
-3
Lead-Free TQFP
100
IND
LCMXO640E-4TN100I
640
1.2V
74
-4
Lead-Free TQFP
100
IND
LCMXO640E-3MN100I
640
1.2V
74
-3
Lead-Free csBGA
100
IND
LCMXO640E-4MN100I
640
1.2V
74
-4
Lead-Free csBGA
100
IND
LCMXO640E-3TN144I
640
1.2V
113
-3
Lead-Free TQFP
144
IND
LCMXO640E-4TN144I
640
1.2V
113
-4
Lead-Free TQFP
144
IND
LCMXO640E-3MN132I
640
1.2V
101
-3
Lead-Free csBGA
132
IND
LCMXO640E-4MN132I
640
1.2V
101
-4
Lead-Free csBGA
132
IND
LCMXO640E-3BN256I
640
1.2V
159
-3
Lead-Free caBGA
256
IND
LCMXO640E-4BN256I
640
1.2V
159
-4
Lead-Free caBGA
256
IND
LCMXO640E-3FTN256I
640
1.2V
159
-3
Lead-Free ftBGA
256
IND
LCMXO640E-4FTN256I
640
1.2V
159
-4
Lead-Free ftBGA
256
IND
Package
Part Number
Part Number
Package
Pins
Temp.
100
IND
LUTs
Supply Voltage
I/Os
Grade
Pins
Temp.
LCMXO1200E-3TN100I
1200
1.2V
73
-3
Lead-Free TQFP
100
IND
LCMXO1200E-4TN100I
1200
1.2V
73
-4
Lead-Free TQFP
100
IND
LCMXO1200E-3TN144I
1200
1.2V
113
-3
Lead-Free TQFP
144
IND
LCMXO1200E-4TN144I
1200
1.2V
113
-4
Lead-Free TQFP
144
IND
LCMXO1200E-3MN132I
1200
1.2V
101
-3
Lead-Free csBGA
132
IND
LCMXO1200E-4MN132I
1200
1.2V
101
-4
Lead-Free csBGA
132
IND
LCMXO1200E-3BN256I
1200
1.2V
211
-3
Lead-Free caBGA
256
IND
LCMXO1200E-4BN256I
1200
1.2V
211
-4
Lead-Free caBGA
256
IND
LCMXO1200E-3FTN256I
1200
1.2V
211
-3
Lead-Free ftBGA
256
IND
LCMXO1200E-4FTN256I
1200
1.2V
211
-4
Lead-Free ftBGA
256
IND
LUTs
Supply Voltage
I/Os
Grade
Package
Pins
Temp.
LCMXO2280E-3TN100I
2280
1.2V
73
-3
Lead-Free TQFP
100
IND
LCMXO2280E-4TN100I
2280
1.2V
73
-4
Lead-Free TQFP
100
IND
LCMXO2280E-3TN144I
2280
1.2V
113
-3
Lead-Free TQFP
144
IND
LCMXO2280E-4TN144I
2280
1.2V
113
-4
Lead-Free TQFP
144
IND
LCMXO2280E-3MN132I
2280
1.2V
101
-3
Lead-Free csBGA
132
IND
LCMXO2280E-4MN132I
2280
1.2V
101
-4
Lead-Free csBGA
132
IND
LCMXO2280E-3BN256I
2280
1.2V
211
-3
Lead-Free caBGA
256
IND
LCMXO2280E-4BN256I
2280
1.2V
211
-4
Lead-Free caBGA
256
IND
LCMXO2280E-3FTN256I
2280
1.2V
211
-3
Lead-Free ftBGA
256
IND
LCMXO2280E-4FTN256I
2280
1.2V
211
-4
Lead-Free ftBGA
256
IND
LCMXO2280E-3FTN324I
2280
1.2V
271
-3
Lead-Free ftBGA
324
IND
LCMXO2280E-4FTN324I
2280
1.2V
271
-4
Lead-Free ftBGA
324
IND
Part Number
5-11

Supplemental Information
June 2013
Data Sheet DS1002
For Further Information

A variety of technical notes for the MachXO family are available on the Lattice web site.
TN1091, MachXO sysIO Usage Guide
TN1089, MachXO sysCLOCK Design and Usage Guide
TN1092, Memory Usage Guide for MachXO Devices
TN1090, Power Estimation and Management for MachXO Devices
TN1086, MachXO JTAG Programming and Configuration Users Guide
TN1087, Minimizing System Interruption During Configuration Using TransFR Technology
TN1097, MachXO Density Migration
AN8066, Boundary Scan Testability with Lattice sysIO Capability
For further information on interface standards refer to the following web sites:
JEDEC Standards (LVTTL, LVCMOS): www.jedec.org
PCI: www.pcisig.com
www.latticesemi.com
6-1
DS1002 Further Information_01.3

Revision History
June 2013
Data Sheet DS1002
Revision History
Date
Version
Section
February 2005
01.0
Change Summary
October 2005
01.1
Introduction
Distributed RAM information in family table updated. Added footnote 1 fpBGA packaging to the family selection guide.
Architecture
sysIO Buffer section updated.
Initial release.
Hot Socketing section updated.

Sleep Mode section updated.
SLEEP Pin Characteristics section updated.
Oscillator section updated.
Security section updated.
DC and Switching
Characteristics
Recommended Operating Conditions table updated.

DC Electrical Characteristics table updated.
Supply Current (Sleep Mode) table added with LCMXO256/640 data.
Supply Current (Standby) table updated with LCMXO256/640 data.
Initialization Supply Current table updated with LCMXO256/640 data.
Programming and Erase Flash Supply Current table updated with
LCMXO256/640 data.
Register-to-Register Performance table updated (rev. A 0.16).
External Switching Characteristics table updated (rev. A 0.16).
Internal Timing Parameter table updated (rev. A 0.16).
Family Timing Adders updated (rev. A 0.16).
sysCLOCK Timingupdated (rev. A 0.16).
MachXO "C" Sleep Mode Timing updated (A 0.16).
JTAG Port Timing Specification updated (rev. A 0.16).
Pinout Information
SLEEPIN description updated.

Pin Information Summary updated.
Power Supply and NC Connection table has been updated.
Logic Signal Connection section has been updated to include all
devices/packages.
Part Number Description section has been updated.

Ordering Part Number section has been updated (added LCMXO256C/
LCMXO640C "4W").
Supplemental
Information
MachXO Density Migration Technical Note (TN1097) added.
November 2005
01.2
Pinout Information
Added Power Supply and NC Connections summary information for

LCMXO1200 and LCMXO2280 in 100 TQFP package.
December 2005
01.3
DC and Switching
Characteristics
Supply Current (Standby) table updated with LCMXO1200/2280 data.
Ordering Part Number section updated (added LCMXO2280C "4W").
April 2006
02.0
Introduction
Introduction paragraphs updated.
Architecture
Architecture Overview paragraphs updated.
www.latticesemi.com
7-1
Revision History
Date
Version
Section
April 2006
(cont.)
02.0
(cont.)
Architecture
(cont.)
Change Summary
Top View of the MachXO1200 Device figure updated.
Slice Diagram figure updated.
Slice Signal Descriptions table updated.
Routing section updated.
sysCLOCK Phase Lockecd Loops (PLLs) section updated.
PLL Diagram updated.
PLL Signal Descriptions table updated.
sysMEM Memory section has been updated.
PIO Groups section has been updated.
PIO section has been updated.
MachXO PIO Block Diagram updated.
Supported Input Standards table updated.
MachXO Configuration and Programming diagram updated.
DC and Switching
Characteristics
Recommended Operating Conditions table - footnotes updated.

MachXO256 and MachXO640 Hot Socketing Specifications - footnotes
updated.
Added MachXO1200 and MachXO2280 Hot Socketing Specifications
table.
DC Electrical Characteristics, footnotes have been updated.
Supply Current (Sleep Mode) table has been updated, removed "4W"
references. Footnotes have been updated.
Supply Current (Standby) table and associated footnotes updated.
Intialization Supply Current table and footnotes updated.
Programming and Erase Flash Supply Current table and associated
footnotes have been updatd.
Register-to-Register Performance table updated (rev. A 0.19).
MachXO External Switching Characteristics updated (rev. A 0.19).
MachXO Internal Timing Parameters updated (rev. A 0.19).
MachXO Family Timing Adders updated (rev. A 0.19).
sysCLOCK Timing updated (rev. A 0.19).
MachXO "C" Sleep Mode Timing updated (A 0.19).
JTAG Port Timing Specification updated (rev. A 0.19).
Test Fixture Required Components table updated.
Pinout Information
Signal Descriptions have been updated.

Pin Information Summary has been updated. Footnote has been
added.
Power Supply and NC Connection table has been updated.
Logic Signal Connections have been updated (PCLKTx_x --> PCLKx_x)
Removed "4W" references.

Added 256-ftBGA Ordering Part Numbers for MachXO640.
May 2006
02.1
Pinout Information
Removed [LOC][0]_PLL_RST from Signal Description table.

PCLK footnote has been added to all appropriate pins.
August 2006
02.2
Multiple
Removed 256 fpBGA information for MachXO640.
7-2
Revision History
Date
Version
Section
November 2006
02.3
DC and Switching
Characteristics
Change Summary
December 2006
02.4
Architecture
February 2007
02.5
Architecture
August 2007
02.6
DC and Switching
Characteristics
Updated sysIO Single-Ended DC Electrical Characteristics table.
November 2007
02.7
DC and Switching
Characteristics
Added JTAG Port Timing Waveforms diagram.
Pinout Information
Added Thermal Management text section.
Corrections to MachXO C Sleep Mode Timing table - value for

tWSLEEPN (400ns) changed from max. to min. Value for tWAWAKE
(100ns) changed from min. to max.
Added Flash Download Time table.
Pinout Information
Supplemental
Information
June 2009
02.8
Introduction
Pinout Information
July 2010
02.9
June 2013
03.0
DC and Switching
Characteristics
All
Architecture
DC and Switching
Characteristics
EBR Asynchronous Reset section added.

Power Supply and NC table: Pin/Ball orientation footnotes added.
Updated EBR Asynchronous Reset section.
Updated title list.

Added 0.8-mm 256-pin caBGA package to MachXO Family Selection
Guide table.
Added Logic Signal Connections table for 0.8-mm 256-pin caBGA package.
Updated Part Number Description diagram and Ordering Part Number
tables with 0.8-mm 256-pin caBGA package information.
Updated sysCLOCK PLL Timing table.
Updated document with new corporate logo.
Architecture Overview Added information on the state of the
register on power up and after configuration.
MachXO1200 and MachXO2280 Hot Socketing Specifications table
Removed footnote 4.
Added MachXO Programming/Erase Specifications table.
7-3

Family Data Sheet

Uploaded by

Document Informationclick to expand document informationFamily Data Sheet

Document Informationclick to expand document information

Copyright:

Available Formats

Family Data Sheet

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Family Data Sheet

Uploaded by

Copyright:

Available Formats

MachXO Family Data Sheet

DS1002 Version 03.0, June 2013

MachXO Family Data Sheet

Data Sheet DS1002

Flexible I/O Buffer

Programmable sysIO buffer supports wide

Non-volatile, Infinitely Reconfigurable

System Level Support

TransFR Reconfiguration (TFR)

High I/O to Logic Density

256 to 2280 LUT4s

The MachXO is optimized to meet the requirements of

Embedded and Distributed Memory

Dist. RAM (Kbits)

EBR SRAM (Kbits)

132-ball csBGA (8x8 mm)

256-ball caBGA (14x14 mm)

256-ball ftBGA (17x17 mm)

324-ball ftBGA (19x19 mm)

MachXO Family Data Sheet

Data Sheet DS1002

Figure 2-2. Top View of the MachXO640 Device

From Adjacent Slice/PFU

Table 2-1. Slice Signal Descriptions

A0, B0, C0, D0 Inputs to LUT4

A1, B1, C1, D1 Inputs to LUT4

Fast Carry In1

LUT4 output register bypass signals

Output of a LUT5 MUX

Output of a LUT6, LUT7, LUT82 MUX depending on the Slice

Fast Carry Out1

1. See Figure 2-4 for connection details.

LUT 4x2 or LUT 5x1

2-bit Arithmetic Unit

LUT 4x2 or LUT 5x1

2-bit Arithmetic Unit

Note: SPR = Single Port RAM, DPR = Dual Port RAM

Clock/Control Distribution Network

Clock input from external pin or routing

1 to reset the input clock divider

PLL output clock to clock tree (phase shifted/duty cycle changed)

PLL output clock to clock tree (No phase shift)

PLL output to clock tree through secondary clock divider

1 indicates PLL LOCK to CLKI

Internal feedback source, CLKOP divider output before CLOCKTREE

Dynamic Delay Enable. 1: Pin control (dynamic), 0: Fuse Control (static)

Dynamic Delay Zero. 1: delay = 0, 0: delay = on

Dynamic Delay Lag/Lead. 1: Lag, 0: Lead

Dynamic Delay Input

True Dual Port

Pseudo Dual Port

True Dual Port RAM

Single Port RAM

Pseudo-Dual Port RAM

Almost Empty (AE)

N = Address bit width

Figure 2-16. Group ofSix Programmable I/O Cells

Note: Buffer 1 tracks with VCCAUX