PCM67P/U

PCM69AP/AU

Advanced 1-Bit BiCMOS Dual 18-Bit

DIGITAL-TO-ANALOG CONVERTER
FEATURES DESCRIPTION
18-BIT RESOLUTION DUAL AUDIO DAC The PCM67 and PCM69A dual 18-bit DAC are low
EXCELLENT THD PERFORMANCE: cost, dual output 18-bit BiCMOS digital-to-analog con-
0.0025% (92dB) at F/S, K Grade verters utilizing a novel architecture to achieve excel-
1.0% (40dB) at 60dB, K Grade lent low level performance.
HIGH S/N RATIO: 110dB typ (IHF-A) By combining a conventional thin-film R-2R ladder
DAC, a digital offset technique with analog correction
DUAL, CO-PHASE
and an advanced one-bit DAC using first order noise
SINGLE SUPPLY +5V OPERATION shaping technique, the PCM67 and PCM69A achieve
LOW POWER: 75mW typical high resolution, minimal glitch, and low zero-crossing
CAPABLE OF 16X OVERSAMPLING distortion.
AVAILABLE IN SPACE SAVING PCM67 digital offset occurs at bit 9, making it ideal for
16-PIN DIP OR 20-PIN SOIC high-performance CD players. PCM69A digital offset
OPERATING TEMP RANGE: occurs at bit 4, making it an excellent choice for digital
25C to +85C musical instruments and audio DSP.
EXTREMELY LOW GLITCH ENERGY Both PCM67 and PCM69A operate from a single +5V
supply. The low power consumption and small size (16-
pin PDIP or 20-pin SOIC) make these converters ideal
for a variety of digital audio applications.

10-Bit DAC plus

Analog Correction

Reference Analog Output Lch

Servo
Advanced 1-Bit
DAC VCOM
Buffer
Lch

VCOM
10-Bit DAC plus Buffer
Rch
Analog Correction

Input Analog Output Rch

Digital Signal In
Interface

Advanced 1-Bit
DAC

International Airport Industrial Park Mailing Address: PO Box 11400 Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132

1992 Burr-Brown Corporation PDS-1168A Printed in U.S.A. August, 1993

SPECIFICATIONS
ELECTRICAL
All specifications at +25C and +VA, +VD = +5V unless otherwise noted

PCM67/69A

PARAMETER CONDITIONS MIN TYP MAX UNITS

RESOLUTION 18 Bits

DYNAMIC RANGE, THD+N at 60dB Referred to Full Scale 106 dB

DIGITAL INPUT
Logic Family TTL/CMOS Compatible
Logic Level: VIH IIH = 5A +2 +VD V
VIL IIL = 5A 0 0.8 V
Data Format Serial, MSB First, BTC(1)
Input System Clock Frequency 16.9344 MHz

TOTAL HARMONIC DISTORTION + N(2,3,4)

PCM67P/69AP, PCM67U/69AU
f = 991Hz (0dB) fS = 352.8kHz 86 82 dB
f = 991Hz (20dB) fS = 352.8kHz 68 dB
f = 991Hz (60dB) fS = 352.8kHz 40 34 dB
PCM67P-J/69AP-J, PCM67U-J/69AU-J
f = 991Hz (0dB) fS = 352.8kHz 91 88 dB
f = 991Hz (20dB) fS = 352.8kHz 72 dB
f = 991Hz (60dB) fS = 352.8kHz 46 40 dB
PCM67P-K/69AP-K, PCM67U-K/69AU-K
f = 991Hz (0dB) fS = 352.8kHz 95 92 dB
f = 991Hz (20dB) fS = 352.8kHz 74 dB
f = 991Hz (60dB) fS = 352.8kHz 46 40 dB

CHANNEL SEPARATION (f = 1kHz) 106 dB

ACCURACY
Level Linearity at 90dB Signal Level 1 dB
Gain Error 3 10 %
Gain Mismatch, Channel-to-Channel 1 5 %
Gain Drift 0C to +70C 95 ppm/C
Warm-up Time 1 Minute

IDLE CHANNEL SNR(5) 20Hz to 40kHz at BPZ(6) 110 dB

ANALOG OUTPUT
Output Range (3%) 1.2 mA
Output Impedance (30%) 1.8 k
VCOM 3.35 3.50 3.65 V
Glitch Energy No Glitch Around Zero

POWER SUPPLY REQUIREMENTS, System Clock = 16.9344MHz

+VA, +VD Supply Voltage Range +VA = +VD +4.75 +5.00 +5.25 V
+IA, +ID Combined Supply Current +VA, +VD = +5V 15 20 mA
Power Dissipation +VA, +VD = +5V 75 105 mW

TEMPERATURE RANGE
Operating 25 +85 C
Storage 55 +100 C

NOTES: (1) Binary Twos Complement coding. (2) Ratio of (DistortionRMS + NoiseRMS)/SignalRMS. (3) D/A converter output frequency/signal level (both left and right
channels are on). (4) D/A converter sample frequency (8 x 44.1kHz; 8X oversampling per channel). (5) Ratio of NoiseRMS/SignalRMS. Measured using a 40kHz
3rd-order GIC (Generalized Immittance Converter) filter and an A-weighted filter. (6) Bipolar Zero.

USA OEM PRICES

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

PCM67/69A 2
PIN ASSIGNMENTS ABSOLUTE MAXIMUM RATINGS
PCM67P PCM67U +VA, +VD to ACOM, DCOM ................................................... 0V to +6.5V
PCM69AP PCM69AU DESCRIPTION MNEMONIC ACOM to DCOM ............................................................................... 0.5V
Digital Inputs to DCOM ............................................ 0.3V to +VD + 0.3V
1 1 +5V Analog Supply Voltage +VA Power Dissipation ................ 300mW (U Package), 500mW (P Package)
2 2 Left Voltage Common LVCOM Lead Temperature, (soldering, 10s) .............................................. +260C
3 No Connection NC Max Junction Temperature ............................................................ +165C
3 4 Left Current Output (0 to 1.2mA) LIOUT
4 5 Servo Decoupling Capacitor SRVCAP NOTE: Stresses above those listed under Absolute Maximum Ratings
5 6 Reference Decoupling Capacitor REFCAP may cause permanent damage to the device. Exposure to absolute
6 7 Right Current Output (0 to 1.2mA) RIOUT maximum conditions for extended periods may affect device reliability.
8 No Connection NC
7 9 Right Voltage Common RVCOM
8 10 Analog Common ACOM
9 11 Digital Common DCOM

10
12
13
Mode Control 2
Right Data Input
MC2
RDATA
ELECTROSTATIC
11
12
14
15
Bit Clock
System Clock
BTCK
SYSCK
DISCHARGE SENSITIVITY
13 16 Word Clock WDCK Electrostatic discharge can cause damage ranging from per-
14 17 Left Data Input LDATA formance degradation to complete device failure. Burr-Brown
18 Mode Control 3 MC3
15 19 Mode Control 1 MC1 Corporation recommends that all integrated circuits be handled
16 20 +5V Digital Supply Voltage +VD and stored using appropriate ESD protection methods.

PACKAGE INFORMATION
PACKAGE DRAWING
MODEL PACKAGE NUMBER(1)
PCM67P/69AP 16-Pin Plastic DIP 180
PCM67U/69AU 20-Pin SOIC 248
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.

3 PCM67/69A
PIN CONFIGURATION PCM67P/69AP (16-Pin DIP)

Data-L
WDCK
SYS CLOCK
BCK
Data-R
1F

16 15 14 13 12 11 10 9

PCM67P/69AP

1 2 3 4 5 6 7 8
+VCC
(+5V) 10F
3.3F 3.3F

RNF RNF

10F Lch 10F Rch

OUT OUT

PIN CONFIGURATION PCM67U/69AU (20-Pin SOIC)

Data-L
WDCK
SYS CLOCK
BCK
Data-R
1F

20 19 18 17 16 15 14 13 12 11

PCM67U/69AU

1 2 3 4 5 6 7 8 9 10
+VCC
(+5V) 10F
3.3F 3.3F

RNF RNF

10F Lch 10F Rch

OUT OUT

PCM67/69A 4
TYPICAL PERFORMANCE CURVES
All specifications at +25C and VCC = +5.0V unless otherwise noted.

THD vs POWER SUPPLY VOLTAGE GAIN ERROR / VCOM vs POWER SUPPLY

0.01% 1.0% 3 3.70

60dB 2

0.005% 0.5% 1 3.60

Gain Error (%)

THD (60dB)
Gain Error

VCOM (V)
THD (F/S)

F/S
0

1 3.50
0.002% 0.2%
VCOM
2

0.001% 0.1% 3 3.40

4.75 5.0 5.25 4.75 5.0 5.25
VCC (V)
VCC (V)

THD vs TEMPERATURE GAIN ERROR / VCOM vs TEMPERATURE

0.01% 1.0% 3 3.70
60dB
2

0.005% 0.5% 1 3.60

Gain Error (%)
THD (60dB)

VCOM (V)
THD (F/S)

F/S
0

1 3.50
0.002% 0.2%

0.001% 0.1% 3 3.40

25 0 25 50 75 85 100
25 0 25 50 85 100
Temperature (C) Temperature (%)

THD vs SYSTEM CLOCK FREQUENCY CHANNEL SEPARATION vs SIGNAL FREQUENCY

0.01% 1.0% 115

fs = 44.1kHz
60dB 110
0.005% 0.5%
Separation (dB)
THD (60dB)
THD (F/S)

105

F/S
0.002% 0.2%
100

0.001% 0.1% 95
384 192 96 48 100 500 1k 2k 4k 8k 16k 128k
fs (Hz) f (Hz)

5 PCM67/69A
DISCUSSION OF
SPECIFICATIONS VOUT = 1.2mA RNF

The PCM67 and PCM69A are specified to provide critical VOUT

performance criteria for a variety of applications. The accu-
racy of a D/A converter is described by the transfer function VCOM
shown in Figure 1. RNF

1.2mA
Digital In IOUT
+FSR VOUT
011...11
Gain Error VCOM
(3.5V)

FIGURE 2. I/V Amplifier Circuit.

000...00 S/N RATIO

Analog
111...11 Out
BPZ S/N ratio is defined as the ratio of full scale output and no input
BPZ 1LSB noise level at BPZ point. The PCM67/69A is specified at
110dB typical with IHF-A filter.
100...00
FSR
(V = 3.5V) LEVEL LINEARITY ERROR
COM
Level linearity error is defined as the deviation of actual
analog output level from digital input level. PCM67/69A is
FIGURE 1. Transfer Performance.
specified at 1dB typical at 90dB output level. The 0.5LSB
quantization error at 90dB of 16-bit conversion is equal to
DIGITAL INPUT CODE
+1.94dB, 2.5dB.
The PCM67/69A accepts Binary Twos Complement (BTC)
digital input code (MSB FIRST).The relationship of digital
TOTAL HARMONIC DISTORTION
input to analog output is shown in Table 1.
THD is a key parameter in audio applications, THD is a
measure of the magnitude and distribution of the linearity
ANALOG OUTPUT ANALOG OUTPUT error, differential linearity error, and noise, as well as quanti-
DIGITAL INPUT (VOLTAGE) (CURRENT)
zation error. To be useful, THD should be specified for both
7FFFFF (HEX) +FSR 1.2mA
high level and low level input signals. This error is unadjustable
00003F (HEX) BPZ 0.6mA
FFFFFF (HEX) BPZ 1LSB 0.59995mA and is the most meaningful indicator of D/A converter accu-
80003F (HEX) FSR 0mA racy for audio applications.
THD is defined as the ratio of the square root of the sum of the
TABLE I. Digital Code and Analog Out.
squares of the values of the harmonics to the value of the
fundamental input frequency and is expressed in percent or
GAIN ERROR AND GAIN MISMATCH,
dB. The rms value of the PCM67/69A error referred to the
CHANNEL-TO-CHANNEL
input can be shown to be
Gain error is defined as deviation of the output current span
from the ideal span of 1.2mA (FSR) on each channel. Gain n 2
error of PCM67/69A is typically 3% of FSR. rms = 1
n E L (i ) + E Q (i ) (1)
Gain mismatch, channel-to-channel is defined as the differ- i=1
ence in gain error between the left channel and right channel.

where n is the number of samples in one cycle of any given

THE RELATIONSHIP OF VCOM AND I/V OUT
sine wave, EL(i) is the linearity error of the PCM67 or
The output current range of PCM67 and PCM69A is 0mA to PCM69A at each sampling point. THD can then be expressed
1.2mA as shown in Table 1. as
n
In the typical application, the non-inverting input of the
n EL (i ) + EQ (i )
2
1
external I/V op amp is connected to the VCOM pin of PCM67 rms i =1
and PCM69A. Accordingly, the output voltage level at FSR THD = = 100%
after I/V conversion is VCOM voltage (+3.5V) as shown in Er ms E rms (2)
Figure 2. where Erms is the rms signal-voltage level.

PCM67/69A 6
This expression indicates that, in general, there is a correlation The PCM67/69A accepts TTL compatible logic input levels.
between the THD and the square root of the sum of the squares The data format of the PCM67/69A is BTC with the most
of the linearity errors at each digital word of interest. How- significant bit (MSB) being first in the serial input bit stream.
ever, this expression does not mean that the worst-case linear-
ity error of the D/A is directly correlated to THD.
tSL tSH
For PCM67 and PCM69A the test period is set at an 8X
oversampling rate (352.8kHz = 44.1kHz 8), which is the SYS Clock
typical sample rate for CD player applications. tDH
The test signal frequency is 991Hz and the amplitude of the
signal level is F/S (0dB), and 60dB down from F/S. Data LSB
tDSU tDHO
All THD tests are performed without a deglitcher circuit and
without a 20kHz low pass filter. Bit Clock
tCH tCL tCW tWC
SYSTEM CLOCK REQUIREMENTS
WD Clock
The PCM67 and PCM69A need a system clock for the one-bit
noise shaping DAC operation.
tWH tWL
The PCM67 is capable of only a 384Fs corollary system clock
frequency such as 192Fs, 96Fs (24 times word rate or integer
multiple of 24). tSH: SYS Clock High Pulse Width : 15ns, min
tSL: SYS Clock Low Pulse Width : 15ns, min
The PCM69A is capable of any system clock up from 48Fs to tDW: Data Valid Time : 20ns, min
384Fs such as 384Fs, 256Fs, 100Fs with condition for timing tDSU: Data Setup Time : 10ns, min
as described in Timing of PCM69A in Figure 5. tDHO: Data Hold Time : 5ns, min
tCH: Bit Clock High Pulse Width : 15ns, min
The user can choose either model for their application. tCL: Bit Clock Low Pulse Width : 15ns, min
Table II shows the different SYSCLK options. tCW: WD Clock Fall Time From Bit Clock Rise : 10ns, min
tWC: Bit Clock Rise Time From WD Clock Fall : 15ns, min
tWH: WD Clock High Pulse Width : 1 SYS Clock Cycle, min
tWL: WD Clock Low Pulse Width : 1 SYS Clock Cycle, min
OTHER CAPABLE
MODEL BASIC SYSCLK SYSCLK
PCM67 384Fs 192Fs, 96Fs FIGURE 4. Timing Specification.
PCM69A Any Clock (with timing condition)
Examples: 384Fs, 300Fs, 256Fs, 200Fs, 90Fs TIMING OF PCM69A
PCM69A timing is similar to PCM67 except that PCM69A is
TABLE II. System Clock Requirements.
capable of operating from any system clock up to 384Fs. For
synchronized operation, PCM69A system clock and WDCK
LOGIC TIMING timing must be as shown in Figure 5.
The serial data bit transfers are triggered on positive bit clock
(BCK) edges. The serial-to-parallel data transfer to the DAC
occurs on the falling edge of Word Clock (WDCK). The
change in the output of the DAC coincides with the falling WDCK

edge of WDCK. tn1

SYSCLK
Refer to Figure 3 for graphical relationships of these signals.
tn2
The setup and hold timing relationships for these signals are
SYSCLK
shown in Figure 4.

tn1: WDCK Fall Delay From Rise of SYSCLK : min 10ns

R-ch Data MSB bit2 bit17 LSB MSB bit2 bit17 LSB tn2: SYSCLK Rise Delay From Fall of WDCK : min 20ns

L-ch Data MSB bit2 bit17 LSB MSB bit2 bit17 LSB
FIGURE 5. Timing of PCM69A for SYSCLK and WDCK.
Bit Clock

WD Clock

SYS Clock

1 WDCK

FIGURE 3. Timing Diagram.

7 PCM67/69A
INSTALLATION SHIFT OF I/V OUT VOLTAGE
If the user requires a bipolar voltage output centered around
POWER SUPPLIES
0V or one-half of VCC, the output can be shifted by adding an
Refer to Pin Configuration diagram for proper connection offset current on the inverting point of the I/V op amp as
of the PCM67/69A. The PCM67/69A requires only a +5V shown in Figure 6.
supply. Both analog and digital supplies should be tied to-
gether at a single point, as no real advantage is gained by using
separate supplies. It is more important that both these supplies
+VCC
be as clean as possible to reduce coupling of supply noise to (+5V)
the output. R1
820

FILTER CAPACITOR REQUIREMENTS RNF

5k
As shown in the Pin Configuration diagram, various sizes of + R2
10F ~ 100F C1
decoupling capacitors can be used with no special tolerances 330

required. All capacitors should be as close to the appropriate IOUT

pins of the PCM67/69A as possible to reduce noise pickup VOUT
from surrounding circuitry. VCOM

A power supply decoupling capacitor should be used near the +

10F ~ 100F C2
analog supply pin to maximize power supply rejection, as
shown in Figure 6, regardless of how good the supplies are. 0V 6V
Both commons should be connected to an analog ground
plane as close to the PCM67/69A as possible.
Note: R1 and C1 are noise de-coupling circuits from noise
The value of these capacitors is influenced by actual board on +VCC power supply line.
layout design and noise from power supplies and other digital
input lines. FIGURE 7. Useful Application Circuit for Shift of I/V Out
The best suitable value for the capacitors should be deter- Voltage.
mined by the users actual application board.
INTERFACE CONTROL FUNCTION
Both the PCM67 and PCM69A (SOIC package type) are
VO VCC
VCOM +
2
VO
2
VO capable of 16-bit L/R serial input and 20-bit L/R parallel input
or 0V as shown in Table 3.
VCOM VS
(+3.5V)
VSHT
MC1 MC2 MC3 DATA-R INPUT FORMAT
0 0 1 0 16-Bit L/R Serial(1) LR L R WDCK
+VCC 0 0 1 1 16-Bit L/R Serial(1) LR L R WDCK
RNF 0 1 1 0 18-Bit L/R Serial(1) LR L R WDCK
ROS IOS 0 1 1 1 18-Bit L/R Serial(1) LR L R WDCK
1 0 1 X 20-Bit L/R Parallel
1 0 0 X 20-Bit L/R Parallel [WDCK Invert]
IOUT 1 1 1 X 18-Bit L/R Parallel
VOUT 1 1 0 X 18-Bit L/R Parallel [WDCK Invert]
VCOM
(3.5V) NOTE: (1) Data input to Data-Lch (Pin 17) for L/R serial format.

TABLE III. Interface Control Function of SOIC.

In case of shift to 3V swing, 0V center
V 6V
RNF = OUT = = 5k
1.2mA 1.2mA PCM67P and PCM69AP (DIP package) have only 18-bit
FSR(VS) = 3V after offset addition, shift voltage L/R serial input function as shown in Table 4.
VSHT is given by
VSHT = VCOM + 3V = 3.5 + 3 = 6.5V
MC1 DATA-R INPUT FORMAT
Offset Current IOS is given by
VSHT 0 0 18-Bit L/R Serial L R L R WDCK
6.5V
IOS = = = 1.3mA 0 1 18-Bit L/R Serial L R L R WDCK
RNF 5k
1 X 18-Bit L/R Parallel
Offset Resistor ROS is given by
V VCOM
ROS = CC = 5 3.5V = 1.15k
TABLE IV. Interface Control Function of DIP.
IOS 1.3mA

FIGURE 6. Shift of I/V Out Voltage.

PCM67/69A 8
DIGITAL FILTER INTERFACE

16-Bit L/R Serial 1 18-Bit L/R Parallel

+VDD SM5840 PCM67U/69AU

PCM67U/69AU

11 DGND
11 DGND
12 MC2
12 MC2
CXD2551 DOR 13 Data R-ch
13 Data R-ch
BCK0 14 BCK
BCK0 14 BCK
XTi 15 SYSCLK
X0 or X1 15 SYSCLK
WDCK0 16 WDCK
LRCK0 16 WDCK
DOL 17 Data L-ch
Data L-ch 17 Data L-ch
18 MC3
18 MC3
4FS, 16-Bit Mode
19 MC1
19 MC1
20 +VDD
20 +VDD

18-Bit Mode VDD

FIGURE 8. Using Sony CXD2551. FIGURE 10. Using NPC SM5840.

16-Bit L/R Serial 2 20-Bit L/R Parallel

SM5807 PCM67U/69AU DF1700 PCM67U/69AU

11 DGND 11 DGND

12 MC2 12 MC2

13 Data R-ch DOR 13 Data R-ch

BCK0 14 BCK BCK0 14 BCK

XTi 15 SYSCLK XTi 15 SYSCLK

LRC0 16 WDCK WDCK0 16 WDCK

DOUT 17 Data L-ch DOL 17 Data L-ch

18 MC3 18 MC3

19 MC1 19 MC1

20 +VDD 20 +VDD

SOMD = H +VDD 20-Bit Mode +VDD

FIGURE 9. Using NPC SM5807. FIGURE 11. Using Burr-Brown DF1700.

9 PCM67/69A
THEORY OF OPERATION
Digital converters in audio systems have traditionally utilized weight of bit n is switched in to compensate. This offset comes
a laser-trimmed, current-source DAC architecture. Unfortu- from a one-bit DAC which has also been trimmed to 18-bit
nately, this type of technology suffers from the problems linearity. While this technique doesnt remove the major carry
inherent in switching widely varying current levels. Design error completely, the glitch is only present in higher ampli-
improvements have helped, but DACs of this type still exhibit tude signals where it is much less audible.
low-level nonlinearity due to errors at the major carry. As for the one-bit DAC, a number of problems with this
Recently, DACs employing a different architecture have been architecture are also reduced: the DAC is designed to operate
introduced. Most of these DACs utilize a one-bit DAC with from the system clock, thus eliminating the need for a separate
noise shaping techniques and very high oversampling rate clock; the lower quantizing level of the DAC make it less
to achieve the digital-to-analog conversion. Basically, the sensitive to clock jitter; and output filtering requirements are
trade-off is from very accurate but slow current sources to one reduced because out-of-band noise has smaller amplitude,
rapidly sampled current source whose average output in the is farther-out, and increases much more slowly due to the
audio frequency range is equal to the current desired. Noise first-order noise shaper. Still, it is important to keep in mind
shaping insures that the undesirable frequencies associated that the one-bit DAC imposes some design considerations.
with one-bit DAC output lie outside the audio range. Figure 2 shows the THD + N of the converter versus System
These Bitstream, MASH, or one-bit DACs overcome the Clock frequency. This is the clock used to operate the one-bit
low level linearity problems of conventional DACs, since DAC and noise shaper. Generally, the higher the oversampling
there can be no major carry error. However, this architecture the better. However, near full-scale, the converter is limited by
exhibits problems of its own: signal-to-noise performance is other constraints and higher clock frequencies (past 96fs) tend
usually worse than a similar conventional DAC, dither to slightly worsen its performance. At low levels, perfor-
noise may be needed in order to get rid of unwanted tones, a mance improves almost linearly with increasing clock fre-
separate high-speed clock may be required, the part may show quency. The one-bit DAC was designed to operate between
sensitivity to clock jitter, and a high-order low-pass filter is 96fs (4X oversampling) and 384fs (16X oversampling). But,
necessary to filter the DAC output. it can be operated at 48fs (2X oversampling) with slightly
reduced performance.
The PCM67/69A is a cross between these two architectures.
It includes both a conventional laser-trimmed, current-source
DAC and an advanced one-bit DAC. The conventional DAC TOTAL HARMONIC DISTORTION + NOISE
is a 10-bit DAC where each bit weight has been trimmed to 18- A key specification for audio DACs is usually total harmonic
bit linearity. The one-bit DAC has a weight equal to bit 10 and distortion plus noise (THD + N). For the PCM67/69A, THD
employs a first-order noise shaper to generate the bitstream. + N is tested in production as shown in Figure 12. Digital data
words are read into the PCM67/69A at eight times the stan-
This approach does not eliminate all the problems associated
dard compact disk audio sampling frequency of 44.1kHz
with the two architectures but rather minimizes them as much
(352.8kHz) so that a sine wave output of 991Hz is realized.
as possible. The conventional DAC still exhibits some major
The output of the DAC goes to an I-to-V converter, then to a
carry error which would normally reduce low-level linearity.
programmable gain amplifier to provide gain at lower signal
However, to reduce this error even further, the PCM67/69A
output test levels, and then through a 40kHz low pass filter
utilizes an offset technique whereby bit n is subtracted from
before being fed into an analog type distortion analyzer.
the digital input code whenever it is positive (see Figure 1 and
Table I). When this is done, an offset current equal to the

PCM67/69A 10
 Use 400Hz High-Pass Low-Pass
Programmable
Filter and 30kHz Distortion Filter
Gain Amp
Low-Pass Filter Analyzer 40kHz 3rd-Order
0dB to 60dB
Meter Settings GIC Type
(Shiba Soku Model
725 or Equivalent)

I-to-V
Binary Digital Code Parallel-to-Serial DUT
Converter
Counter (EPROM) Conversion (PCM67/69A)
OPA627

System Clock
Bit Clock
Word Clock

Sampling Rate = 44.1kHz x 8 (352.8kHz)

Timing Output Frequency = 991Hz
Logic

FIGURE 12. PCM67/69A THD+N Production Test.

C10

1000pF
R5

2k
+5V
R7
200
11 10
A2 OUT R-ch
12 9 2.5V 1.2V
+C + C12
13 8 6
C8
100F + C9 2200pF
10F
14 7 R4
PCM67 C5
Digital 680
+

15 or 6 1000pF
In 10F
PCM69A R6
+

16 5 R3
10F
C4 680
17 4 2k
R8
18 3 200
A1 OUT L-ch
19 2 2.5V 1.2V
+ C3 C7
20 1 R2 + + C11
100F 10F
680 2200pF

R1 A1, A2; NJM2100 or LM833

+ C1 680
0.1F VCC
(+5V)
+C
2
100F

FIGURE 13. Single +5V Power Supply, with LPF, I/V Amp Application Circuit for Portable Digital Audio.

11 PCM67/69A
 +5V

4.7F +5V +5V

4.7F
+ 10F 1F

+ 17.1k
4.7F 4.7F
+5V
1 7 +
3 17 22 1 15 16 NOTE: Only left channel shown.
0.1F
Digital Interface 8X Interpolation 18-Bit D/A
Format Receiver Digital Filter Converter
Interleaved DOR 23 10 RDATA
Digital 28

PCM67/69A
Input BCO 26 11 BTCK
A 8 6
12 SYSCK LVCOM 2 6
6 BCO 12 2 2.7k
WCK 25 13 WDCK A1
5 L/R 15 28 LIOUT 3 5
DOL 24 14 LDATA
16.9344MHz DA 17 1
(192FS ) 220pF
3.3F Burr-Brown 10F
1M Yamaha Burr-Brown 4
PCM67P/69AP
YM3623 DF1700P
(Note: 16-Pin DIP) 5k
5
10pF 10pF
3 4 14 14 4 8 10 16 21 8 9
100pF 3.3F
150

12
4700pF

+15V
4.7F

+
510 3.3F 8
3
1
A2 VOUT
2200pF 2200pF 100k 2
Left
DGND AGND 4
+15V

FIGURE 14. HiFi D/A Converter Unit Application with Digital Audio Interface Format.
4.7F 4.7F
+
+
8 15V
3
1.5k 1
A3
2
6
4
7 4.7F
A4 +
5
1.5k
15V

1.5k 2200pF A1 to A4 = Burr-Brown OPA2604AP

or NE5532 equivalent.