1 Structural VHDL

Structural VHDL
Dr DC Hendry
March 19, 2006
1 Structural VHDL
The designs we have used so far have consisted of a single design entity (except-
ing in the laboratory where a testbench has also been used). Real designs will
contain a number, often a large number, of design entities representing various
components of the design. These components may be at a high level of abstrac-
tion (a USB interface or a microprocessor), or at a lower level (an adder or a
multiplier). These designs must then be connected together to create the com-
plete design. The design work at this stage consists of connecting the various
inputs and outputs between designs. This style of design, where the structure
of the overall design is being represented is sometimes referred to as structural
design.
VHDL contains a number of features supporting structural design. The most

obvious of these is the component declaration and the component instantiation
statement. Where large numbers of components must be instantiated in a re-
peated manner, or components must be conditionally instantiated, the generate
statement may be used. Finally, additional libraries and packages may make
components available in a design.
1.1 Components and Component Instantiation
The component declaration (wherever it appears) has the syntax:
component <component_name> [is]

[<generic_list>]
[<port_list>]
end component [<component_name>];
1.1 Components and Component Instantiation Structural VHDL
The optional <component name> may only appear in VHDL-93.
Here is an example of a component declaration taken from one of the laboratory

examples testbenches:
component example1
port (
a, b, c : in std_logic;
z, y : out std_logic);
end component;
At a practical level, Xemacs is normally used to copy an entity header and than
paste that header as a component declaration. Similarly Xemacs can be used
to paste an entity header as a component instantiation so saving much typing
and possibility of error.
Component instantation statements are then used to insert one or more such
components into the design. Each component instantiation statement is consid-
ered to be a single concurrent statement, and is therefore placed between the
begin and end of the architecture body.
The syntax of a component instantation statement is:
<instantiation_label> : <instantiated_unit>
[<generic_map>]
[<port_map>] ;
for example:
DUT: example1
port map (
a => a,
b => b,
c => c,
z => z,
y => y);
where:
<instantiation label> is a name constructed by the designer referring to this

instantiation of the component, e.g. DUT, U1, U2.
Revision : 1.1 Page 2 of 7 Dr DC Hendry

Structural VHDL
<instantiated unit> This is normally the name of the design representing this
components, e.g. example1 or detector. Other forms are available.
<generic map> Supplies values for any generic parameters required.
<port map> Specifies the connections of input and output signals.
The generic map gives the value of required generic parameters using the fol-
lowing syntax:
generic map(<formal_parameter> => <actual_parameter>, ...)
where:
<formal parameter> is the parameter name used in the original design entity
header.
<actual parameter> is an expression giving the value to be used for this in-
stantiation.
Here is the formal syntax for the port map:
port map(<formal\_parameter> => <actual_parameter>, ...)
where:
<formal parameter> is the signal name used in the original design entity header.
<actual parameter> is a signal name defined in the higher level design to con-
nect to this formal signal, or
open if the keyword open is given (only sensible for an output signal, no con-
nection is made.
2 The Generate Statement
The generate statement allows a potentially large number of subcomponents

to be instantiated with a for loop. Also, the generate statement can be used to
conditionally instantiate a subcomponent. First well look at the syntax, and
then an example of how to use such statements.

2.1 The For ... Generate Statement Structural VHDL
2.1 The For ... Generate Statement
The syntax of the for ... generate is:
<label> : for <variable> in <range> generate

begin
<concurrent_statements>
end generate <label>;
<label> is a name created by the designer for this generate statement.

<variable> is a variable name for the index for this loop, e.g. n.
<range> is range over which <variable> ranges, for example 0 to 15.
<concurrent statements> are then concurrent statements (usually, but not
restricted to, component instantiation statements) that are repeated.
2.2 The If ... Generate Statement
Conditional instantiation of subcomponents is possible with:
<label> : if <condition> then generate

begin
<concurrent_statements>
end generate <label>;
<label> is a name created by the designer for this generate statement.
<condition> is a conditional expression evaluated at compile time.

<concurrent statements> are then concurrent statements (usually, but not
restricted to, component instantiation statements) that are conditionally
inserted.
3 Example Design
In this section well look at the application of the above statements to the
structural design of an adder. You should not construct an adder in this way,

Structural VHDL
rather allow the synthesis tool to construct such a design. An adder is being
used here due to its familiarity and simplicity to illustrate the concepts above.
The design will be constructed with a single bit adder as the basic building
block. This has three inputs, cin (carry in), a and b and two outputs, the sum
bit sum and the carry out bit called cout. Here is the VHDL for the single bit
adder design:

Title : Single bit adder
Project : EG3560

File : adder1bit.vhd
Author : <d.c.hendry@abdn.ac.uk>
Company : Aberdeen University
Created : 2006-03-19
Last update: 2006-03-19
Platform :

Description: A single bit adder used in course EG3560 to illustrate use of
the for generate and if generate statements.

Copyright (c) 2006 DC Hendry, University of Aberdeen

Revisions :
Date Version Author Description
2006-03-19 1.0 eng186 Created

library ieee;
use ieee.std logic 1164.all;
entity adder1bit is
port (
cin, a, b : in std logic;
sum, cout : out std logic);
end adder1bit;
architecture rtl of adder1bit is
begin rtl
cout <= (cin and a) or (cin and b) or (a and b);

sum <= cin xor a xor b;

Structural VHDL
end rtl;
and then that for the complete N bit adder:

Title : N bit structural adder
Project : EG3560

File : adderNbit.vhd
Author : <d.c.hendry@abdn.ac.uk>
Company : Aberdeen University
Created : 2006-03-19
Last update: 2006-03-19

Description: An N bit adder constructed with for generate and if generate
statements.

Copyright (c) 2006 DC Hendry, University of Aberdeen

library ieee;
use ieee.std logic 1164.all;
entity adderNbit is
generic (
N : integer);
port (
a, b : in std logic vector(N 1 downto 0);
cout : out std logic;
sum : out std logic vector(N 1 downto 0));
end adderNbit;
architecture rtl of adderNbit is

component adder1bit
port (
cin, a, b : in std logic;
sum, cout : out std logic);
end component;
signal carries : std logic vector(N 1 downto 0);
begin rtl
carries(0) <= 0;

Structural VHDL
bn: for n in 0 to N 1 generate

bnm1: if n < N 1 generate
adder1bit 1: adder1bit
port map (
cin => carries(n),
a => a(n),
b => b(n),
sum => sum(n),
cout => carries(n+1));
end generate bnm1;
topbit: if n = N 1 generate
adder1bit 1: adder1bit
port map (
cin => carries(n),
a => a(n),
b => b(n),
sum => sum(n),
cout => cout);
end generate topbit;
end generate bn;
end rtl;

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Structural VHDL

March 19, 2006

VHDL contains a number of features supporting structural design. The most

1.1 Components and Component Instantiation

The component declaration (wherever it appears) has the syntax:

component <component_name> [is]

The optional <component name> may only appear in VHDL-93.

Here is an example of a component declaration taken from one of the laboratory

The syntax of a component instantation statement is:

<instantiation label> is a name constructed by the designer referring to this

Revision : 1.1 Page 2 of 7 Dr DC Hendry

generic map(<formal_parameter> => <actual_parameter>, ...)

Here is the formal syntax for the port map:

port map(<formal\_parameter> => <actual_parameter>, ...)

2 The Generate Statement

The generate statement allows a potentially large number of subcomponents

Revision : 1.1 Page 3 of 7 Dr DC Hendry

2.1 The For ... Generate Statement

The syntax of the for ... generate is:

<label> : for <variable> in <range> generate

<label> is a name created by the designer for this generate statement.

2.2 The If ... Generate Statement

Conditional instantiation of subcomponents is possible with:

<label> : if <condition> then generate

<label> is a name created by the designer for this generate statement.

<condition> is a conditional expression evaluated at compile time.

Revision : 1.1 Page 4 of 7 Dr DC Hendry

architecture rtl of adder1bit is

cout <= (cin and a) or (cin and b) or (a and b);

Revision : 1.1 Page 5 of 7 Dr DC Hendry

and then that for the complete N bit adder:

architecture rtl of adderNbit is

Revision : 1.1 Page 6 of 7 Dr DC Hendry

bn: for n in 0 to N 1 generate

Revision : 1.1 Page 7 of 7 Dr DC Hendry

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