Adsd PPR Cat 1

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ANJUMAN COLLEGE OF ENGINEERING & TECHNOLOGY

DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION

SESSION (2018-19)

CAT – 1 Subject : ADSD

Time : 1 hour 30 min Marks : 30

Q1) a) Expain the different design units used in Vhdl with their syntax. (5M)

Q1) b) Write vhdl code of 2 input Xor gate. (5M)

OR

Q2) a) Expain Vhdl development flow with suitable flow chart. (6M)

Q2) b) What are the advantages of vhdl over other conventional programming
languages. (4m)

Q3) a) Explain various data types supported by Vhdl. (6M)

Q3) b) Write a vhdl code for a 3:8 decoder using selected signal assignment statement.
(4M)

OR

Q4) a) Write a vhdl code for a Four – bit adder using structural type of modelling and
placing the component inside the architecture body. (5M)

Q4)b) what are data objects used in Vhdl. Expain with their syntax. (5M)

Q5)a) Write a vhdl code for BYTE ADDER circuit using generate statement. (5M)

Q5)b) Write the structural description of 16:1 mux using 4:1 mux using vhdl. (5M)

OR

Q6)a) What is subprogram? Explain ‘Function’ and ‘Procedure’ with their syntax. (5M)

Q6)b) Write a test bench for 8:1 mux. (5M)

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