Computer-Aided Design for Emerging Technologies

Leakage Minimization
Technique for Nanoscale
CMOS VLSI
Kyung Ki Kim and Yong-Bin Kim Nohpill Park
Northeastern University Oklahoma State University, Stillwater

Minsu Choi
University of Missouri-Rolla

application of ‘‘halo’’ profiles cause

Editor’s note: significantly large reverse-biased junc-
Leakage current is a major drawback in nanoscale CMOS. This article tion BTBT leakage currents through the
introduces a novel, practical approach that is amenable to CAD, to drain- and source-substrate junctions.1–3
heuristically estimate this current during standby mode. This is a serious problem in portable
—Fabrizio Lombardi, Northeastern University electronic systems that operate mostly in
sleep mode. To minimize leakage power
dissipation, researchers have proposed
several circuit techniques such as multi-
&BECAUSE OF THE continued scaling of technology threshold-voltage CMOS (MTCMOS) and variable-
and supply-threshold voltage, leakage power has threshold-voltage CMOS (VTCMOS) using variable
become more significant in power dissipation of substrate bias voltage. However, these techniques
nanoscale CMOS circuits. Therefore, estimating the require significant circuit modification and perfor-
total leakage power is critical to designing low-power mance overhead for leakage reduction.1,3
digital circuits. Another technique with little or no overhead is
In nanometer CMOS circuits, the main leakage the input pattern control technique based on the
components are the subthreshold, gate-tunneling, stack effect: the amount of leakage current of
and reverse-biased junction band-to-band-tunneling a nanometer CMOS circuit varies depending on
(BTBT) leakage currents. As transistor geometries the input pattern. However, it is an NP-hard problem
decrease, it is necessary to reduce the supply voltage to determine the input pattern that sets up the
to avoid electrical breakdown and obtain the required minimum leakage current during standby mode
performance. However, to retain or improve perfor- without any hardware overhead or architecture
mance, it is necessary to reduce the threshold voltage change. Researchers have proposed several tech-
(VTH) as well, which results in an exponential increase niques to generate the minimum leakage test
of subthreshold leakage. To control short-channel pattern and to solve the NP-hard problem,4–6 but
effect and increase the transistor driving strength in none of these techniques explicitly considers the
deep-submicron (DSM) circuits, gate-oxide thickness interactions among the subthreshold leakage, gate-
also becomes thinner as technology scales down. The tunneling leakage, body effect, and fan-out effect.
aggressive scaling in the gate oxide results in Although some articles have been published on
a tunneling current through the oxide, which is modeling subthreshold leakage and gate-tunneling
a strong exponential function of the oxide thickness leakage, they neglect the interactions among the
and the voltage magnitude across the oxide. In scaled three leakage components. They also do not
devices, the higher substrate doping density and the consider the fan-out effect in the leakage current.4–9

322 0740-7475/07/$25.00 G 2007 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
Therefore, this problem requires a better understand-
ing and a more accurate model of leakage currents
for input pattern control in nanometer CMOS circuits.
In this article, we investigate all the possible leakage
current components and propose a novel macromo-
deling technique to characterize the minimum leak-
age current of each individual leaf cell, considering
fan-out effect, stack effect, and the interaction between
gate-leakage and subthreshold currents. We devel-
oped a heuristic approach to find the input pattern for
minimum leakage current during standby mode of
nanoscale VLSI chips. Our approach uses the func-
Figure 1. Leakage current in a nanoscale CMOS circuit: off-
tional dependencies in VLSI and the controllability of
state (a) and on-state (b) leakage components.
its nodes.
gate-oxide thickness, the tunneling drops exponential-
Leakage power model and analysis ly. This is given by
In the off state, the main components of leakage  
Tox
{B VGS a
current are subthreshold leakage (ISubTH), gate- Igate tunneling ~ ðAC ÞðWLÞe ð1Þ
induced drain leakage (IGIDL), gate-tunneling leakage
(IGATE), and band-to-band tunneling (IBTBT), as Fig- where A 5 q3/(8phwb), B 5 8p (2mox)1/2wb3/2/(3hq),
ure 1a shows. Gate-tunneling leakage (IGATE) is the C 5 (VGS/Tox)2, and a is a parameter that ranges
major component during the on state, as Figure 1b from 0.1 to 1, depending on the voltage drop
shows.10 across the oxide. Here, h is Planck’s constant, and
The GIDL is a current from the drain to the substrate wb is the barrier height for electrons and holes in
the conduction and valence band.
caused by the high electric field between the gate and
In nanometer CMOS technology, the gate-tunneling
the drain; thin gate-oxide thickness and a high supply
leakage current is expected to increase to more than
voltage increase GIDL. The gate-tunneling leakage is
twice the subthreshold leakage current. Figure 2a
a current flowing into the transistor’s gate by
shows the gate-tunneling leakage currents produced
a tunneling effect; thin gate-oxide thickness and a high
by a nanoscale n-channel MOS transistor. As Figure 2a
supply voltage also increase gate-tunneling leakage.
shows, the gate-tunneling current consists of four
The subthreshold leakage is a weak inversion conduc-
components: gate-to-channel tunneling (IGC), gate-to-
tion current of the CMOS transistor when VGS is less
drain edge tunneling (IGD), gate-to-source edge
than VTH. It increases exponentially because of the
tunneling (IGS), and gate-to-body tunneling (IGB). The
reduced threshold voltage, and it is a main leakage
gate tunneling’s magnitude depends on the applied
component in the case of a high forward body bias.
voltage VGS. For NMOS, four possible states exist,
Finally, the BTBT leakage is a current by electron
depending on the voltages of the three terminals
tunneling across the reverse-biased pn junction
between the drain or source and the CMOS transistor’s
substrate. Therefore, in the case of a high reverse body
bias, the BTBT leakage becomes a major portion of the
total leakage current. Kuroda et al. show that the
subthreshold leakage current and the BTBT leakage
are more sensitive to the applied body bias than the
other two leakage components.10 The minimum
leakage current is obtained when the subthreshold
leakage current is equal to the BTBT leakage.
Figure 2. The gate-tunneling and subthreshold leakage current
Gate-tunneling leakage current in NMOS and PMOS transistors: maximum gate-tunneling
Gate-tunneling leakage is a current flowing (tun- leakage current state (a) and maximum subthreshold leakage
neling) into the transistor’s gate. With an increase of current state (b).

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 Computer-Aided Design for Emerging Technologies

known as junction BTBT.

If both n and p regions
are heavily and halo-
doped shallow junctions,
the BTBT significantly in-
creases and becomes
a major contributor to
the total leakage current.3
Figure 3 shows the ef-
fect of body-bias voltage
and supply voltage on
leakage power for a 45-
nm NMOS transistor. Fig-
ure 3 also shows that as
supply voltage and body-
bias voltage decrease,
leakage power decreases
because of ISubTH reduc-
tion. On the other hand,
leakage current starts in-
Figure 3. Leakage power as a function of body-bias voltage and supply voltage. creasing as the body bias
decreases from 20.9 to
(drain, gate, source): (1, 0, 0), (1, 0, 1), (0, 0, 1), and (0, 22.2 V because the increase of IBTBT becomes
1, 0). The leakage current under the (0, 1, 0) state is the dominant over the subthreshold leakage current.
highest due to the strong inversion. For a p-channel Therefore, the optimal body-bias voltage to minimize
MOS transistor, the current direction and the voltages the power dissipation is determined by the relationship
are the opposite of the NMOS transistor (as Figure 2a between ISubTH and IBTBT.
shows). Because holes must pass a higher barrier to
tunnel, the PMOS tunneling current is less than the Minimum leakage pattern generation
NMOS tunneling current.11,12 Because of stack effect, fan-out effect, and the
interaction between gate-leakage and subthreshold
Subthreshold leakage current currents, the leakage power of a circuit under
Even though the transistor’s gate voltage decreases standby mode depends on its input pattern.
below VTH, a small current still flows between the However, it is an NP-hard problem to determine
source and drain terminals, as Figure 2b shows.1–3 The the input pattern. An accurate heuristic approach is
subthreshold leakage current is given by required to solve the NP-hard problem for better
V {V   accuracy.
TH VDS 
{B GS {
Isubthreshold ~ I0 e gkT=q 1 { e kT=q ð2Þ
Stack effect
2 1.8
where I0 5 m0Cox(W/L)(kT/q) (1 2 e ), W and L When there are two or more stacked transistors, the
are the transistor channel width and length, m0 is the subthreshold leakage is reduced. This reduction
low field mobility, Cox is the gate-oxide capaci- depends on the choice of the input pattern during
tance, k is Boltzmann’s constant, q is the electronic standby periods because it determines the number of
charge, and N is the subthreshold swing factor. off transistors in the stack. Turning off more than one
transistor in a stack forces the intermediate node
BTBT leakage and body effect of nanoscale voltage to go to a higher value than 0.12 This causes
CMOS gates a negative VGS, a negative VBS (more body effect), and
In a high electric field (greater than 106 volts per a VDS reduction (less DIBL) in the top transistor closest
centimeter), electrons tunnel across the reverse-biased to the outputs, thereby reducing the subthreshold
pn junction of drain and source substrates, in what is leakage current flowing through the stack consider-

324 IEEE Design & Test of Computers

 sure the leakage compo-
nents are not counted
twice when the total
leakage currents of Inv
3 are calculated. In Fig-
ure 4, Igate_inv3 is the gate-
tunneling leakage of Inv
3; that is, only Igate_inv2
and Isub_inv2 are the leak-
age currents of Inv 2.

Fan-out effect
Depending on the pri-
mary input (PI) pattern,
Figure 4. Leakage current flows in nanoscale CMOS circuits. the subthreshold leakage
current and gate tunnel-
ably, which is known as the stack effect. The leakage ing are affected by the adjacent fan-in and fan-out
current decreases monotonously with the number of logic circuits. Figure 5 illustrates the dependency of
stacked off transistors. the leakage current on the fan-out structures. In
Because of the transistor stack effect, a gate’s Figure 5, the PI is logic 1, the number of fan-outs of
leakage current depends on its input combination. An inverter G2 is two, and the number of fan-outs of
individual CMOS gate shows a variation in the leakage inverter G3 is three. First, the current IgG3 is the gate-
power for different input patterns. Only a few input tunneling leakage of inverter G3. In this circuit, IgG2
patterns, defined as dominant leakage states, cause and IgG4 are the gate-tunneling leakage currents of G2
significant leakage. Therefore, 011, 101, 110, and 111 and G4, respectively. The directions of the three
input patterns of a 3-input NAND gate are dominant currents converge into the input of inverter G3.
leakage states. If the dominant leakage states of all The sum of the gate leakage currents at node N3 is
input patterns are used to generate macromodels, the a function of gate G1’s fan-out and the subthreshold
lookup table’s size for the macromodels is reduced by currents of G2, G3, and G4. The 0 state voltage at node
ignoring the rest. N3 increases as the fan-out of G1 increases, which in
Figure 4 shows the static current paths that appear turn reduces the gate-leakage current of G2, G3, and
when the leakage current is considered in CMOS G4 because the voltages between the inputs and
circuits. In the circuits, each inverter has a few paths of outputs of those gates are reduced. The gate-leakage
subthreshold and gate-tunneling leakage current. We currents of G2, G3, and G4 are also a function of their
can assume that Inv 2 is the device under test (DUT), subthreshold currents because the subthreshold cur-
and the input of Inv 1 is 0. Inv 2 has three leakage rents affect the voltage between those gates’ inputs
components, which depend on the fan-out structures and outputs. Considering these fan-out effects, IgG3 is
of Inv 2: about one-third of the gate-tunneling leakage when G1
has only one fan-out. Consequently, the subthreshold
& the gate-tunneling current Igate_inv2 starting from current is influenced by the number of fan-outs of the
the PMOS of Inv 1, previous driver. However, the fan-out of inverter G3
& the subthreshold leakage of the turned-off state cannot have a significant effect on the leakage current
PMOS in Inv 2 (Isub_inv2), and of inverter G3. As the number of fan-outs for G3
& the gate-tunneling current Igate_inv3 starting from increases, G3’s output voltage decreases, which then
Inv 3. reduces its subthreshold and gate-tunneling leakage
currents.
Therefore, the total leakage current is the sum Therefore, the total leakage of inverter G3 is
of Igate_inv2, Isub_inv2, and Igate_inv3. However, when affected by the fan-outs of G1 and G3. Hence, it is
a cell’s macromodel is generated, one leakage tun- necessary to consider the interaction of each leakage
neling current (Igate_inv3) should be removed to make current component in both previous stages and the

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 Computer-Aided Design for Emerging Technologies

consider the fan-out effect when model-

ing the leakage current, the smallest
total leakage is 3.34 mA under the
0 input, and the largest total leakage is
6.19 mA under the 1 input. In large
circuits, depending on the applied input
vector, leakage of different logic gates
moves in different directions (some
increase and some decrease). Because
of this, in such circuits, the net change
in overall leakage due to the fan-out
effect tends to be reduced by averaging
out the individual gate’s leakage current
change.

Input-pattern generation
Based on the fan-out effect in leakage
current, we developed the macromodel
for a leaf cell (inverter, NAND, and NOR
gates) based on an Hspice simulation,
where the controlling variables are the
number of fan-outs, the cell size, and the
Figure 5. Fan-out effect for the G3 gate. The leakage currents depend on the input pattern, considering the stack
fan-out structures of the G3 gate. [W/L of PMOS is (90 nm)/(45 nm), and W/L effect under fixed VDD, VTH, Tox, and
of NMOS is (45 nm)/(45 nm), where W and L are the transistor channel width temperature. On the basis of the accu-
and length.] rate macromodel of the cells, we
implemented a heuristic approach to
generate the minimum leakage test
next stages for an accurate leakage estimate in pattern. The leakage of each cell in the circuit depends
nanoscale CMOS circuits. However, the effects of the on the input pattern applied to the circuits. Research-
leakage current components beyond one logic level ers have proposed several techniques to generate the
from the DUT are negligible. input pattern for minimum leakage current and solve
4–6
Figure 6 presents the fan-out effect on the leakage the NP-hard problem. An easy way to solve the
current for inverter G3 shown in Figure 5. The leakage problem is to use the functional dependencies in the
currents are measured at inverter G3 in Figure 5. The circuits and the controllability of the nodes. In this
number of fan-outs of G1 varies from 1 to 5, as does the article, we improve the methodology to estimate the
number of fan-outs of G3. Figure 6a and Figure 6b accurate leakage current with a fast simulation time.
show the subthreshold leakage and gate tunneling, The functionality of the cells in circuits determines
respectively, when the input of inverter G3 is 1. the states of the internal nodes for any given input
Figure 6c and Figure 6d show the subthreshold vector. A cell is dominated if its input pattern causing
leakage and gate tunneling, respectively, when the the minimum leakage current is a subset of the
input of inverter G3 is 0. minimum leakage input pattern of the other cells. A
As expected, the number of fan-outs of G1 affects cell is conflicting if the input pattern causing the
the leakage current. For the 0 input to G3, the fan-outs minimum leakage conflicts with other cells’ input
of G3 significantly affect the leakage current, but less vectors that cause the minimum leakage.
than the fan-outs of the previous driver. We measured Before finding the optimal input pattern to reduce
the smallest total leakage (0.73 mA) for the 1 input with leakage power dissipation, the functional dependen-
five fan-outs of G1 and five fan-outs of G3. We see the cies between cells should be searched, and each cell’s
highest total leakage (2.33 mA) for the 0 input with one dominated and conflicting cells should be listed in the
fan-out of G1 and one fan-out of G3. If we do not order of the weight function, which is given by

326 IEEE Design & Test of Computers

Figure 6. Leakage current variation due to fan-out effect in BSIM4 45-nm technology: subthreshold leakage current
with input 1 (a), gate-tunneling leakage current with input 1 (b), subthreshold leakage current with input 0 (c), and
gate-tunneling leakage current with input 0 (d).

X X Once the list is determined, the cell that has the

Wc ðGi Þ ~ ðMLKcc ðGi ÞÞ { ðMLKdc ðGi ÞÞ least weight function will be selected. If the cell
i i satisfies the functional constraints for minimum
{ MLKfG { MLK ðGi Þ ð3Þ leakage current, the PI patterns controlled by the cell
are determined. After finding the proper input patterns,
where Wc(Gi) is the weight of cells Gi; and MLKcc, the cell is removed from the list, and at the same
MLKdc, and MLKfG are the mean leakage for time the cell’s dominated and conflicting cells are
conflicting cells, dominating cells, and fan-out of removed. This procedure is repeated until there are no
Gi, respectively. cells in the list or only undefined cells remain. If the

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macromodel and the controllability for the C17 circuit,

PI patterns that minimize leakage current are generat-
ed, then the conflicting and dominated cell lists are
identified, as Table 2 shows. However, the input vector
(1, 0) to gate G1 conflicts with the G2 and G5 inputs.
Therefore, the input pattern (1, 0) must be changed to
the input pattern that causes the next-least leakage
current, which is (0, 0), as Table 1 shows. This is a trade-
off between the minimum leakage current and the
conflicting input vectors. Consequently, the minimum
Figure 7. ISCAS85 benchmark circuit C17, which is used as an
leakage input patterns for G1 and G2 are changed to
example to explain our proposed heuristic algorithm.
00XXX and X00XX, respectively. The conflicting cells
undefined cells are found, proper patterns must be for G1 and G2 are removed from the list, and G1 among
assigned, considering the conditions for low leakage the conflicting cells for G5 is also removed because G1
current, because these cells have no dominated or no longer conflicts with G5. At the same time, the
conflicting cells. weight function for each cell must be updated using
The example ISCAS85 benchmark circuit C17 Equation 3, and a cell with the least weight function
shown in Figure 7 explains this proposed heuristic must be identified. In this case, G1 and G2 are the cells
approach in detail. As we described at the beginning with the least weight function, so the two cells are
of this subsection, a macromodel is generated for all removed from the list, and the 000XX input pattern is
the cells in the library, and the macrocells contain all determined by combining 00XXX and X00XX. G4 is the
the leakage current information for all the possible next cell that has the least weight function among the
input and fan-out cases. For example, the two-input remaining cells. If G4 is removed from the list, G4 and its
NAND gate in Figure 7 has the leakage currents shown conflicting cell G6 are also removed, and the 000X0
in Table 1 for different inputs and a fan-out of 2. pattern is determined. Finally, G3 and G5 are left.
In Table 1, Input 1 represents the input to the Because the weight function of G5 is smaller than G3,
transistor closest to the output. For a NAND gate, the G5 is removed from the list, and the input pattern
total leakage is the lowest when the inputs are (1, 0) becomes 00010, which is the final input pattern.
and the gate leakage current is dominant over the
subthreshold current. If the subthreshold current is Experimental results
larger than the gate leakage, then the total leakage is We implemented our minimum leakage test pattern
lowest when the inputs are (0, 0). In this article, we generator for nanometer CMOS gates in Hspice and C
consider nanoscale CMOS technology that has a larger language and ran it on a 500-MHz UltraSparc-IIe with
gate-tunneling current than the subthreshold current. 500 Mbytes of memory. We were able to demonstrate
The primary-input patterns for minimum leakage the algorithm using the results from various ISCAS85
current and the lists of dominating and conflicting benchmark circuits. Each benchmark circuit was
cells are created using the test controllability lists of the designed using Hspice in a 45-nm BSIM4 model. The
C17 circuit. The possible input patterns can be minimum leakage current was measured using Monte
obtained from the macromodel of each cell. Carlo simulations with 50 repetitions in Hspice. Monte
The detailed procedure is as follows: On the basis of Carlo simulations let us iteratively evaluate a determin-
the leakage current information of each cell from the istic model using many sets of random numbers as
inputs. These simulations generated many random
inputs, and we ran Hspice simulations for the circuit
Table 1. Total leakage current for a two-input NAND gate. with those inputs; we then selected the least leakage
Input 1 Input 2 Total leakage current (mA) from the results. In addition, we compared the results
0 0 0.33 of our proposed methodology with and without the
0 1 1.01 fan-out effect.
1 0 0.15 Table 3 compares the simulation results for our
1 1 1.61 proposed method with other simulations. Our method’s
accuracy is within a 4% difference of the Hspice

328 IEEE Design & Test of Computers

 Table 2. Input patterns for minimum leakage

Minimum leakage input

pattern of each cell Minimum leakage input pattern
Cell Input 1 Input 2 A1 A2 A3 A4 A5 Conflicting cells
G1 1 0 1 0 X X X G2, G5
G2 1 0 X 1 0 X X G1
G3 1 0 X X 0 0 X G5
G4 1 0 X X 0 X 0 G6
G5 1 0 0 X 0 1 X G1, G3, G6
G6 1 0 X X X 0 1 G4, G5

Table 3. Leakage estimation results for benchmark circuits.

Estimated leakage current

(mA) Hspice CPU runtime
No. of Without With fan-out minimum Error Our work Hspice
Circuit gates fan-out effect effect leakage (mA) rate (%) (ms) (s)
C432 160 3.75 1.49 1.53 2.70 0.89 9.45
C499 202 10.48 6.78 7.00 3.20 5.60 40.34
C880 383 9.67 5.34 5.40 1.20 3.50 28.88
C1355 546 16.54 7.43 7.21 3.90 5.87 40.41
C1908 880 15.53 6.84 6.57 4.00 6.65 35.98
C2670 1,193 18.43 11.14 10.75 3.50 9.88 64.83
C5315 2,307 35.12 29.54 29.18 1.22 16.30 185.98
C6288 2,388 33.48 26.57 25.88 2.60 42.57 987.45
C7552 1,916 35.67 28.57 29.38 2.83 23.84 235.87

simulation results. In addition, the simulation time of accurate macromodel, because the leakage current
our method is far faster than that of the Hspice below 90-nm technology is sensitively affected by
simulation. PVT variations. &
It is not easy to compare our method with alternate
approaches, because most of the previously published & References
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requires little or no overhead, but they are NP-hard Proc. IEEE, vol. 91, no. 2, Feb. 2003, pp. 305-327.
problems. Our heuristic approach solves the previous 2. A. Agarwal et al., ‘‘Leakage Power Analysis and
approaches’ problems, considering all the leakage Reduction: Models, Estimation and Tools,’’ IEE Proc.
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to compare the complexity of the algorithms. The 3. S.G. Narendra and A. Chandrakasan, Leakage in
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 Computer-Aided Design for Emerging Technologies

Computer Aided Design,’’ Proc. Int’l Conf. Computer-Aided circuit design. Kim has a BS from Sogang University,
Design (ICCAD 04), IEEE CS Press, 2004, pp. 527-532. Seoul, an MS from the New Jersey Institute of
6. X. Chang et al., ‘‘SoC Leakage Power Reduction Technology, and a PhD from Colorado State Univer-
Algorithm by Input Vector Control,’’ Proc. Int’l Symp. sity, all in electrical engineering. He is senior member
System-on-Chip, IEEE Press, 2005, pp. 86-89. of the IEEE.
7. Y. Xu, Z. Luo, and X. Li, ‘‘A Maximum Total Leakage Current
Estimation Method,’’ Proc. Int’l Symp. Circuits and Systems Minsu Choi is an associate pro-
(ISCAS 04), vol. 2, IEEE Press, 2004, pp. 757-760. fessor in the Department of Electrical
8. Y. Xu et al., ‘‘Average Leakage Current Macromodeling and Computer Engineering at the
for Dual-Threshold Voltage Circuits,’’ Proc. 12th Asian University of Missouri-Rolla. His re-
Test Symp, (ATS 03) IEEE CS Press, 2003, pp. 196-201. search interests include computer
9. R. Kumar and C.P. Ravikumar, ‘‘Leakage Power architecture and VLSI, embedded systems, fault
Estimation for Deep Submicron Circuits in an ASIC tolerance, testing, quality assurance, reliability mod-
Design Environment,’’ Proc. Conf. Asia South Pacific eling and analysis, configurable computing, parallel
Design Automation / VLSI Design (ASP-DAC/VLSID 02), and distributed systems, instrumentation and mea-
IEEE CS Press, 2002, pp. 45-50. surement, and computational nanotechnology. Choi
10. T. Kuroda et al., ‘‘Variable Supply-Voltage Scheme for has a BS, an MS, and a PhD in computer science
Low-Power High Speed CMOS Digital Design,’’ IEEE J. from Oklahoma State University, Stillwater. He is
Solid-State Circuits, vol. 33, no. 3, Mar. 1998, pp. 454-462. a member of Sigma Xi and of the Golden Key
11. S. Yang et al., ‘‘Accurate Stacking Macro-modeling of National Honor Society.
Leakage Power in Sub-100 nm Circuits,’’ Proc. 18th Int’l
Conf. VLSI Design (VLSID 05), IEEE CS Press, 2005, Nohpill Park is an associate pro-
pp. 165-170. fessor in the Computer Science De-
12. D. Lee et al., ‘‘Analysis and Minimization Techniques for partment at Oklahoma State Universi-
Total Leakage Considering Gate Oxide Leakage,’’ Proc. ty, Stillwater. His research interests
40th Design Automation Conf. (DAC), ACM Press, 2003, include computer architecture, de-
pp. 175-180. fect- and fault-tolerant systems, testing and quality
assurance of digital systems, parallel and distributed
computer systems, multichip-module systems, pro-
Kyung Ki Kim is a PhD candidate in grammable digital systems, and SoCs. Park has a BS
the Department of Electrical and and an MS in computer science from Seoul National
Computer Engineering at Northeast- University and a PhD in computer science from Texas
ern University. His research interests A&M University.
include high-speed, low-power VLSI
design; analog VLSI circuit design; electronic CAD; & Direct questions and comments about this article to
and ATE system design. Kim has a BS and an MS in Yong-Bin Kim, Dept. of Electrical and Computer
electronics engineering from Yeungnam University, Engineering, Northeastern University, 442 Dana Re-
Kyungsan, South Korea. search Center, 360 Huntington Ave., Boston, MA
02115; ybk@ece.neu.edu.
Yong-Bin Kim is an associate pro-
fessor in the Department of Electrical
and Computer Engineering at North- For further information on this or any other computing
eastern University. His research fo- topic, visit our Digital Library at http://www.computer.
cuses on high-speed, low-power VLSI org/publications/dlib.

330 IEEE Design & Test of Computers