Eet202/3 Digital Electronics Ii Tutorial 4

EET202 Tutorial 4
EET202/3 DIGITAL ELECTRONICS II

TUTORIAL 4
1. Perform the datapath for the following microoperation by using Appendix 1. The value of R4 and
R5 are 002 and 012.
R0
 R1 R3
2. Design a 4-bit arithmetic circuit with two selection variables S 1 and S 0, which generates the
arithmetic operations in Table 1. Draw the logic diagram for a single bit stage.
Table 1
S1 S0 Cin=0 Cin=1
0 0 F  A  B (add ) F  A  B 1
EET202 Tutorial 4
0 1 F  A (transfer) F  A  1 (increment)
1 0 F  B (complement) F  B  1 ( negate)
1 1 F  A B F  A  B  1 (subtract)
EET202 Tutorial 4
EET202 Tutorial 4
3. Design a 2-bit logic circuit that will perform the logic operations according to Table 2.
Table 2
S1 S0 Operation
0 0 F  A B
0 1 F  A B
1 0 F  A B
1 1 FA
EET202 Tutorial 4
4. Design a 4-bit arithmetic circuit with two selection variables, S 1 and S0, that generates the
arithmetic operations in Table 3. Draw the logic diagram for a single bit stage.
Table 3
S1 S0 Cin=0 Cin=1
0 0 F  A B F  A  B  1 (subtract)
0 1 F  A  B (add ) F  A  B 1
1 0 F  A (transfer) F  A  1 (increment)
1 1 F  B (complement) F  B  1 ( negate)
Answer: Follow step similar with question 2 to obtain the answer
5. Design an arithmetic circuit with two selection variables S1 and S0 and two n-bit data input A and
B. The circuit generates the following eight arithmetic operations in conjunction with carry C in as
in Table 4.
Table 4
S1 S0 Cin=0 Cin=1
0 0 F  A B F  A  B  1 ( subtract B  A)
0 1 F  A  1 (decrement) F  A  1 (increment)
1 0 F  A  B (add ) F  A  B  1 ( subtract A  B)
1 1 F  A (1' s complement) F  A  1 (2' s complement)

EET202 Tutorial 4
6. Design an arithmetic circuit with two selection variables S 1 and S0 and two n-bit data input A and
B. The circuit generates the following eight arithmetic operations in conjunction with carry Cin as
shown in Table 5.
Table 5
S1 S0 Cin=0 Cin=1
0 0 F  A  B (add )
F  A  B  1 (subtract A  B)
0 1 F  A  1 ( decrement) F  A  1 (increment)
1 0 F  A B F  A  B  1 (subtract B  A)
1 1 F  A (1' s complement) F  A  1 (2' s complement)
7. The logic diagram for a 4-bit arithmetic circuit, using full adder and multiplexer is shown in
Figure 1.
Figure 1
i. Determine the simplified Boolean function / expression for input XI and Yi.
EET202 Tutorial 4
EET202 Tutorial 4
ii. Determine the arithmetic operation that performed for each of the four combinations
of
S & Cin  {00, 01, 10, 11}
Specify the arithmetic operation in function table.

EET202 Tutorial 4
8. Design one stage of a 4-bit arithmetic circuit that will perform arithmetic operations between
two 4-bit binary numbers, A and B according to Table 6. Use 4-to-1 multiplexers, full adder and
logic gates on your design.
Table 6
Select Output
Operation
S1 S0 Cin F
0 0 0 F  A B Add
0 0 1 F  A  B 1 Add with carry
0 1 0 F  A B Subtract with borrow
0 1 1 F  A  B 1 Subtract
1 0 0 FA Transfer
1 0 1 F  A 1 Increment A
1 1 0 F  A 1 Decrement A
1 1 1 FA Transfer
9. With reference to the Control Word structure and the Encoding of Control Word table as
specified in Appendix 2, obtain the 16-bit control word to implement each of the following
micro-operations:
i. R6  srR6
ii. R 4  R6  2
EET202 Tutorial 4
10. Use Appendix 1 as reference. The width of registers shown is 8-bit. Each register contains the
same value as their register number. (e.g.: register R5 contains 05 in hexadecimal) before the
execution of a control word. Determine the new register content as a result of the execution of
each of the Control Words set given below:
i. Set A : 111 101 000 0 1001 0 1
ii. Set B : 010 010 011 0 0010 0 1

EET202 Tutorial 4
iii. Set C : 100 011 110 0 1110 0 1
11. Refer to the 4-bit barrel shifter in the Figure 2. Determine the output Y (Y3, Y2, Y1, Y0) for each of
the following bit patterns applied to S1, S 0, D3, D2, D 1 and D0:
i. 111010
ii. 010011
iii. 101110
EET202 Tutorial 4
EET202 Tutorial 4
12. Given are three sets 16-bit control words:
Set A : 110 010 100 0 0101 0 1

Set B : 101 100 101 0 1000 0 1
Set C : 011 000 000 0 0000 1 1
The width of the register is 8-bit and that, before the execution of a control word, they contain
the value of their number (e.g.: register R5 contains 05 in hexadecimal).
Data-in has the value of 1B.
With reference to the Control Word structure and the Encoding of Control Word table as
specified in Appendix 1, determine for each control word set above:
i. the micro-operation that is executed.

ii. the new value of the register contents for each of the control word.

Eet202/3 Digital Electronics Ii Tutorial 4

Uploaded by

Copyright:

Available Formats

Eet202/3 Digital Electronics Ii Tutorial 4

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Eet202/3 Digital Electronics Ii Tutorial 4

Uploaded by

Copyright:

Available Formats

EET202 Tutorial 4

EET202/3 DIGITAL ELECTRONICS II

Answer: Follow step similar with question 2 to obtain the answer

Answer: Follow step similar with question 2 to obtain the answer

Answer: Follow step similar with question 2 to obtain the answer

Specify the arithmetic operation in function table.

Answer: Follow step similar with question 2 to obtain the answer

i. Set A : 111 101 000 0 1001 0 1

ii. Set B : 010 010 011 0 0010 0 1

iii. Set C : 100 011 110 0 1110 0 1

12. Given are three sets 16-bit control words:

Set A : 110 010 100 0 0101 0 1

Data-in has the value of 1B.

i. the micro-operation that is executed.

Answer: Follow step similar with question 10 to obtain the answer

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.