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    Arithmetic Logic Unit: CSE 429 Digital System Design

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    tor 3
    The overflow bit V indicates whether an arithmetic operation resulted in a wrapped around overflow or underflow. For subtraction of signed numbers, overflow occurs if: - Both operands have the same sign bit (both positive or both negative) - The sign bit of the result is different than the sign bit of the operands This happens when subtracting the most negative number from the most positive number, or vice versa. The sign bit of the operands is C4, and the carry out bit C5 indicates whether the result wrapped around (changed sign). So V = 1 if C5 != C4, indicating the sign changed due to wrapping around overflow/underflow. V = 0 if C5 =

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    Arithmetic Logic Unit: CSE 429 Digital System Design

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    tor 3
    40 views36 pages
    The overflow bit V indicates whether an arithmetic operation resulted in a wrapped around overflow or underflow. For subtraction of signed numbers, overflow occurs if: - Both operands have the same sign bit (both positive or both negative) - The sign bit of the result is different than the sign bit of the operands This happens when subtracting the most negative number from the most positive number, or vice versa. The sign bit of the operands is C4, and the carry out bit C5 indicates whether the result wrapped around (changed sign). So V = 1 if C5 != C4, indicating the sign changed due to wrapping around overflow/underflow. V = 0 if C5 =

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    2-ALU.pptx

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    The overflow bit V indicates whether an arithmetic operation resulted in a wrapped around overflow or underflow. For subtraction of signed numbers, overflow occurs if: - Both operands have the same sign bit (both positive or both negative) - The sign bit of the result is different than the sign bit of the operands This happens when subtracting the most negative number from the most positive number, or vice versa. The sign bit of the operands is C4, and the carry out bit C5 indicates whether the result wrapped around (changed sign). So V = 1 if C5 != C4, indicating the sign changed due to wrapping around overflow/underflow. V = 0 if C5 =

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    40 views36 pages

    Arithmetic Logic Unit: CSE 429 Digital System Design

    Uploaded by

    tor 3
    The overflow bit V indicates whether an arithmetic operation resulted in a wrapped around overflow or underflow. For subtraction of signed numbers, overflow occurs if: - Both operands have the same sign bit (both positive or both negative) - The sign bit of the result is different than the sign bit of the operands This happens when subtracting the most negative number from the most positive number, or vice versa. The sign bit of the operands is C4, and the carry out bit C5 indicates whether the result wrapped around (changed sign). So V = 1 if C5 != C4, indicating the sign changed due to wrapping around overflow/underflow. V = 0 if C5 =

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    © All Rights Reserved
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    Download as pptx, pdf, or txt
    of 36

    Arithmetic Logic Unit

    CSE 429
    Digital System Design
    Block Diagram
    4 bit ALU
    •Multi-operation, combinational-logic
    digital function
    •Can perform a set of basic arithmetic
    operations and a set of logic operations
    •K selection variables  upto 2k
    distinct operations
    • We will use k = 3, that means 23 = 8
    operations. But we will implement
    12!
    •Input and output carries are
    meaningful only during arithmetic
    operations
    Operation modes
    S2 S1 S0 Cin Operations
    0 ? ? ? 8 arithmetic operations
    1 ? ? 0 4 logical operations
    Full specification
    S2 S1 S0 Cin Operation Type
    0 0 0 0 A Arithmetic
    0 0 0 1 A+1 Arithmetic
    0 0 1 0 A+B Arithmetic
    0 0 1 1 A+B+1 Arithmetic
    0 1 0 0 A–B–1 Arithmetic
    0 1 0 1 A–B Arithmetic
    0 1 1 0 A–1 Arithmetic
    0 1 1 1 A Arithmetic
    1 0 0 X A + B (OR) Logical
    1 0 1 X AB Logical
    1 1 0 X A.B Logical
    1 1 1 X A’ Logical
    Arithmetic Circuit
    Specification of Arithmetic Circuit
    S1 S0 Cin Operation
    0 0 0 A
    0 0 1 A+ 1
    0 1 0 A+ B
    0 1 1 A+ B+ 1
    1 0 0 A– B– 1
    1 0 1 A– B
    1 1 0 A– 1
    1 1 1 A
    What’s inside the ALU?
    Answer: Full adders
    X
    Functions of F/A? F
    Y
    F =XYZ
    Cout = XY + Cin .(X  Y)
    Bad design
    - Use separate circuits to generate each function
    - Use a MUX to output the required function

    Why?
    - MUX is actually combination of AND and OR gates. A lot of unnecessary
    transistors used. Bad for latency and area. Therefore bad for processor design.
    Correct Design
    Find out what the input should be for each function.
    And then simplify the input function.
    Ci
    The circuit should look somewhat like this

    Xi
    Ai
    Combinatorial Fi
    Full Adder
    Circuit Yi
    Bi

    S2 S1 S0
    Ci+
    1
    Transfer and Increment
    S1 S0 Cin Operation X Y
    0 0 0 A A 0
    0 0 1 A+ 1 A 0

    So we can just XOR A with 0 to get the desired result


    Add and Add with Carry
    S1 S0 Cin Operation X Y
    0 1 0 A+ B A B
    0 1 1 A+ B+ 1 A B

    We can just XOR A with B to get the desired result


    How about these two?
    S1 S0 Cin Operation X Y
    1 0 0 A– B– 1 A B’
    1 0 1 A– B A B’

    -B is actually equal to B’ + 1
    So we can set Y = B’
    How can we decrement?
    S1 S0 Cin Operation X Y
    1 1 0 A– 1 A 1111
    1 1 1 A A 1111

    Adding all 1 (1111) to a 4 bit number is equivalent to decrementing the number


    So we can set Y = 1111
    Final Table
    S1 S0 Cin X Y Operation
    0 0 0 A 0 A
    0 0 1 A 0 A+1
    0 1 0 A B A+B
    0 1 1 A B A+B+1
    1 0 0 A B’ A–B–1
    1 0 1 A B’ A–B
    1 1 0 A 1111 A–1
    1 1 1 A 1111 A

    We can keep X = A fixed for arithmetic operations and find a function of Y


    Input Functions
     
    Effect of Output Carry
    1. F = A (A  0)
    Cout is always 0
    2. F = A + 1
    If A = 1111, A+ 1 = 10000, So Cout will be 1
    Otherwise Cout is 0
    3. F = A + B
    If A + B > 1111, Cout = 1
    Otherwise Cout is 0
    4. F = A + B + 1
    If A + B ≥ 1111, Cout = 1
    Otherwise Cout is 0
    Effect of Output Carry
    5. F = A – B – 1
    For Cout to be 1, the result has to be greater than or equal to 10000 (24)
    That means A – B – 1 ≥ 24 (10000)
     A – B > 24 (We can replace 24 by 0)
     A> B
    So Cout = 1 if A > B
    And Cout = 0 otherwise.
    6. F = A – B
    Similar, just Cout = 1 if A ≥ B
    And Cout = 0 otherwise.
    Effect of Output Carry
    7. F = A – 1
    Remember we don’t actually subtract 1, but rather add 1111.
    If A = 1, we have 1 + 1111 = 10000, so we’ll have Carry
    So, Cout = 1 if A ≥ B and 0 otherwise
    8. F = A
    We actually add 10000 (1111 + 1) to A.
    So Cout will always be 1.
    Logic Circuit
    Specifications
    Remember that S2 = 1 for logic operations and Cin = 0

    S1 S0 Function
    0 0 A + B (OR)
    0 1 A  B (XOR)
    1 0 A.B (AND)
    1 1 A’
    (COMPLEMENT)
    Bad Design (yet again)
    - Keep the arithmetic circuit like it is
    - Implement the logic functions
    - Use a MUX to select desired output
    Correct way to do it
    For Arithmetic operation, we didn’t have to manipulate the X input.
    It was fixed as Xi = Ai
    For logical operation we will change it.
    Depending on the operation, we OR some value to the input of Xi
    OR
    - Recall that for S1S0 = 00, we had Yi
    =0
    - We will only OR some value to Xi S1 S0 Function
    - What should we OR in this case? 0 0 A + B (OR)

    - Answer: Bi
    So Yi = 0 and Xi = Ai + Bi
    Result of F/A (XOR) is Fi = Ai + Bi
    XOR
    - Recall that for S1S0 = 01, we had Yi =
    Bi
    - So the output of the F/A will be S1 S0 Function
    Fi = Ai  Bi 0 1 A  B (XOR)
    - We don’t need to add anything else
    AND
    -Recall that for S1S0 = 10, we had Yi =
    Bi’
    -So now we need to OR some value to S1 S0 Function
    Xi so that the result is Fi = Ai.Bi 1 0 A.B (AND)
    - Suppose Xi = Ai + Ki
    - We can find that for Ki = Bi’, Fi will
    be equal to Ai.Bi

    So we will use Xi = Ai + Bi’


    COMPLEMENT
    Recall that for S1S0 = 11, we had Yi =
    1111
    Now, if we XOR any number with 1111, S1 S0 Function
    what will happen? 1 1 A’ (COMP)
    1111
    1001
    --------
    0110
    We get the complement of the number!
    So we don’t need to change anything here
    Final logic circuit
    We need
    Xi = Ai + Bi for OR (S1S0 = 00)
    And Xi = Ai + Bi’ for AND (S1S0 = 10)
    Others can stay the same
    So when S1S0 = 00 we OR Bi to Xi
    And when S1S0 = 10 we OR Bi’ to Xi

    So Xi = Ai + S2S1‘S0’ Bi + S2S1S0’ Bi’


    Note the extra S2 in the equation, why is it there?
    Combined Circuit (Arithmetic + Logic)
     
    Status Register
    Status Bits
    If we are using unsigned numbers, then we need only 2
    - Carry (C)
    - Zero (Z)

    When using signed numbers, we need 4


    - Carry (C)
    - Sign (S)
    - Zero (Z)
    - Overflow (V)
    Using status bits for relational operators
    Suppose we need to compare 2 numbers stored in A and B and then determine if a
    particular relation (greater than, equal etc. ) is true or not.

    What should we do?

    Answer- Perform A-B and check the value of the status bits
    Unsigned Numbers
    Carry flag is set whenever we have Cout = 1
    Zefo flag is set whenever the result of the ALU is 0.

    So if,
    A – B = 0  A = B, Z = 1
    A – B ≠ 0  A ≠ B, Z = 0
    Again
    A – B ≥ 24 (0)  A ≥ B, C = 1
    A – B < 24 (0)  A < B, C = 0
    Unsigned Numbers
    Relation Condition Function
    A> B C = 1 and Z = 0 CZ’
    A≥B C=1 C
    A< B C=0 C’
    A≤B C = 0 or Z = 1 C’ + Z
    A= B Z=1 Z
    A≠B Z=0 Z’
    Signed Numbers
    - Bit C is set if the output carry of the ALU is 1. Cleared if Cout is 0
    C = C5
    - Bit S is set if the highest-order bit of the result in the output of the ALU (sign bit) is
    1. It is cleared if the highest order bit is 0.
    S = C4
    - Bit Z is set if the output of the ALU contains all 0s, and cleared otherwise
    Z = 1 if all 0. Z = 0 otherwise
    - Bit V is set if the exclusive-OR of C5 and C4 is 1, and cleared otherwise.
    V = C5  C4
    Why is V = C5  C4?

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