Xilinx XC9500 CPLD Series ™

The low-cost solution for 2.5V, 3.3V, and 5V applications

Today’s cutting-edge system

designs demand new levels of 144-Pin
CSP
performance, low cost, expansive 48-Pin
CSP
feature sets, and flexibility.
The Xilinx XC9500 CPLD
series provides all these capabilities,
64-Pin
plus superior pin locking that VQFP 144-Pin 256-Pin
TQFP BGA
allows designers to change CPLD
designs without affecting board 44-Pin 208-Pin
PLCC PQFP
layout—even when the system 100-Pin
TQFP
is in the field.
Xilinx makes it easy to
develop your CPLD design. The Complete CPLD Solution
You can download free software The Xilinx XC9500 CPLD series provides a comprehensive solution for a wide range
of applications:
tools and start development today.
• Voltage translation • Standard bus interface (I2C,SPI,8b10b)
We also offer a wide range of • I/O expansion • Microprocessor interface
reference designs and application • Bus transceiver • DRAM controllers
• ASIC patch • Video clock generator
notes so you can complete your • Discrete logic replacement • Display driver
design faster and more reliably. • PAL/GAL consolidation • State machine/control logic

You can even use our low-cost The XC9500 series gives you a wide range of options to meet your exact needs. You can
choose from 36 to 288 macrocells, and 2.5V, 3.3V, or 5V operation. Whichever family
design kit to verify your design you choose, you get the high performance, superior pin locking, high reliability, and
quickly and get it into production. low cost your application demands.

Xilinx CPLD design tools offer Maximum Design Flexibility

• Advanced, second-generation pin locking for easy redesign without changing
the same environment as those board layout
used by our higher density • In-system programming (ISP) and full IEEE 1149.1 JTAG boundary scan for superior
debug and design-iteration capability
FPGAs, providing a seamless
• Re-configurable throughout the full commercial operating range and a high programming
logic development solution. endurance rating for worry-free system updates in the field
• 36 to 288 macrocell densities available with multiple package options and I/O capacity
This makes completing your
for easy migration across multiple densities
designs faster, easier, and more • Output slew rate control and user-programmable ground pins to reduce system noise
cost-effective than ever before.
Easy-to-use, Industry-leading Software Tools Get Started Today!
The XC9500 CPLD series is supported in all versions of the Xilinx Information about our CPLDs, plus reference designs and applications
Integrated Software Environment (ISE) which include ISE WebPACK™, notes, is available on our web site, so you can start earlier and finish
WebFITTER™, and ISE Foundation. your design faster. Then, complete your design with the Xilinx CPLD
• ISE WebPACK is a free, downloadable desktop solution that offers Design Kit (see details at http://www.xilinx.com/cpldkit) and get
VHDL, Verilog, and ABEL synthesis and simulation, JTAG and your product developed faster.
third-party EDA support, and device support for all Xilinx CPLD
Go to http://www.xilinx.com/xc9500 to learn more about how the
and FPGA families up to 400K gates.
Xilinx XC9500 CPLD series can support your designs.
• WebFITTER is a Web-based CPLD design fitter tool that allows you
to evaluate your designs using XC9500 and all other Xilinx CPLD
families. It accepts VHDL, Verilog, and ABEL, and standard net list
inputs. You can also convert existing CPLD designs from other
manufacturers into the appropriate Xilinx CPLD.
• ISE Foundation is a full-featured software environment that supports
For Quick and Easy search for 9500 development boards visit Xilinx
all our current CPLD and FPGA families.
on Board site @ http://www.xilinx.com/xlnx/xebiz/board_search.jsp
XC9500 Series
36 Macrocell 72 Macrocell 108 Macrocell 144 Macrocell 216 Macrocell 288 Macrocell

XC9500XV CPLDs
XC95144XV

XC95288XV
XC95144XL

XC95288XL
XC9536XV

XC9572XV
XC9536XL

XC9572XL

XC95108

XC95144

XC95216

XC95288
• 2.5V core voltage
XC9536

XC9572

Features • Two I/O banks on higher densities

Speed Grades 5, 6, 5, 7, 5, 7 7, 10, 5, 7, 5, 7 7, 10, 15, 20 7, 10, 5, 7, 5, 7 10, 15, 20 10, 15, 6, 7, 6, 7,
• 3.3V, 2.5V, 1.8V I/O interfacing
10, 15 10 15 10 15 10 20 10 10 • Power-reduction mode
MAX I/O 34 36 36 72 72 72 108 133 117 117 166 192 192 192
XC9500XL CPLDs
Vcc (Volts) 5 3.3 2.5 5 3.3 2.5 5 5 3.3 2.5 5 5 3.3 2.5
• 3.3V core voltage
Package Type • Lowest cost per macrocell
VQ44 34 34 34 34 34 • 5.0V, 3.3V, 2.5V I/O interfacing
PC44 34 34 34 34 34 34 • Power-reduction mode
CS48 34 36 36 38 38 XC9500 CPLDs
VQ64 36 52 • 5V core voltage
PC84 69 69 • 5.0V, 3.3V I/O interfacing
TQ100 72 72 72 81 81 81 81 • Broad I/O and package offering
• Power-reduction mode
PQ100 72 81 81

CS144 117 117

TQ144 117 117 117 117

PQ160 108 133 133

HQ208 166 168

PQ208 168 168

BG256 192

FG256 192 192

CS280 192 192

BG352 166 192

Corporate Headquarters European Headquarters Japan Asia Pacific

Xilinx, Inc. Xilinx, Ltd. Xilinx, K. K. Xilinx, Asia Pacific
2100 Logic Drive Citywest Business Campus Shinjuku Square Tower 18F Unit 1201, 12/F, Tower 6
San Jose, CA 95124 6-22-1 Nishi-Shinjuku Gateway
Saggart,
Tel: 408-559-7778 Shinjuku-ku, Tokyo 9 Canton Road
Co. Dublin Tsimshatsui, Kowloon
Fax: 408-559-7114 Ireland 163-1118, Japan
Web: www.xilinx.com Hong Kong The Programmable Logic CompanySM
Tel: +353-1-464-0311 Tel: 81-3-5321-7711 Tel: 852-2-424-5200
Fax: +353-1-464-0324 Fax: 81-3-5321-7765 Fax: 852-2-494-7159
Web: www.xilinx.com Web: www.xilinx.co.jp E-mail: ask-asiapac@xilinx.com

© 2003 Xilinx Inc. All rights reserved. The Xilinx name and logo are registered trademarks; XC9500, WebPACK and WebFITTER are trademarks; and The Programmable Logic Company is a service mark of Xilinx Inc.
All other trademarks are the property of their owners.

Printed in U.S.A. PN 0010570-03