Simulink PLC Coder™ Release Notes
Simulink PLC Coder™ Release Notes
Simulink PLC Coder™ Release Notes
Phone: 508-647-7000
R2015a
R2014b
iii
R2014a
R2013b
iv Contents
R2013a
R2012b
R2012a
v
Global Tunable Parameters for Generated Code from
Rockwell Automation RSLogix 5000 Add-On Instructions
and Routine Formats and Phoenix Contact PC WORX . . . 7-2
R2011b
R2011a
vi Contents
Generated Code File Name Can Now Be Renamed . . . . . . . . 9-2
R2010b
R2010a
vii
R2015a
Version: 1.9
New Features
Bug Fixes
R2015a
This behavior allows you to easily map variables defined in your MATLAB code to
the ones in the generated structured text. Earlier, certain optimizations during code
generation caused reuse of variable names.
1-2
R2014b
Version: 1.8
New Features
Bug Fixes
R2014b
2-2
R2014a
Version: 1.7
New Features
Bug Fixes
R2014a
Code generation for Siemens STEP 7 V5.5 IDE, B&R Automation Studio 4
IDE, and Beckhoff TwinCAT 3 IDE
Simulink PLC Coder supports Siemens® STEP® 7 version 5.5, B&R Automation Studio®
4, and Beckhoff® TwinCAT® 3.
3-2
R2013b
Version: 1.6
New Features
Bug Fixes
R2013b
To see how mask parameters map to generated code, see Generated Code Structure for
Subsystem Mask Parameters.
• Global tunable parameters that are structures and array data types are initialized in
a PLC_INIT_PARAMETERS function block. For more information, see Global Tunable
Parameter Initialization for PC WORX.
• floor and ceil rounding is supported.
• Array type names incorporate data type description and size.
For example, if you have a 51-element array of real data, the generated code for the
array data type is:
PLC_ARRAY_0_50_LREAL: ARRAY [0..50] OF LREAL;
• Code generation header comments and block description comments are in the body of
the generated code, and are therefore visible when you import the code into the IDE.
4-2
Relative tolerance for test bench data comparison
When checking single and double data type values, the test bench now uses a relative
error tolerance. Integer data type comparisons in the test bench still use an absolute
tolerance.
To learn more about test bench data comparison, see How Test Bench Verification
Works.
4-3
R2013a
Version: 1.5
New Features
Bug Fixes
R2013a
To open an example that shows how to generate code from a multirate model, at the
command line, enter:
plcdemo_multirate
5-2
R2012b
Version: 1.4
New Features
Bug Fixes
R2012b
For Rockwell Automation RSLogix 5000 AOI/routine target IDEs, the coder also
generates the subsystem block description text as an AOI or routine description L5X
6-2
XML tag. The IDE can then import the tag as part of AOI and routine definition in the
generated code.
For more information, see Internal Signals for Debugging in RSLogix 5000 IDE.
6-3
R2012b
6-4
R2012a
Version: 1.3
New Features
Bug Fixes
R2012a
• Load the code generated from routines without first restarting the Rockwell
Automation RSLogix 5000 PLC. You can now:
• Take advantage of RSLogix user defined types (UDTs) to preserve model hierarchy in
routine code and represent model.
• Observe that reusable subsystems become separate routine instances and access
instance data in program UDTs.
• In the Configuration Parameters dialog box PLC Code Generation > Target IDE
parameter, the Rockwell RSLogix 5000 17, 18: Routine option was added.
• In the Configuration Parameters dialog box PLC Code Generation > Target IDE
parameter, the Rockwell RSLogix 5000 17, 18 option was changed to Rockwell
RSLogix 5000 17, 18: AOI. This renamed option continues to generate code for
Add-On instruction constructs, as in previous releases.
• In the command-line PLC_TargetIDE parameter, the rslogix5000_routine option
was added.
7-2
Support for Absolute Time Temporal Logic for the Rockwell Automation
RSLogix 5000 IDE
The Simulink PLC Coder software now supports absolute time temporal logic in
Stateflow charts for the Rockwell Automation RSLogix 5000 IDE. The coder does not
support absolute time temporal logic for other target IDEs.
Note: If your model uses absolute time temporal logic, you cannot create test bench code
for that model.
7-3
R2012a
New Examples
The following examples are new:
7-4
R2011b
Version: 1.2.1
New Features
Bug Fixes
Compatibility Considerations
R2011b
1 In the Configuration Parameters dialog box, clear the Generate testbench for
subsystem check box.
2 In the Simulink editor, right-click the subsystem and select PLC Code Generation
> Generate and Import Code for Subsystem.
In previous releases, the coder generated and imported test bench code into the target
IDE regardless of the setting of the Generate testbench for subsystem check box.
Compatibility Considerations
This release simplifies the function block code of the top-level subsystem for generated
code.
• If the top-level subsystem in the Simulink model has internal state, the generated
function block for the block will have an extra first parameter ssMethodType of
integer type. This extra parameter is in addition to the function block I/O parameters
mapped from Simulink block I/O ports.
1 Initialize the block by calling the function block with ssMethodType set to
integer constant SS_INITIALIZE.
2 If the IDE does not support symbolic constants, set ssMethodType to integer
value 0.
3 For each follow-up invocation, call the function block with ssMethodType set to
constant SS_STEP.
4 If the IDE does not support symbolic constants, set ssMethodType to integer
value 1.
8-2
These settings cause the function block to initialize or compute and return output for
each time step.
• If the top-level subsystem does not have internal state, the function block code has
only parameters mapped from Simulink block I/O ports. There is no ssMethodType
parameter. To use the function block in this case, call the function block with I/O
arguments.
For non-top-level subsystems, either with or without internal state, the function
block code has the ssMethodType parameter. The generated code might have other
ssMethodType constants to implement Simulink semantics.
New Demo
The following demo is new:
• Generating Structured Text for a Simple Simulink Subsystem without Internal State
— Illustrates changes for function block prototypes in generated code.
8-3
R2011a
Version: 1.2
New Features
Bug Fixes
R2011a
See Supported IDE Platforms in the Simulink PLC Coder User's Guide for more
information.
9-2
3 From the Approximation method parameter, select CORDIC.
4 Generate code for the atomic subsystem.
64-Bit Support
The Simulink PLC Coder product supports 64-bit systems. You can still use the Simulink
PLC Coder product with 32-bit IDEs.
See the MathWorks® website at Supported IDEs for a list of supported IDEs and
platforms.
New Demos
The following demos are new:
• Airport Conveyer Belt Control System — Illustrates code generated for an airport
conveyer belt.
• Generating Structured Text for Simulink Model with Fixed-Point Data Types —
Illustrates generating fixed-point code in the Simulink PLC Coder environment.
9-3
R2010b
Version: 1.1
New Features
R2010b
See Supported IDE Platforms in the Simulink PLC Coder User's Guide for more
information.
You can take advantage of this capability for the following PLC IDEs:
See Automatically Importing Structured Text Code in the Simulink PLC Coder User's
Guide for more information.
New Demo
A new Simulink PLC Coder demo, Speed Cruise Control System Using Simulink and
Stateflow, illustrates code generated for a cruise control controller subsystem using a
triggered subsystem.
10-2
R2010a
Version: 1.0
New Features
R2010a
New Product
Simulink PLC Coder generates hardware-independent IEC 61131-3 Structured Text
from Simulink models, Stateflow charts, and Embedded MATLAB® functions. The
Structured Text is generated in PLCopen and other file formats supported by widely used
integrated development environments (IDEs). As a result, you can compile and deploy
your application to numerous programmable logic controller (PLC) and programmable
automation controller (PAC) devices.
Simulink PLC Coder generates test benches that help you verify the Structured Text
using PLC and PAC IDEs and simulation tools.
Key features:
11-2
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