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    EEE 270 Advanced Topics in Logic Design: Lab - 1 Full Adder

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    Praveen Meduri
    This document provides instructions for a lab assignment to design and implement a 1-bit full adder using VHDL. The tasks include: 1) Understanding provided VHDL code for a full adder 2) Simulating the full adder design in ModelSim to verify functionality 3) Creating a Vivado project and adding the VHDL code and constraints files 4) Synthesizing, implementing, and generating a bitstream file 5) Programming the bitstream onto a Nexys4 DDR board and testing the full adder.

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    EEE 270 Advanced Topics in Logic Design: Lab - 1 Full Adder

    Uploaded by

    Praveen Meduri
    85 views6 pages
    This document provides instructions for a lab assignment to design and implement a 1-bit full adder using VHDL. The tasks include: 1) Understanding provided VHDL code for a full adder 2) Simulating the full adder design in ModelSim to verify functionality 3) Creating a Vivado project and adding the VHDL code and constraints files 4) Synthesizing, implementing, and generating a bitstream file 5) Programming the bitstream onto a Nexys4 DDR board and testing the full adder.

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    This document provides instructions for a lab assignment to design and implement a 1-bit full adder using VHDL. The tasks include: 1) Understanding provided VHDL code for a full adder 2) Simulating the full adder design in ModelSim to verify functionality 3) Creating a Vivado project and adding the VHDL code and constraints files 4) Synthesizing, implementing, and generating a bitstream file 5) Programming the bitstream onto a Nexys4 DDR board and testing the full adder.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    85 views6 pages

    EEE 270 Advanced Topics in Logic Design: Lab - 1 Full Adder

    Uploaded by

    Praveen Meduri
    This document provides instructions for a lab assignment to design and implement a 1-bit full adder using VHDL. The tasks include: 1) Understanding provided VHDL code for a full adder 2) Simulating the full adder design in ModelSim to verify functionality 3) Creating a Vivado project and adding the VHDL code and constraints files 4) Synthesizing, implementing, and generating a bitstream file 5) Programming the bitstream onto a Nexys4 DDR board and testing the full adder.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 6

    EEE 270 Advanced Topics in Logic Design

    Lab – 1 Full Adder

    SOFTWARE AND HARDWARE NEEDED


    Notepad ++, ModelSim from Altera (Now Intel), Vivado from Xilinx and NEXYS4 DDR board.

    PURPOSE
    The main purpose of this lab is to develop familiarity with the software and hardware tools used
    for this course. You will not write any VHDL code in this lab. You will run the code that is given
    to you and implement it on the NEXYS4 DDR board.
    As a running example, we will use a 1–bit Full Adder designed in VHDL.

    STARTER PROJECT
    Lab-1.zip. This folder contains 4 files that are necessary to start on the project.

    BACKGROUND
    A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full
    adder adds three one-bit numbers. The full adder used in this project has x, y, and C_in as three
    inputs: x and y are the input bits, and C_in is the input carry bit. The two outputs are S (for sum)
    and C_out (for Carry out).
    The working of the full adder is shown in the truth table below. The block diagram of a full
    adder is in Figure – 0.

    Table – 1. Full – Adder Truth Table

    C_in y x S C_out
    0 0 0 0 0 x S
    0 0 1 1 0
    0 1 0 1 0
    1 – Bit
    0 1 1 0 1
    y
    Full Adder
    1 0 0 1 0
    1 0 1 0 1
    C_out
    C_in
    1 1 0 0 1
    1 1 1 1 1
    Figure – 0: Full Adder
    TASKS
    (1) Open Full_Adder_2.vhd file with notepad++ and understand the VHDL code.
    (2) Create a ModelSim Library and successfully simulate a Full Adder. Verify the functionality
    of the code for the full adder using simulations.
    (3) Create a New Project in Xilinx Vivado and add the verified VHDL code file to the project
    (4) Edit the constraints file (Full_Adder_2_Nexys4DDR_Master.xdc) to map the design ports
    onto the pins of the Nexys 4 DDR board and add to the project in Vivado
    (5) Synthesize, Implement and Generate a (*.bit) file
    (6) Program the Board using the (*.bit) file you just created.
    (7) Verify functionality on the board by using different input patterns

    STEP BY STEP GUIDE


    1. Download and unzip the Lab-1 file to a USB drive. Pease use your own storage drive.
    2. Open Full_Adder_2.vhd file with notepad++ and understand the code. (Task – 1 Complete)
    3. Search for and open ModelSim on the lab computer (see Figure – 1)
    4. Click on File  Change Directory  browse to NEXYS4DDR directory  OK
    5. Click on File  New  Library  OK (see Figure – 2) (leave all fields as defaults)
    6. Click Tools  Tcl  Execute Macro  Full_Adder_2.tcl
    7. You should see simulations similar to Figure – 3 (You may need to press ‘f’ to fit all the
    simulations in one screen). Compare simulations to the truth table to verify correct operation.
    8. You can now close ModelSim (Task – 2 Complete)
    9. Search for and open Vivado on the lab computer (Not Vivado HLS or other programs)
    10. Click on File  New Project  Next  Project Name: Full_Adder_2 (see Figure 4)  Next
    11. Select RTL Project (On the Project Type Screen)  Next  Select the Target Language as
    VHDL  Next  Next
    12. Select the Default part as xc7a100tcsg324-1 (See figure – 5)  Next  Finish
    13. In the Sources window, right click on Design Sources  Add Sources …  Add
    Full_Adder_2.vhd file and finish. (Task – 3 Complete)
    14. In the Sources window, right click on Constraints  Add Sources …  Add
    Full_Adder_2_NEXYS4DDR.xdc file and finish.
    15. Understand the pin mapping in the Full_Adder_2_NEXYS4DDR.xdc file (look at the
    uncommented lines which do not have a # sign in-front of them.) (Task 4 Complete, no need
    to edit the xdc file for the first lab)
    16. On the left most pane of the Vivado window  Click on Run Synthesis and  OK
    17. When Synthesis Completes  Run Implementation
    18. When Implementation complete  Generate Bitstream (Task – 5 Complete)
    19. Connect the Nexys4DDR Board to the computer using the USB cable
    20. When Bitstream Generation completes  Open Hardware manager (On the left Panel) 
    Open Target  Open New Target
    21. Click Next  Select Local Server on the Hardware Server settings page
    22. Select the Xilinx part to open target
    23. In the Open Hardware Manager Pane on the left, click on Program Device.
    24. Select the Full_Adder_2.bit file and click on Program (Task – 6 complete)
    25. Verify the functionality of the Full Adder using the 3 right most switches and the 2 right
    most LEDs. Compare to the simulations and truth table. (Task – 7 complete)
    ACKNOWLEDGEMENTS
    The lab materials and the VHDL code have been provided by Jordan Christman.
    https://www.udemy.com/user/jordanchristman/

    Figure – 1: Model Sim Opening screen


    Figure – 2: New Library creation

    Figure – 3 a: Simulations on ModelSim

    Figure – 3 b: Closer look at the wave forms and signals in simulations


    Figure – 4: Vivado New project creation. Make sure “Create project subdirectory” is checked
    Figure – 5: Selecting the Xilinx part for the project

    Figure – 6: Adding Design source (Full_Adder_2.vhd) file

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