VLSI Qna
VLSI Qna
VLSI Qna
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Consider the time period of input clock is T. If the input clock is delayed by T/4 time period and if this
delayed clock along with original input clock is given to a combinational gate then one would see that
only XOR gate fits in, to produce output with double the frequency of input clock.
Answer) Combinatorial and Asynchronous
Q.3) What is the function of a D FF whose complemented output ( Qbar ) is connected to
its input,D. What is the maximum clock frequency that can be used for it?
Answer) Suppose that there was some value at the output Q('0') of the flip flop, so when rising edge of
clock comes, it samples the inverted value of output and retains it until next clock. When next rising
edge comes, flop samples inverted value of output and so on. This behaviour of circuit shows that
output will be half of the clock.
AND gate,
A and B = C; A and C = B
Replacing value of B in first equation,
A and (A and C) = C ---> This is again false, hence AND is not the answer.
XOR gate,
A xor B = C; A xor C = B
Replacing value of B in first equation,
A xor (A xor C) = C,
A xor (A.not(C) + C.not(A)) = C,
A.not(A.not(C) + C.not(A)) + not(A).(A.not(C) + C.not(A)) = C,
A(not(A).not(C) + A.C) + not(A).C = C,
0 + A.C + not(A).C = C,
C = C, -----> This is true, hence XOR is the answer
These type of questions are usually solved using hit and trial method.
Unknown at 21:50
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