GaN Power Device Tutorial Part2 GaN Driving

2
GaN Power HEMT Tutorial:

GaN Driving
GANPOWER INTERNATIONAL INC
Fred Yue Fu （傅玥）

Co-founder and COO
GaNPower International Inc.
© Fred Yue Fu (傅玥), GaNPower International Inc.

Contents
Ø Session 1: GaN devices basics
Ø Session 2: GaN Gate Driving
Ø Gate driving basics

Ø High dv/dt and di/dt issues
Ø Gate drivers and isolation
Ø Gate drive related power loss calculations
Ø Co-package and monolithic GaN IC
Ø Session 3: GaN Applications
© Fred Yue Fu (傅玥), GaNPower International Inc. 2

Gate Driving: Turn-on
Miller
Plateau

Gate Driving: Turn-off
Miller
Plateau

Gate Driving: Non-ideal case
Caused by Caused by Id
Id overshoot undershoot
A portion of the Ids

has to charge COSS
Qrr from the other transistor
(for cascode) and charging
current for COSS (QOSS)
Drain leakage Drain leakage

inductance induced inductance induced
(VD-L*di/dt) (VD+L*di/dt)
Non-linearity of COSS

Gate Driving: Switching Loss
Qgs1 Qgs2 Qgd Qgd Qgs2 Qgs1
Qgs2+Qgd Qgs2+Qgd
Turn-on-Loss Turn-off-Loss

Gate Driving: Soft and Hard-switching Turning-on
ZVS
No Miller
Plateau
Current Slope Determined

by the Inductor
Coss Discharge

Gate Driving: Turning-off with Strong Driver
Ø ZVS provides soft-switching at turning-

on, but turning-off is still hard
switching
Ø A strong driver increases switching

speed, reduces switching time and
switching losses
Ø For a strong driver turn-off, Miller

plateau may not be observed. This is Charging Coss
exactly what we have seen when
switching GaN devices off
Non-linear Coss
Ref: Wei Zhang, Mastering the art and fundamentals of high

voltage gate driver; TI High Volt Interactive

Gate Driving: Parasitic Inductance
GaN Chip
Bonding-wire
Inductance
~0.5 nH
Lead Inductance
~10 nH

Gate Driving: Kelvin Source
Some device packaging types, such as DFN, have kelvin source pins,
properly connecting the kelvin source to the drive loop will minimize the
common source inductance (CSI)
Power Loop
DFN8x8
VDD
PMW
Gate Driver
Input
Drive Loop
?
GND

Gate Driving: Parameters that affect switching loss
Ø Gate resistance Rg
Ø Gate to source capacitance CGS
Ø Gate to drain capacitance CGD
Ø Drain to source capacitance CDS
Ø ….

Gate Driving: Rg
Turn-on Turn-off
Rg↑:
Ø dv/dt ↓
Ø di/dt ↓
Ø Reduces switching speed
Ø Increase switching loss

Gate Driving: Rg (Experimental)
E-mode GaN in DFN Package
ü Rg limits the gate charging and discharging current and reduces dv/dt and di/dt slew rate
ü Larger Rg will increase switching loss, especially for turn-off
ü A properly selected Rg can mitigate the EMI issue that stems from high switching speed
Source: X. Huang, T. Liu, B. Li, F. C. Lee, and Q. Li, "Evaluation and applications of
600V/650V enhancement-mode GaN devices," 2015 WiPDA

Gate Driving : Rg Design Considerations
Trade off between fast switching and ringing
Ø Equivalent RLC circuit for voltage driven topology:
Ø Small RG ↓ ⇒ fast switching ↑ ⇒ large ringing ↑

Ø Large RG ↑ ⇒ slow switching ↓ ⇒ small ringing ↓
Ø Ringing causes Conducted Electromagnetic Interference (CEMI)
4(𝐿# + 𝐿) )
𝑅# ≥
𝐶#)
http://www.electronicdesign.com/power/take-practical-path-toward-high-performance-power-conversion

Gate Driving : Rg Design Considerations
Ø To avoid ringing, with certain LG, LS and CGS, RG can be calculated as:
For GPI65015DFN with CGS = 119 pF

4(𝐿# + 𝐿) )
𝑅# ≥
𝐶#)
LG+LS (nH) RG (Ω)
0 0
1 5.8
2 8.2
3 10.0
4 11.6
http://www.electronicdesign.com/power/take-practical-path-toward-high-performance-power-conversion

Gate Driving: CGS
Turn-on Turn-off
CGS ↑:
Ø dv/dt -
Ø di/dt ↓
Ø CGS mostly affects the
current rising and
falling period
Charging CGS -> di/dt

Gate Driving: CGD
Turn-on Turn-off
CGD ↑:
Ø dv/dt ↓
Ø di/dt -
Ø CGD mostly affects the
drain rising and falling
period during the
Miller plateau
Charging CGD -> dv/dt

Gate Driving: Adding External CDS
Ø Adding external CDS capacitance

does not reduce dv/dt at turn-on
Ø When the device turns on, at Miller

plateau, drain voltage drops from
VD to 0
Ø dv/dt is governed by the Cgd and
discharging current Igd from the
gate driver
Ø Paralleling external capacitance to

Cds doesn’t impact dv/dt at turn-on,
but it will add extra channel current
ICDS that increases switching loss for
hard-switching At Turn-on

Gate Driving : Adding External CDS
Ø When the device turns off, at Miller

plateau, drain voltage rises from 0 to VD
Ø IDS from the drain is diverted into three
parts: Igd for charging CGD, ICDS for
charging CDS and the rest goes through
the channel (Ichannel)
Ø dv/dt at turning-off is governed by CGD

and CDS. Increasing CDS will reduce dv/dt,
especially if Ichannel is relatively small
Ø ICDS will divert the current in the channel

and reduces switching loss at turn-off
(but increases turning-on loss at the same
time for hard switching)
At Turn-off
Ø If paralleling CDS is required to improve
EMI, the value should be large enough so
that the dv/dt rate at turn-off can be
modulated

Contents
Ø Session 2: Gate Driving


High dv/dt Effect
Ø High dv/dt charges parasitic capacitances. CDS High dv/dt Event
is charged during this period, as well as the
series connected CGD and CGS GaN
Ø If the VGS gets higher than Vth due to CGS
Keep VG<Vth
charging, the device unintentionally switches
on, which will lower overall efficiency. This is Gate
called Miller turn-on Driver
Ø A by-pass can divert the current that flows
through Miller capacitance to avoid false turn-
on
Ø Miller ratio （ QGD/QGS1 ） can be used to

determine how fragile the devices are due to
Miller false turn-on. If the ratio smaller than 1, High dv/dt path
the device is guaranteed no false turn-on,
However, many commercial devices cannot + + + +
keep the ratio below 1
Ø Miller ratio also depends on applied Vds, since Miller ratio + +
Qgd is a function of Vds. Higher Vds yields larger (from EPC)

Qgd and thus more sensitive to dv/dt
++ ++
Alex Lidow Johan Strydom Michael de Rooij David Reusch, GaN TRANSISTORS FOR EFFICIENT POWER CONVERSION, Wiley

GaN Device dv/dt issue: no pull-down path
With no pull-down current from external driver：
CBD
VBC = VDC
CBC + CBD
In order to maintain VBC < VFG so

that GaN device won’t suffer from
false turn-on, the maximum VDS
can be calculated as：
CBC + CBD
VDC,IJK ≤ VFG
CBD
The calculated VDC,IJK value can be

quite small
Texas Instruments: Estimating MOSFET Parameters from the Data Sheet

GaN device dv/dt Issue: The intrinsic dv/dt limit
If the external driver resistance is 0, which means G and S are shorted, this is
to calculate the intrinsic dv/dt limit
dVDC
CBD R ≤ VFG
dt B,O
dVDC VFG
⟹ Y ≤
dt IJK CBD Z R B,O
For example：CBD = CPQQ = 4 pF (@VDS = 400V); CBC = CSQQ − CPQQ = 123 − 4 =

119 pF (@VDS = 400V); R B,O = 1.5Ω
dVDC VFG 1.41V

Y ≤ = = 235V/ns
dt IJK CBD Z R B,O 4pF×1.5Ω

GaN device dv/dt issue: A practical design
In a practical design, with external gate resistance RGATE and driver resistance RLO
dVDC
CBD (R B,O +R B`Fa + R bc) ≤ VFG
dt
dVDC VFG
⟹ Y ≤
dt IJK CBD Z (R B,O +R B`Fa + R bc)
For example：CBD = CPQQ = 4 pF; CBC = CSQQ − CPQQ = 123 − 4 = 119 pF; R B,O = 1.5 Ω; with
gate driver from TI UCC27611: R bc = 0.35 Ω; and assume R B`Fa = 0.5 Ω and @VDS=400V
dVDC VFG 1.41V

⟹ Y ≤ = = 150V/ns
dt IJK CBD Z (R B,O +R B`Fa + R bc) 4 pF Z 1.5Ω + 0.35 Ω + 0.5 Ω
Low impedance turn-off drive-loop is critical for designs with GaN due to high dv/dt,
especially for 650V devices
GaN device dv/dt issue: A more comprehensive approach
A more comprehensive analysis was done by a group of researchers at Virginia Tech
for MOSFET before, and it can be applied to GaN as well
Besides Cgd, other parasitic components

such as Ld, Ls, Cgs and Cds all play a role in
spurious turn-on by high drain dv/dt
This is another reason why we should

have lower parasitic inductance
dVDC VFG
Y ≤
dt IJK 1 RfdQ
Cde R dQ + Cde ( − ) (Le + LQ )(Cde + CeQ )
CdQ 4Ld
Yuming Bai, Deva Pattanayak*, Alex Q. Huang, Analysis of dv/dt Induced Spurious Turn-on of MOSFET, Virginia Tech

GaN dv/dt issues: High Side
p With high positive and negative

dv/dt slew rate of GaN, the
common mode current can flow
through the level-shifter or
isolator of the high side switch
p It can cause ground bounce

within the level shifter and even
change logic states
p A smaller parasitic capacitance

from the level-shifter or isolator is
desirable, which will give a higher
CMTI (common mode transient
immunity)

GaN vs. SJ MOS in terms of dv/dt
Ø GaN has much higher dv/dt and di/dt than SJ MOS, special designs are
necessary and drivers with high CMTI (Common mode transient immunity) is
necessary
Wei Zhang, A Deep Dive of Isolated Gate Driver Robustness – dv/dt (CMTI) and di/dt, TI, APEC 2018

Common Source Inductance（CSI）and di/dt issues
p The common source inductance (CSI) is

shared by the power loop and the drive loop
p Voltage across the CSI will be induced by the

high current slew rate di/dt during switching
period
p During device turn-on, this voltage

counteracts with the voltage on the gate and
elongates the turn-on time Without Kelvin Source With Kelvin Source
p During device turn-off, this voltage increases Type LG (nH) LS (nH) LD (nH)
the gate voltage, delays the turn-off time
TO220 3.6 3.9 2.3
and causes ringing and false turn-on
DFN 2.4 0.9 1.3
p This negative feedback brings longer
voltage-current overlap and increases
switching loss
p A Kelvin pin is generally required to separate

GaNPower GaNPower
power and driving loop DFN 8x8
TO220
Xiucheng Huang, Tao Liu, Bin Li, Fred C. Lee, and Qiang Li Evaluation and
Applications of 600V/650V Enhancement-Mode GaN Devices , 2015 WiPDA

Ground Bounce
p If controller ground is tied to the

power ground, the controller
logic might be affected by the
voltage pulses on the CSI (created
by large high voltage slew rates
across capacitors that generates
large current pulses of short
duration), which is called ”ground
bounce”
p Ground bounce can alter the

normal device switching and lead
to unwanted device behaviors
p One way to mitigate this issue is

to tie the controller ground to the
driver ground
Alex Lidow Johan Strydom Michael de Rooij David Reusch, GaN

TRANSISTORS FOR EFFICIENT POWER CONVERSION, Wiley

DFN vs. TO220 GaN in Hard-Switching (CSI Issue)
Turn-on transition
Turn-off transition
Ø CSI affects di/dt, not dv/dt Ø For turn-off, there is no voltage transition delay,
since voltage rises before current falls
Ø For turn-on, a lower di/dt can be observed for
TO220 with CSI and no kelvin pin (due to Ig↓) Ø di/dt rate is not much different, since most of
the current transition we observed are for Coss
Ø Voltage transition is postponed due to charging
increased current transition time
Ø However, a severe ringing occurred in TO220
Ø Higher Eon loss for TO220 that may indicate a false turn-on. Eoff loss is
higher for TO220
Xiucheng Huang, Tao Liu, Bin Li, Fred C. Lee, and Qiang Li; Evaluation and Applications of 600V/650V Enhancement-Mode GaN Devices, 2015 WiPDA

Gate Driving: Bootstrap
Ø If a bi-polar gate voltage (negative for turning-off ) is applied, Vsd for GaN
devices can be quite large (several Volt)
Ø Bootstrap capacitor can be over-charged to cause damage to upper GaN

switch
Bootstrap Cap Charging 𝑉ijk = 𝑉ll − 𝑉mnomp + 𝑉qm

Contents


Gate Voltage Requirements
Si-MOS Si-IGBT SiC-MOS GaN
Vds Ratings 20~650V ≥650V ≥650V ≤1200V
Optimal Vgs 0~+15V -10~+15V -5~+20V -5~+6V
Max Vgs ±20V ±20V -10~+25V -10～+7V

Commercial Discrete 650V E-Mode GaN Driver Examples
Pull-up / Pull-
Configur Sink / VDD Supply Propagation
GaN Drivers Vendor Gate Drive Voltage down
ation Source Voltage Delay
Resistance
Single- 7.6A /
LM5114 TI 4~12.6V ~VDD 2Ω /0.23Ω 12ns
Sided 1.3A
Single-
UCC27611 TI 4A /6A 4~18V 5V 1Ω /0.35Ω 14ns
Sided
Single-
UCC27517 TI 4A/4A 4.5~18V ~VDD 5Ω /0.5Ω 13ns
Sided
Maxim Single-
MAX5048C 7A /3A 4~14V ~VDD 0.84Ω /0.3Ω 8ns
Integrated Sided
Fairchild / Single- 9.7A
FAN3122 4.5V to 18V ~VDD NA 20ns
ON-Semi Sided /7.1A
Single-
Si8271 Silicon Lab 4A /4A 4.2V to 30V ~VDD 2.7Ω /1Ω 60ns (max)
Sided
Half-
Si8273 Silicon Lab 4A /4A 4.2V to 30V ~VDD 2.7Ω /1Ω 60ns (max)
bridge
Half-
NCP51820 ON 2A/1A 9V to 17V 5.5V N/A 25ns
Bridge

Isolated Gate Driving
In order to meet IEC 61010 isolation requirement, three types of isolated gate driving are
available:
Gate Isolation with Transformer

Gate Isolation with Digital Isolator
Transformer Iso Digital Isolator Isolated driver

Prop. Delay 20 ns 100 ns 19 ns (Typical)
Bias Power No Yes Yes
CIO ≥10 pF <1 pF <1 pF
Parasitics Large Llk Very Small Very Small
Overshoot Large Small Small
Size Bulky Small Very Small
Isolated Gate Driver
Source: Wei Zhang, Mastering the art and fundamentals of high voltage gate driver; TI High Volt Interactive

Half Bridge Gate Driver : Isolated and Non-Isolated
A typical non-isolated gate driver from TI
Isolated gate driver such as Si8273 provides:
ü 200 kV/μs CMTI A typical isolated gate driver

ü 2.5 kV RMS withstand voltage from Silicon Lab for GaN
ü Input supply: 2.5–5.5 V
ü Driver supply: 4.2–30 V (6V for E-mode GaN)
ü Prop. Delay: 60 ns (max)
UCC27714High-Speed, 600-VHigh-SideLow-SideGateDriver with 4-A Peak Output

https://www.silabs.com/documents/public/data-sheets/Si827x.pdf

Digital Isolation Technology: Magnetic Isolator
Magnetic isolator is based on chip-scale transformers, compared to optocoupler, magnetic couplers
use low-stress, thick-film polyimide insulation to achieve thousands of volts of isolation that can be
monolithically integrated with standard silicon ICs and can be fabricated in single-channel, multi-
channel, and bidirectional configurations
ü 4x improvement in data rate and timing specifications

ü Integrates multiple isolation channels with other functions to reduce size and cost
ü Operates at power levels up to 90% lower than optocouplers
ü Minimizes external components needed to connect to other digital devices
ü Increases reliability by eliminating LEDs used in optocouplers
Ref: Analog Devices: Standard Digital Isolators

Digital Isolation Technology: Capacitive Isolator
Capacitive isolation is made by adding capacitive isolation barrier on top of each die to
connect in series, digital circuits are used for encoding and decoding various signals
through the isolation barrier. A capacitive isolator ’s inability to pass DC signals makes it
inherently the right choice for isolation
TI’s capacitive isolation barrier is made

from layers of high-dielectric SiO2 Silicon Lab’s capacitive isolation solution
1, Capacitive Isolation: The Future AC/DC Power Conversion, Monolithic Power Systems
2, https://www.silabs.com/documents/public/data-sheets/Si827x.pdf
3, TI: Digital Isolators

Isolation Technology: Comparison
Independent Reliability
dv/dt Propagation power supply (over time &
Isolation Integration level Cost
immunity delay needed at the harsh
secondary environment)
Optocouplers Few kV >50kV/µs >400ns Medium Yes Aging issues $
Several 10’s Good
Fiber optic >100kV’s/µs Negligible Medium Yes $$$$
kV reliability
Monolithic Integrated on
None 50kV/µs - No - $
level shifter the IC
Pulse
Several kV >50kV/µs <100 ns Bulky No Reliable $
transformer
Integrated on-
Digital
Several kV >100kV/µs ~20 ns chip or driver IC Yes Very reliable $$
isolation
package
Optical Magnetic Capacitive
Chip Integrated Isolation

Source:
Gate Drivers market evolution: coreless isolation
and WBG specific solutions, Yole Development,
APEC 2018

Choosing GaN Gate Driver and Rg
Ø If possible, gate drivers with individual

turn-on and turn-off pins are
recommended
Ø Use separate drive loops for turn-on

and turn-off. Turn-off loop low
impedance is recommended to avoid
false turn-on and oscillations
Ø Proper selection of Rg-on vs. Rg-off is

critical. Normally the ratio of Rg-on to Rg-
off can be chosen between 5 to 10
*Source: GN001 Application Guide: Design with GaN Enhancement mode HEMT, GaN Systems

Current-source and Voltage-source Gate Drivers
Current-source gate driver Voltage-source gate driver

Ø Current sources have a high resistive output Ø Voltage sources shall be as low resistive as
by default possible
Ø Any additional voltage drop in the gate Ø Any additional voltage drop in the gate
drive loop has no influence on the gate drive loop has immediate influence on the
current Ig inside limits gate current Ig
Ø Supposed to damp oscillations Ø Prone to oscillations
Ref: Turn-on performance comparison of current-source vs. voltage-source gate drivers, Infineon, APEC 2018

Contents


GaN Device Power Loss Analysis
Ø Conduction Loss:
PCond=ID2・Rdson ・ D (D: Duty Cycle)
GaN Power Loss Chart
Ø Switching Loss:
PSwitching=1/2 ・ ID ・ VD ・ (ton+toff )・ fsw
Ø Gate Driving Loss:

PDriving=Vg ・ Qg ・ fsw
Ø Power Loss from Coss Conduction Loss Switching Loss Gate Driving Loss
PCOSS=EOSS ・ fsw

GaN Gate Driving Loss
With same gate driver, soft-switching

such as ZVS has a lower turn-on gate
driving loss than hard-switching:
𝑃sjtp_mv_ow = 𝐸ow_qoyt Z 𝑓q{ = 𝑉sq Z 𝑄sow_qoyt Z 𝑓q{
𝑃sjtp_mv_ow = 𝐸ow_}jvm Z 𝑓q{ = 𝑉sq Z 𝑄sow_}jvm Z 𝑓q{
Wei Zhang, Mastering the art and fundamentals of high voltage gate driver; TI High Volt Interactive

GaN vs. SJ MOS: Qrr and Qoss Loss
SJ MOSFET with Qrr from body- GaN HEMT with Qoss from other GaN
diode and Qoss
Peter Di Maso, Lucas Lu, GaN E-HEMTs Enable Innovation in Power Switching Applications, GaN Systems, APEC 2017

GaN Device Power Loss Analysis: Hard-Switching
Ø With same Rdson and same frequency, GaN power loss vs. Si:
𝑃}jvm_)~ = 𝑃iowm + 𝑃q{ + 𝑃ioqq + 𝑃sjtp + 𝑃qm + 𝑃vv
SJ MOS GaN Remark

Pcond same same Same Rdson
Psw higher lower Due to GaN has smaller QGS2 and QGD
Pcoss higher lower GaN has a lower Coss
Pgate higher lower GaN has lower gate drive voltage
Psd lower higher GaN has a higher Vsd
Prr higher none GaN has no Qrr
Phard_sw higher lower GaN has a lower total hard switching power loss

Contents


Si Driver + GaN Co-package
PARAMETER TEST CONDITION MIN TYP UNIT

GPI65030CO: double-pulse test, rising
VDD (VDD operating voltage TJ) range of 40°C to 125°C
MAX
5 V
edge of second pulse (turn-on @
VDD under voltage
lockout VDD Rising Tj=25°C 3.8
second pulse). Yellow: Drain to Source
UVLO V Voltage; Blue: Drain to Source Current
VDD undervoltage lockout hysteresis 0.2
IDD VDD quiescent IN=INB=0 Tj=25°C 0.01 mA PARAMETER TEST CONDITION (VDD=5V) MIN TYP UNIT
MAX
current
tR Rise time CL=1nf 5 ns
N-CHANNEL OUTPUT tF Fall time CL=1nf 3 ns
Ron-N (Driver output resistance- VDD = 5V, IN-OUT = –100mA 0.25 tD-ON turn-on propagation Tj=25°C 17
pulling down) delay CL=1nf (TJ) range ns
of 40°C to 12.9
IPK-N peak sink current CL = 10,000 pF 5 A 20
P-CHANNEL OUTPUT 125°C
tD-OFF turn-off propagation Tj=25°C 15.7
Ron-P (Driver output resistance- VDD = 5 V, IN-OUT = 50 mA 2.1 delay CL=1nf (TJ) range ns
pulling up) 13.5
of 40°C to
IPK-P peak source current CL = 10,000 pF 1.3 A 18
125°C
GPI65030CO: Si driver basic parameters GPI65030CO: Si driver dynamic parameters

Si Driver + GaN Co-package: D-Mode GaN
A smart gate driver IC for cascode D-GaN (By University of Toronto)
ü Desired functions include
ü Tunable output resistance
ü Precise timing control
ü Current sensing for regulation and protections purposes
ü Dynamic driving techniques

ü Change gate driving strength during switching
ü Fully integrated controller circuits

ü Flexible digital control
ü Active driving ability under different load conditions
Jingshu Yu, Weijia Zhang, Andrew Shorten, Rophina Li and Wai Tung Ng, A Smart Gate Driver IC for GaN Power Transistors; ISPSD 2018

Si Driver + GaN Co-package: D-Mode GaN
VCC
SEG[3]
GaN
DRAIN SEG[2] large
CLK SEG[1] V CC
EN Current SEG[0]
ADC D SEG_EN
DRAIN
Sensing Rout
HOLD Stack DYN_OFF small
RESET CPU Hybrid Gating

t0 t1 t2 DYN_ON Level
VG
DELAY-LINE DELAY-LINE DELAY-LINE Shilfter large
MOSI DPWM Signal DELAY-LINE DELAY-LINE DELAY-LINE &
Gate DYN_ON Pre-driver
MISO Configuration Bits
Driver DYN_OFF
small
SEG_EN
On-chip Digital Controller Segmented Gate Driver Programmable sense-FET
+ =
10X D-Mode GaN by GaNPower

Smart Gate Driver IC
Jingshu Yu, Weijia Zhang, Andrew Shorten, Rophina Li and Wai Tung Ng, A Smart Gate Driver IC for GaN Power Transistors; ISPSD 2018

Si Driver + GaN Co-package: E-GaN and SenseFET
A novel SenseFET by GaNPower helps researchers from University of Toronto
won the prestigious 2019 IEEE ISPSD Charitat Young Researcher Award
Integrated GaN SenseFET

GaNPower SenseFET GaN, in collaboration with University
of Toronto
Source: W.J. Zhang, Y.H. Leng, J.S. Yu, Y.S. Lu, C.Y. Cheng and W.T. Ng, A Gate Driver IC for
Enhancement Mode GaN Power Transistors with Precise Dead-time Correction, ISPSD 2019

Si Driver + GaN Co-package: E-GaN and SenseFET
GP16501510 as HS and LS Provided by GaNPower
Ø The SenseFET from GaNPower is rated at 100V/20mΩ with two extra leads for the sensing gate and sensing source
Ø The current of the sensing source is designed to have a small match ratio while providing accurate sensing.
However, the novelty is to use the SenseFET in a voltage clamping circuit to detect reverse conduction of the e-
mode GaN low side output device while protecting the detection circuit from the high voltage swing at the
switching node
Ø The duration of this reverse conduction is then corrected by adjusting the dead-time in the following switching
cycle to ensure optimum power conversion efficiency
Ø The GaN SenseFET is conveniently packaged in an 8×8 8-lead DFN package
Source: W.J. Zhang, Y.H. Leng, J.S. Yu, Y.S. Lu, C.Y. Cheng and W.T. Ng, A Gate Driver IC for
Enhancement Mode GaN Power Transistors with Precise Dead-time Correction, ISPSD 2019

Si Driver + GaN Co-package: TI Direct-Drive
Direct-drive looks like a cascode method, in The voltage slew rate can exceed
which a low voltage MOS is in series with high 100V/ns
voltage D-mode GaN. The difference is that TI
integrates the driver IC to drive the GaN directly,
while the low voltage MOS is used to make the
package normally-off
Source: LMG341xR070 600-V 70-mΩ GaN with Integrated

Driver and Protection. TI datasheet

GaN IC, is it the future?
ü Currently, mainstream GaN technology is using 6-inch wafer with 0.5um feature
size
ü This roughly equals to the silicon lateral BCD technology used 20 years ago
ü GaN IC doesn’t have P-type HEMT, due to ion-implantation of p-type materials

such as Mg and subsequent thermal anneal very difficult to handle
ü Instead, GaN IC is either using Direct-Coupled FET Logic (DCFL) with both E-mode
and D-mode devices, or just use D-mode devices in the IC design
ü Resistors, capacitors are available in GaN IC, much like 20 years ago in silicon BCD
technology
Panasonic GaN IC
• GaN-based Semiconductor Devices for Future Power Switching Systems; Hidetoshi Ishida, Ryo Kajitani,
Yusuke Kinoshita, Hidekazu Umeda, Shinji Ujita, Masahiro Ogawa, Kenichiro Tanaka, Tatsuo Morita,
Satoshi Tamura, Masahiro Ishida and Tetsuzo Ueda; IEDM 2016
• Navitas APEC 2019 Industry paper

ü Both active devices, such as high voltage and low voltage D-mode
and E-mode HEMT are available
ü Passive components, such as GaN-FET-based rectifiers, MIM

capacitors and 2DEG resistors are available for analog functions
Source: Kevin J. Chen, Oliver Häberlen, Alex Lidow, Chun lin Tsai, Tetsuzo Ueda, Yasuhiro Uemoto and Yifeng Wu, GaN-on-Si
Power Technology:, Devices and Applications IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 3, MARCH 2017

Ø One of the first published monolithically integrated GaN IC design with two
generations using directly-coupled FET Logic that combines both D-mode and E-
mode transistors
Source: Gaofei Tang1, M.-H. Kwan2, Zhaofu Zhang1, Jiabei He1, Jiacheng Lei1, R.-Y. Su2, F.-W. Yao2, Y.-M. Lin2, J.-L. Yu2, Thomas Yang2, Chan-
Hong Chern2, Tom Tsai2, H. C. Tuan2, Alexander Kalnitsky2, and Kevin J. Chen1, High-Speed, High-Reliability GaN Power Device with Integrated
Gate Driver; Proceedings of the 30th International Symposium on Power Semiconductor Devices & ICs May 13-17, 2018, Chicago, USA

Numerous design has been reported for GaN IC, including simple logic functions such as
NAND, NOR and comparators
GaN integrated ESD protection circuit (<2% area) An over-voltage-protection (OVP) function
integrated to the gate of the power device on offered by GaNPower provides gate voltage
the GaN power device platform. Human body protection by clamping gate voltage below
model ESD voltage on the gate can exceed 5 kV required maximum gate voltage of GaN when
from −45 °C to 150 °C the driver output exceed the maximum

GaN integrated pre-gate driver (<5%

area) integrated with a 120-mm E-mode
GaN power device. Integration of
devices shortens parasitic paths and
thus achieves low ringing, short rise (8.5
ns) and fall (2.5 ns) time, and higher
switching speed
Need more detailed analysis from the application side to fully compare the
benefits and drawbacks of using either monolithically integrated GaN solution
or Si driver + GaN solution

IMEC is offering GaN IC for MPW (multi-project-wafer) based on their GaN-on-SOI epitaxy.
They have also demonstrated first high-side/low-side GaN-IC on chip with perfect isolation
Source: https://www.imec-int.com/en/200mm-GaN-on-Si-technology

(From Yole Development with modifications). Gate Drivers market evolution: coreless isolation and WBG specific solutions,
Yole Development, APEC 2018

While monolithic integration provides ultimate performance and eliminates on-board
parasitics, silicon IC + GaN co-package can still provide more comprehensive
functionalities -- at least for now
Dead Time Short Circuit

Control Protecion
di/dt and dv/dt Over Current
Control Protection
Over
EMI
Temperature
Suppression
Smart Gate Protection
Switching
Power Loss
Driver Over/Under
Voltage
Control Protection
Parallel
Current Self Diagnosis
Ballancing Current Sensing/ Temperature
Regulation Sensing
Switching Behavior Control Protection Monitoring/Regulation
Ref: Design Trends in Smart Gate Driver ICs for Power MOSFETs and IGBTs, ASICON 2017

GaNPower Future Integrated Modules
Integrated Power Module

THANKS FOR WATCHING!
Contact us （Vancouver Headquarters）:
230-3410 LOUGHEED HWY VANCOUVER, BC, V5M 2A4 CANADALGA
1.778.588.1119
information@iganpower.com
联系我们 ( Greater China Region )
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+86-512-65267027
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GaN Power Device Tutorial Part2 GaN Driving

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GaN Power Device Tutorial Part2 GaN Driving

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2

GaN Power HEMT Tutorial:

GANPOWER INTERNATIONAL INC

Fred Yue Fu （傅玥）

© Fred Yue Fu (傅玥), GaNPower International Inc.

Ø Session 2: GaN Gate Driving

Ø Gate driving basics

Ø Session 3: GaN Applications

© Fred Yue Fu (傅玥), GaNPower International Inc. 2

© Fred Yue Fu (傅玥), GaNPower International Inc. 3

© Fred Yue Fu (傅玥), GaNPower International Inc. 4

A portion of the Ids

Drain leakage Drain leakage

© Fred Yue Fu (傅玥), GaNPower International Inc. 5

Qgs1 Qgs2 Qgd Qgd Qgs2 Qgs1

© Fred Yue Fu (傅玥), GaNPower International Inc. 6

Current Slope Determined

© Fred Yue Fu (傅玥), GaNPower International Inc. 7

Ø ZVS provides soft-switching at turning-

Ø A strong driver increases switching

Ø For a strong driver turn-off, Miller

Ref: Wei Zhang, Mastering the art and fundamentals of high

© Fred Yue Fu (傅玥), GaNPower International Inc. 8

© Fred Yue Fu (傅玥), GaNPower International Inc. 9

© Fred Yue Fu (傅玥), GaNPower International Inc. 10

Ø Gate to source capacitance CGS

Ø Gate to drain capacitance CGD

Ø Drain to source capacitance CDS

© Fred Yue Fu (傅玥), GaNPower International Inc. 11

© Fred Yue Fu (傅玥), GaNPower International Inc. 12

ü Larger Rg will increase switching loss, especially for turn-off

© Fred Yue Fu (傅玥), GaNPower International Inc. 13

Ø Equivalent RLC circuit for voltage driven topology:

Ø Small RG ↓ ⇒ fast switching ↑ ⇒ large ringing ↑

Ø Ringing causes Conducted Electromagnetic Interference (CEMI)

© Fred Yue Fu (傅玥), GaNPower International Inc. 14

For GPI65015DFN with CGS = 119 pF

© Fred Yue Fu (傅玥), GaNPower International Inc. 15

Charging CGS -> di/dt

© Fred Yue Fu (傅玥), GaNPower International Inc. 16

Charging CGD -> dv/dt

© Fred Yue Fu (傅玥), GaNPower International Inc. 17

Ø Adding external CDS capacitance

Ø When the device turns on, at Miller

Ø Paralleling external capacitance to

© Fred Yue Fu (傅玥), GaNPower International Inc. 18

Ø When the device turns off, at Miller

Ø dv/dt at turning-off is governed by CGD

Ø ICDS will divert the current in the channel

© Fred Yue Fu (傅玥), GaNPower International Inc. 19

Ø Session 2: Gate Driving

Ø Gate driving basics

Ø Session 3: GaN Applications

© Fred Yue Fu (傅玥), GaNPower International Inc. 20

Ø Miller ratio （ QGD/QGS1 ） can be used to

keep the ratio below 1

Ø Miller ratio also depends on applied Vds, since Miller ratio + +

Qgd is a function of Vds. Higher Vds yields larger (from EPC)

© Fred Yue Fu (傅玥), GaNPower International Inc. 21

In order to maintain VBC < VFG so