NBKR Institute of Science & Technology:: Vidyanagar
NBKR Institute of Science & Technology:: Vidyanagar
1 17EC1101 4 - - 4 2 40 2 40 3 60 100
Digital System Design
Advanced Digital Signal
2 17EC1102 4 - - 4 2 40 2 40 3 60 100
Processing 0.8*Best of
Embedded System 2 mids +
3 17EC1103 4 - - 4 2 40 2 40 0.2*other 3 60 100
Concepts
mid
Coding Theory and
4 17EC1104 4 - - 4 2 40 2 40 3 60 100
Techniques
6 Elective -I 4 - - 4 2 40 2 40 3 60 100
PRACTICALS
Day to Day
Digital System Design Evaluation(30) + a
7 17EC11P1 - - 3 2 Day to Day Assessment 40 test(10)=(40 3 60 100
Lab
Marks)
Continuous
Periodical Review and Internal
8 17EC11P2 Seminar-I - - 4 2 100 Assessment - - 100
Seminar (100)
TOTAL 24 - 07 28 - - - - - - 800
M.Tech. (DECS) - I YEAR I SEMESTER: 2017-2018
LIST OF SUBJECTS
S. Hours/
Subject Code Subject
No. Week
1 17EC1101 Digital System Design 4
2 17EC1102 Advanced Digital Signal Processing 4
3 17EC1103 Embedded System Concepts 4
4 17EC1104 Coding Theory & Techniques 4
5 17EC1105 Transform Techniques 4
6 ELECTIVE- I 4
LABORATORY:
17EC11P1 Digital Systems Design Lab 3
17EC11P2 Seminar-1 4
M.Tech. (DECS) I SEMESTER
17EC1101-DIGITAL SYSTEM DESIGN
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT I
DESIGN OF DIGITAL SYSTEMS: ASM charts, Hardware description language and
control sequence method, Reduction of state tables, state assignments, Design of
sequence detector and generators, Design using PLA’s, PLA minimization and PLA
folding.
UNIT II
SEQUENTIAL CIRCUIT DESIGN & FAULT MODELING: Design of Iterative
circuits, Design of sequential circuits using ROMs and PLAs, sequential circuit design
using CPLD, FPGAs. Fault classes and models – Stuck at faults, bridging faults,
transition and intermittent faults.
UNIT III
TEST GENERATION: Fault diagnosis of Combinational circuits by conventional
methods – Path Sensitization technique, Boolean difference method, Kohavi algorithm.
D’ algorithm, PODEM, Random testing, transition count testing, Signature Analysis and
testing for bridging faults.
UNIT IV
FAULT DIAGNOSIS IN SEQUENTIAL CIRCUITS: State identification and fault
detection experiment. Machine identification, Design of fault detection experiment.
UNIT V
PLA TESTING & ASYNCHRONOUS SEQUENTIAL MACHINE: Fault models,
Test generation and Testable PLA design. Fundamental mode model, flow table, state
reduction, minimal closed covers, races, cycles and hazards.
TEXT BOOKS:
1. ZVI. Kohavi – “Switching & finite Automata Theory” (TMH)
2. N. N. Biswas – “Logic Design Theory” (PHI)
3. Nolman Balabanian, Bradley Calson – “Digital Logic Design Principles” – Wily
Student Edition 2004 (wiley India Pvt Ltd2004).
REFRENCE BOOKS:
1. M. Abramovici, M. A. Breues, A. D. Friedman – “Digital System Testing and Testable
Design”, Jaico Publications
2. Charles H. Roth Jr. – “Fundamentals of Logic Design”. (Penram Internationl
Publishing)
3. Frederick. J. Hill & Peterson – “Computer Aided Logic Design” – Wiley 4th Edition.
M.Tech. (DECS) I SEMESTER
17EC1102-ADVANCED DIGITAL SIGNAL PROCESSING
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT I
OVERVIEW : The Discrete-Time Fourier Transform, Energy Density Spectrum of a Discrete-
Time Sequence, Band-Limited Discrete-Time signals, The Frequency Response of LTI Discrete-
Time System.
UNIT II
LTI DISCRETE-TIME SYSTEMS IN THE TRANSFORM DOMAIN: Types of Linear-
Phase transfer functions, Simple Digital Filters, Complementary Transfer Functions, Inverse
Systems, System Identification, Digital Two-Pairs, Algebraic Stability Test.
UNIT III
DIGITAL FILTER SRTUCTURE AND DESIGN: All Pass Filters, Tunable IIR Digital
Filters, IIR Tapped Cascade Lattice Structures, FIR Cascaded Lattice Structures, Parallel All Pass
Realization of IIR Transfer Functions, Poly phase Structures, Digital Sine-Cosine Generator,
Computational Complexity of Digital Filter Structures, Design of IIR Filter using Pades’
approximation, Least Square Design Methods, Design of Computationally Efficient FIR Filters.
UNIT IV
DSP ALGORITHMS: Fast DFT algorithms based on Index mapping, Sliding Discrete Fourier
Transform, DFT Computation Over a narrow Frequency Band, Split Radix FFT, Linear filtering
approach to Computation of DFT using Chirp Z-Transform.
UNIT V
POWER SPECTRAL ESTIMATION METHODS: Estimation of spectra from finite duration
observation of signals, Non-parametric methods: Bartlett, Welch & Blackmann - Tukey methods.
Parametric Methods for Power Spectrum Estimation: Relation between Auto correlation & Model
parameters, Yule-Waker & Burg Methods, MA & ARMA models for power spectrum estimation.
TEXT BOOKS:
1. Digital Signal Processing by Sanjit K Mitra, Tata McGraw Hill Publications.
2. Digital Signal Processing Principles, Algorithms, Applications by J G Proakis,
D G Manolakis, PHI.
REFERENCE BOOKS:
1. Discrete-Time Signal Processing by A V Oppenhiem, R W Schafer, Pearson Education.
2. DSP- A Practical Approach- Emmanuel C Ifeacher Barrie. W. Jervis, Pearson Education.
3. Modern Spectral Estimation Techniques by S. M .Kay, PHI, 1997
4. Modern Spectral Estimation techniques by Nit zberg, R.Affiliation: AA, PHI, 1981.
M.Tech. (DECS) I SEMESTER
17EC1103-EMBEDDED SYSTEM CONCEPTS
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT I
UNIT II
UNIT III
SOFTWARE ARCHITECTURE AND RTOS CONCEPTS: Round robin, round robin with
interrupts, function queue scheduling architecture, selecting an architecture saving memory space.
Architecture of the kernel, interrupt service routines, semaphores, message queues, pipes.
UNIT IV
UNIT V
TEXT BOOKS:
1. Computers as a Component: Principles of Embedded Computing System Design- Wayne Wolf
2. An Embedded Software Premier: David E. Simon.
3. Embedded / Real Time Systems-KVKK Prasad, Dream Tech. press, 2005, John Stan Kovic
University of Virginia, Alan Burns University of New York.
REFERENCEBOOKS:
1. Embedded Systems by K.V. Shibhu, TMH, 2010
2. Embedded Real Time Systems Programming-Sri Ram V Iyer, Pankaj Gupta, TMH, 2004
3. Embedded System Design- A Unified Hardware/Software Introduction- Frank Vahid, Tony
D.Givargis, John Willey, 2002
M.Tech (DECS) I SEMESTER
17EC1104-CODING THEORY & TECHNIQUES
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT I
SOURCE CODING: Mathematical Model of Information, Logarithmic Measure of
Information, Average and Mutual Information and Entropy, Coding for Discrete
Memory less Sources, Source Coding Theorem, Fixed Length and Variable Length
Coding, properties of Prefix codes, Shannon-Fano Coding, Huffman code, Huffman
code applied for pair of Symbols, Efficiency Calculations, Lempel-Ziv Codes.
UNIT II
LINEAR BLOCK CODES: Introduction to Linear Block Codes, Generator Matrix, and
Systematic Linear Block codes, Encoder Implementation of Linear Block Codes, Parity
Check Matrix, Syndrome Testing, Error Detecting and Correcting Capability of Linear
Block Codes.
UNIT III
HAMMING CODES: Probability of an undetected error for linear codes over a Binary
Symmetric Channel, Weight Enumerators and Mac-Williams identities, Perfect codes,
Application of Block Codes for Error Control in Data Storage Systems.
UNIT IV
CYCLIC AND CONVOLUTIONAL CODES: Algebraic structure of Cyclic Codes,
Binary Cyclic Code properties, Encoding in Systematic and Non-systematic form,
Encoder using (n-k) Bit Shift Register, Syndrome Computation and Error
Detection, Decoding of Cyclic Codes, Encoding, Structural properties of Convolutional
Codes, State Diagram, Tree diagram, Trellis Diagram, Maximum-Likelihood Decoding
of Convolutional Codes.
UNIT V
BCH CODES AND VITERBI ALGORITHM: Groups, Fields, Binary Fields
Arithmetic, Construction of Galois fields GF (2m), Basic properties of Galois Fields,
Computation using Galois Field GF (2m) Arithmetic, Description of BCH Codes,
Decoding procedure for BCH codes. Fano, Stack Sequential Decoding Algorithms,
Application of Viterbi and Sequential Decoding.
TEXT BOOKS:
1. SHU LIN and Daniel J. Costello, Jr. “Error Control Coding – Fundamentals and
Applications”, Prentice Hall Inc.
2. Bernard Sklar,”Digital Communications – Fundamental and Application”, Pearson
Education, Asia.
3. Man Young Rhee, “Error Control Coding Theory”, McGraw Hill Publications.
REFERENCE BOOKS:
1. John G. Proakis, “Digital Communications”, Mc. Graw Hill Publication.
2. K. Sam Shanmugam, “Digital and Analog Communication Systems”, Wiley
Publications.
3. Symon Haykin, “Digital Communications”, Wiley Publications.
M.Tech. (DECS) I SEMESTER
17EC1105-TRANSFORM TECHNIQUES
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT I
REVIEW OF TRANSFORMS: Signal spaces, concept of convergence, Hilbert spaces for energy
signals, Fourier basis, FT-failure of FT-need for time-frequency analysis, Continuous FT, DTFT,
Discrete Fourier Series and Transforms, Z-Transform, relation between CFT-DTFT, DTFT-DFS,DFS-
DFT, Walsh-Hadamard, Haar, Slant, KLT, Hilbert Transforms – definition, properties and applications.
UNIT II
CWT & MRA: Time-frequency limitations, tiling of time-frequency plane for STFT, Heisenberg
uncertainty principle, Short time Fourier Transform (STFT) analysis, short comings of STFT, Need for
wavelets- Wavelet Basis, Continuous time wavelet Transform Equation- Need for scaling Function-
Multi resolution analysis, Tiling of time scale plane for CWT. Important Wavelets : Haar, Mexican Hat
Meyer, Shannon, Daubechies
UNIT III
MULTIRATE SYSTEMS , FILTER BANKS AND DWT: Basics of Decimation and Interpolation in
time & frequency domains, Two-channel Filter bank, Perfect Reconstruction Condition, Relationship
between Filter Banks and Wavelet basis, DWT Filter Banks For Daubechies Wavelet Function.
UNIT-IV
UNIT-V
TEXT BOOKS:
REFERENCE BOOKS:
UNIT-I
UNIT-II
Feed Forward Neural Networks: Introduction, perceptron models, Discrete and continuous
perceptron networks, perceptron convergence theorem, limitation of perceptron model, applications.
UNIT-III
ANN Paradigms: Multi – layer perceptron using Back propagation Algorithm-Self – organizing Map –
Radial Basis Function Network – Functional link, network – Hopfield Network.
UNIT-IV
UNIT-V
Classical and Fuzzy Sets: Introduction to classical sets, properties, operations and relations; Fuzzy
sets, membership, uncertainty, properties, fuzzy relations, cardinalities, membership functions.
Fuzzy Logic System Components: Fuzzification, membership value assignment, development of rule
base and decision-making system, defuzzification to crisp sets, defuzzification methods.
Text Books:
1. “Neural networks, Fuzzy logic, Genetic algorithms: synthesis and application” by Rajasekharan
and Rai, PHI publication
2. “Introduction to Artificial Neural systems” by Jacek M.Zuarda, Jaico publishing house.
Reference Books:
2. “Fuzzy Logic with Engineering Applications” by Thimothy J Ross, Mc-Graw Hill New york (1997)
M.Tech. (DECS) I SEMESTER
17EC11E2-LOW POWER VLSI DESIGN
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT-I
MOS/BiCMOS PROCESSES: Introduction to low voltage low power design, limitations, Silicon on
insulator, CMOS process, BiCMOS process, Integration and Isolation considerations, Integrated
Analog/Digital BiCMOS process.
UNIT-II
LOW POWER DESIGN APPROACHES: CMOS Inverter DC characteristics, sources of power
dissipation, low power design approaches through voltage scaling, switched capacitance minimization
approaches.
UNIT-III
CMOS AND BiCMOS LOGIC GATES: Conventional CMOS and BiCMOS logic gates, performance
evaluation, low voltage BiCMOS applications.
UNIT-IV
LOW VOLTAGE LOW POWER ADDERS: Introduction, standard adder cells, CMOS adder’s
architectures:- Ripple carry adder, carry look ahead adder, carry select adder, carry save adder, low
voltage low power design techniques:- Trends of technology and power supply voltage, low voltage low
power logic styles.
UNIT-V
LOW VOLTAGE LOW POWER MULTIPLIERS & MEMORIES: Braun, Baugh, Booth multipliers
and Introduction to Wallace tree multiplier. SRAM— Basics of SRAM, read-write operation, low power
techniques. DRAM--Basics of DRAM, read –write operation, low power techniques, self refresh
technique.
TEXT BOOKS:
1. CMOS/Bi-CMOS ULSI low voltage, low power -- Yeo Rofail/Gohl- Pearson Education Asia 1st
Indian reprint, 2002.
2. CMOS Digital Integrated circuits-Analysis and Design -- Sung-Mo Kang, Yusuf Leblebici,
TMH,2011.
3. Low voltage, Low power VLSI subsystems -- Kiat-Seng Yeo, Kaushik Roy, TMH professional
Engineering.
REFERENCES:
1. Practical low power digital VLSI Design -- Gary K. Yeap, KAP, 2002.
3. Low Power CMOS Design –Anantha chadrasekhran, IEEE press/ wiley International, 1998.
M.Tech. (DECS) I SEMESTER
17EC11E3- DIGITAL CONTROL SYSTEMS
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT-I
Introduction and signal processing: Introduction to analog and digital control systems – Advantages
of digital systems – Typicalexamples – Signals and processing – Sample and hold devices – Sampling
theorem and datareconstruction – Frequency domain characteristics of zero order hold.
UNIT-II
Z–transformations: Z–Transforms – Theorems – Finding inverse z–transforms –Formulation of
differenceequations and solving – Block diagram representation – Pulse transfer functions and
findingopen loop and closed loop responses.
UNIT-III
State space analysis and the concepts of Controllability and observability: State space
representation of discrete time systems – State transition matrix and methods ofevaluation –
Discretization of continuous – Time state equations – Concepts of controllabilityand observability –
Tests(without proof).
UNIT- IV
Stability analysis: Mapping between the s–Plane and the z–Plane – Primary strips and Complementary
strips –Stability criterion – Modified Routh’s stability criterion and Jury’s stability test.
UNIT-V
Design of Digital Control System: Design of Discrete PID Controller, Design of discrete state
feedback controller. Design of set pointtracker. Design of Discrete Observer for LTI System. Design of
Discrete compensator.
Discrete output feedback control: Design of discrete output feedback control. Fast output sampling
(FOS) and periodic outputfeedback controller design for discrete time systems.
Text Books:
Reference Books:
TOTAL 24 - 07 28 - - - - - - 800
M.Tech. (DECS) I YEAR II SEMESTER: 2017-2018
LIST OF SUBJECTS
6 ELECTIVE- II 4
LABORATORY:
UNIT I
INTRODUCTION TO WIRELESS COMMUNICATIONS SYSTEMS: Evolution, Examples
of Wireless Communication systems, Comparison, Generations of Cellular Networks, WLL,
Bluetooth and Personal Area Networks.
UNIT II
MOBILE RADIO PROPAGATION: Large-Scale Path Loss, Introduction to Radio Wave
Propagation, Propagation Mechanisms, Ground Reflection (Two-Ray) Model. Small-Scale
Fading and Multipath, Impulse Response Model of a Multipath Channel, Small-Scale
Multipath Measurements, Parameters of Mobile Multipath Channels, Types of Small-Scale
Fading, Rayleigh and Ricean Distributions, Statistical Models for Multipath Fading Channels.
UNIT III
DIVERSITY TECHNIQUES: Repetition coding and Time Diversity- Frequency and Space
Diversity, Receive Diversity- Concept of diversity branches and signal paths- Combining
methods, Selective diversity combining, Switched combining, maximal ratio combining,
Equal gain combining, performance analysis for Rayleigh Fading channels.
UNIT 1V
DIVERSITY IN DS-SS SYSTEMS: Rake Receiver, Performance analysis. Spread Spectrum
Multiple Access, CDMA Systems: Interference Analysis for Broadcast and Multiple Access
Channels, Capacity of cellular CDMA networks: Reverse link power control, Hard and Soft
hand off strategies.
UNIT-V
FADING CHANNEL CAPACITY: Capacity of Wireless Channels- Capacity of flat and
frequency selective fading channels, Multiple Input Multiple output (MIMO) systems
GSM specifications and Air Interface, specifications, IS 95 CDMA- 3G systems: UMTS &
CDMA 2000 standards and specifications.
TEXT BOOKS:
1. Andrea Goldsmith, “Wireless Communications”, Cambridge University press.
2. Simon Haykin and Michael Moher, “Modern Wireless Communications”, Person Education.
3. T.S. Rappaport, “Wireless Communication, principles & practice”, PHI, 2002.
REFERENCE BOOKS:
nd
1. G.L Stuber, “Principles of Mobile Communications”, 2 edition, Kluwer Academic
Publishers.
2. Kamilo Feher, „Wireless digital communication‟, PHI, 1995 by F.Molisch, Prentice-hall
3. R.L Peterson, R.E. Ziemer and David E. Borth, “Introduction to Spread Spectrum
Communication”, Pearson Education.
4. A.J.Viterbi, “CDMA- Principles of Spread Spectrum”, Addison Wesley, 1995.
M.Tech. (DECS) II SEMESTER
17EC1202-DIGITAL COMMUNICATION TECHNIQUES
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT I
CHARACTERIZATION OF COMMUNICATION SIGNALS AND SYSTEMS: Signal
space representations- Vector Space Concepts, Signal Space Concepts, Orthogonal Expansion of
Signals. Representation of Digitally Modulated Signals-Memory less Modulation Methods.
Matched Filter receiver and error probabilities.
UNIT II
COMMUNICATION OVER ADDITIVE GAUSSIAN NOISE CHANNELS: Optimum
receiver for binary signals, Optimum receiver for M-ary orthogonal signals, Probability of error
for envelope detection of M-ary orthogonal signals. Optimum waveform receiver for colored
Gaussian noise channels, Karhunen Loeve expansion approach, whitening.
UNIT III
FADING CHANNELS: Characterization of fading multipath channels, Statistical Models for
fading channels, Time varying Channel impulse response, narrow and wide band fading models,
channel correlation functions, Key multipath parameters, Rayleigh and Ricean fading channels,
Simulation methodology of fading channels.
UNIT IV
COMMUNICATION OVER BAND LIMITED CHANNELS: Communication over band
limited Channels- Optimum pulse shaping- Nyquist criterion for zero ISI, partial response
signaling- Equalization Techniques, Zero forcing linear Equalization- Decision feedback
equalization.
UNIT V
DIGITAL MODULATION SCHEMES AND OFDM: Performance of BPSK, QPSK, FSK,
DPSK, MSK etc. over wireless channels. OFDM Carrier Synchronization, Timing
synchronization, Multichannel and Multicarrier Systems.
TEXT BOOKS:
1. J. Proakis, Digital Communications, McGraw Hill, 2000
2. J. Viterbi and J. K. Omura, Principles of Digital Communications and Coding, McGraw Hill,
1979
3. Marvin K. Simon, Jim K Omura, Robert A. Scholtz, Barry K.Levit, Spread Spectrum
Communications, 1995.
4. Andrew J Viterbi, CDMA Principles of Spread Spectrum Communications, Addison Wesley,
1995.
REFERENCE BOOKS:
1. Ahmad R S Bahai, Burton R Saltzberg ,Mustafa Ergen, “Multi-carrier Digital
Communications: Theory and Applications of OFDM.” Springer Publications.
2. J.S.Chitode, “Digital Communication”, Technical Publications.
3. Edward. A. Lee and David. G. Messerschmitt, “Digital Communication”, Allied Publishers
(second edition).
4. J Marvin.K.Simon, Sami. M. Hinedi and William. C. Lindsey, “Digital Communication
Techniques”, PHI.
5. William Feller, “An introduction to Probability Theory and its applications”, 3rd Ed Vol I,
wiley Publications and vol ll, wiley 2000
M.Tech. (DECS) II SEMESTER
17EC1203-MODERN RADAR SYSTEMS
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT-I
RADAR CONFIGURATIONS & OPERATIONAL CONCEPTS: Basic Function– Frequency Bands
& Applications – Range Equation –Receiver Noise– Signal to Noise Ratio – Search
Radar – Range with Active Jamming–Range with Clutter–Detection Range in Combined
Interference-Radar Cross Section of Simple Objects and Complex Targets – Bi-Static
Cross –Section.
UNIT-II
RADAR DETECTION TECHNIQUES: Coherent & Non-Coherent Detection – Matched Filters-
Different methods of Integration of Pulse Trains – Detection of Fluctuating Targets –
Fluctuation laws – Diversity gain – Binary Integration of Fluctuation Targets –
Cumulative Integration of Fluctuating Targets – Sequential Detection with Rapid
Confirmation – Constant False Alarm Rate Detection – Cell Averaging – Two Parameter
Averaging & Non-Parametric Averaging.
UNIT-III
RADAR MEASUREMENT AND TRACKING TECHNIQUES: Radar Measurement Characteristics –
Sensitivity – Angle Measurement – Conical Scan – Sector Scan – Mono Pulse Radar-
Range Tracking –Doppler Measurement –Error Analysis of Radar.
UNIT-IV
SPECIAL RADAR CONFIGURATIONS AND THEIR APPLICATIONS: Bi-Static Radar – Synthetic
Aperture Radar – HF Over The Horizon Radar –Air Surveillance Radar– Height Finder
& 3D radar.
UNIT-V
RADAR ELECTRONIC COUNTER MEASURES (ECM) AND ELECTRONIC COUNTER-COUNTER
MEASURES (ECCM): Noise Jamming of Surveillance Radar – Detection Range in Noise
Jamming – ECCM Provisions for Surveillance Radar – Objective of ECM –Tracking
Radar – Prevention & Delay of Acquisition – Denial of Range & Doppler data.
TEXT BOOKS:
REFERENCE BOOKS:
TEXT BOOKS:
1. Adaptive Signal Processing - Bernard Widrow, Samuel D.Strearns, 2005, PE.
2. Adaptive Filter Theory - Simon Haykin-, 4 ed., 2002, PE Asia.
REFERENCE BOOKS:
1. Optimum signal processing: An introduction - Sophocles. J. Orfamadis, 2 ed., 1988, McGraw-
Hill, New york
2. Adaptive signal processing-Theory and Applications, S.Thomas Alexander, 1986, Springer-
Verilog.
M.Tech. (DECS) II SEMESTER
17EC1205-MICRO COMPUTER SYSTEM DESIGN
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT I
REVIEW OF 8086 PROCESSOR: Architecture, Register organization, Addressing
Modes and Instruction Set (Brief treatment only). 80286 Microprocessors: Architecture,
Register Organization, Addressing Modes and instruction sets of 80286 (brief treatment
only).
UNIT II
THE 80386, AND 80486 MICRO PROCESSORS: Architectural features, Register
Organization, Memory management, Virtual 8086 mode, The Memory Paging
Mechanism, Pin Definitions of 80386 and 80486 (brief treatment).
UNIT III
THE PENTIUM AND PENTIUM PRO PROCESSORS: The Memory System,
Input/output system, Branch Prediction Logic, Cache Structure, Pentium Registers,
Serial Pentium pro features. The Pentium IV And Dual Core Micro Processors:
Architecture, Special Registers and Pin Structures (brief treatment only).
UNIT IV
INTRODUCTION TO MULTIPROGRAMMING: Fundamentals of I/O
Considerations Programmed I/O, Interrupt I/O, Block Transfers and DMA, I/O Design
Example. Process Management, Semaphores Operations, Common Procedure Sharing,
Memory Management, Virtual Memory Concept of 80286 and other advanced
Processors.
UNIT V
ARITHMETIC COPROCESSOR, MMX AND SIMD TECHNOLOGIES: Data
formals for Arithmetic Coprocessor, Internal Structure of 8087 and Advanced
Coprocessors. Instruction Set (brief treatment).
TEXT BOOKS:
1. Barry, B. Brey, “The Intel Microprocessors,”8 th Edition Pearson Education, 2008.
2. A.K. Ray and K.M. Bhurchandi,”Advanced Microprocessor and Peripherals,” TMH.
REFERENCE BOOKS:
1. YU-Chang, Glenn A. Gibson, “Micro Computer Systems: The 8086/8088 Family
Architecture, Programming and Design” 2nd Edition, Pearson Education, 2007.
2. Douglas V. Hall, “Microprocessors and Interfacing,” Special Indian Edition, 2006.
M.Tech. (DECS) II SEMESTER
17EC12E1-DSP PROCESSORS & ARCHITECTURES
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT I
INTRODUCTION TO DIGITAL SIGNAL PROCESING: Linear Time-Invariant
systems, Digital filters, Decimation and interpolation, Analysis and Design tool for DSP
Systems MATLAB, DSP using MATLAB.
UNIT II
COMPUTATIONAL ACCURACY IN DSP IMPLEMENTATIONS: Number formats
for signals and coefficients in DSP systems, Dynamic Range and Precision, Sources of error
in DSP implementations, A/D Conversion errors, DSP Computational errors, D/A
Conversion Errors, Compensating filter.
UNIT III
ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES: Basic Architectural
features, DSP Computational Building Blocks, Bus Architecture and Memory, Data
Addressing Capabilities, Address Generation Unit, Programmability and Program
Execution, Speed Issues, Features for External interfacing, Commercial Digital signal-
processing Devices, Data Addressing modes, Memory space, instructions, Program
Control of TMS320C54XX Processors, and Programming On-Chip Peripherals, Interrupts,
Pipeline Operation of TMS320C54XX Processors.
UNIT IV
IMPLEMENTATIONS OF BASIC DSP & FFT ALGORITHMS: The Q-notation, FIR
Filters, IIR Filters, Interpolation Filters, Decimation Filters, PID Controller, Adaptive
Filters, 2-D Signal Processing. An FFT Algorithm for DFT Computation, A Butterfly
Computation, Overflow and scaling, Bit-Reversed index generation, An 8-Point FFT
implementation on the TMS320C54XX, Computation of the signal spectrum.
UNIT V
INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSP
DEVICES: Memory space organization, External bus interfacing signals, Memory
interface, Parallel I/O interface, Programmed I/O, Interrupts and I/O, Direct memory
access (DMA). A Multichannel buffered serial port (McBSP), McBSP Programming, a
CODEC interface circuit, CODEC programming, A CODEC-DSP interface example.
TEXT BOOKS:
1. Digital Signal Processing – Avtar Singh and S. Srinivasan, Thomson Publications, 2004.
2. DSP Processor Fundamentals, Architectures & Features – Lapsley et al.S. Chand & Co, 2000.
REFERENCE BOOKS:
1. Digital Signal Processors, Architecture, Programming and Applications-B.Venkata
Ramani and M. Bhaskar, TMH, 2004.
2. Digital Signal Processing – Jonatham Stein, John Wiley, 2005.
M.Tech. (DECS) II SEMESTER
17EC12E2- INTERNET OF THINGS
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT-I
INTRODUCTION & CONCEPTS: Introduction to Internet of Things, Physical Design of IOT, Logical
Design of IOT, IOT Enabling Technologies, IOT Levels. WCNs and everyday things: RFIDS/GRIFS, EPC,
WCNs/mobile etc.
UNIT – II
DOMAIN SPECIFIC IOTS: Home Automation, Cities, Environment, Energy, Retail, Logistics,
Agriculture, Industry, Health & Life Style, interaction models and paradigms between human and things.
UNIT – III
M2M: M2M, Difference between IOT and M2M, SDN and NFV for IOT, Software defined Networking,
Network Function Virtualization, Need for IOT Systems Management, Simple Network Management
Protocol, Limitations of SNMP, and Network Operator Requirements.
UNIT – IV
CLOUD COMPUTING BASICS: Cloud Computing basics, terminology, characteristics, services, cloud
deployment – public, private environments, Secure Communication, Cloud Security.
UNIT – V
DEVELOPING INTERNET OF THINGS & LOGICAL DESIGN USING PYTHON: Introduction, IOT
Design Methodology, Installing Python, Python Data Types & Data Structures, Control Flow, Functions,
Modules, Packages, File Handling, Date/ Time Operations, Classes, Python Packages.
IOT PHYSICAL DEVICES & ENDPOINTS: What is an IOT Device, Exemplary Device, Board, Linux
on Raspberry Pi, Interfaces, and Programming& IOT Devices.
SEMANTIC TECHNOLOGIES: Ontologies, micro formats, context etc.
TEXT BOOKS:
1. Vijay Madisetti, ArshdeepBagha,”Internet of Things A Hands-On- Approach”,2014, ISBN:978-1-
118-43062-0
REFERENCE BOOKS:
1. Adrian McEwen, “Designing the Internet of Things”, Wiley Publishers.
2. Daniel Kellmereit, “The Silent Intelligence: The Internet of Things”.
M.Tech. (DECS) II SEMESTER
17EC12E3- ADVANCED DIGITAL COMMUNICATION
Credits: 4
Hours /week: 4 Hrs Sessional Marks: 40
Univ.Exam.Duration: 3Hrs Univ.Examination.Marks: 60
UNIT- I
INTRODUCTION: Digital communication system (description of different modules of the block diagram),
Complex baseband representation of signals, Gram-Schmidt orthogonalization procedure. M-ary orthogonal
signals, bi-orthogonal signals, simplex signal waveforms.
UNIT-II
MODULATION: Pulse amplitude modulation (binary and M-ary, QAM), Pulse position modulation (binary
and M-ary), Carrier Modulation (M-ary ASK, PSK, FSK, DPSK), Continuous phase modulation (QPSK and
variants, MSK, GMSK).
UNIT-III
BAND-LIMITED CHANNELS: Pulse shape design for channels with ISI: Nyquist pulse, Partial response
signalling (duo binary and modified duo binary pulses) and demodulation; Channel with distortion: Design of
transmitting and receiving filters for a known channel and for time varying channel (equalization);
Performance: Symbol by symbol detection and BER, symbol and sequence detection, Viterbi algorithm
SYNCHRONIZATION: Different synchronization techniques (Early-Late Gate, MMSE, ML and spectral
line methods).
UNIT-V
TEXT BOOKS:
REFERENCE: