AND8408/D

Pulse Generation and

Signal Conditioning Circuits
Using Configurable
Multifunction Logic Gates
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Prepared by: Jim Lepkowski
ON Semiconductor APPLICATION NOTE
Introduction
A configurable multifunction logic gate is a versatile IC Signal Conditioning Circuits
that can be used to create pulse generation and signal • 2−to−1 multiplexer / selector
conditioning circuits. Configurable logic gates are a low cost • Voltage translator
flexible IC that can function as a buffer / inverter, AND /
• Power good indicator
NAND, OR / NOR, XOR / XNOR or multiplexer. Twelve
popular circuits are shown that are created by either adding • Switch debouncer
an external resistor and capacitor to an input pin or by taking • Oscillators
advantage of the inherent features of the multifunctional • NRZ−to−RZ data converter
gates. Design examples are provided for the following
circuits: Configurable Multifunction Logic Gates
Table 1 provides a list of the functions that are available
Pulse Generation Circuits
in the industry standard ‘57’, ‘58’, ‘97’, ‘98’ and ‘99’
• Dual edge delay configurable gates. Configurable logic ICs are available in
• Leading edge delay a number of different logic technologies that offer a range of
• Trailing edge delay operating voltages and performance specifications.
• Dual edge detector / frequency doubler Appendix A provides an overview of the attributes of the
• Leading edge detector ON Semiconductor configurable logic devices.
• Trailing edge detector
Table 1. SUMMARY OF THE LOGIC FUNCTIONS AVAILABLE WITH THE CONFIGURABLE LOGIC GATES
Part Number / Function
NL7SZxx
NLX1Gxx 57 58 97 98 99
Buffer
Inverter
2−to−1 MUX / Selector
2−to−1 MUX / Selector (with inverted output)
2−input AND
2−input AND (with 1−inverted input)
2−input NAND
2−input NAND (with 1−inverted input)
2−input OR
2−input OR (with 1−inverted input)
2−input NOR
2−input NOR (with 1−inverted input)
2−input XOR
2−input XOR (with 1−inverted input)
2−input XNOR
Available Logic Configurations 7 7 9 9 15

© Semiconductor Components Industries, LLC, 2009 1 Publication Order Number:

August, 2009 − Rev. 0 AND8408/D
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The desired logic function is determined from the inputs. The AND function is selected by setting input pin A
Functional Truth Table provided in the data sheets. For to a logic ‘1’ which selects the bottom four rows of the truth
example, Figure 1 shows how to use the ‘57’ as a 2−input table. The B and C pins serve as the inputs while the output
AND gate or the equivalent 2−input NOR with inverted is provided by pin Y.

’57’ FUNCTIONAL DIAGRAM

NLX1G57
A

’57’ FUNCTIONAL TABLE

Design Example:
2−Input AND / NOR
Input A = H
+3.3 V
’57’
B 1 6 C
B
Y GND VCC
C 2 5

A 3 4 Y
B
Y
C

Figure 1. This design example shows how to implement a 2−input AND gate with
the NLX1G57 configurable logic gate

The Schmitt trigger inputs are an important feature of the VOUTPU

configurable logic gates. Schmitt trigger inputs have two T

different switching points, as shown in Figure 2. The

VOH
difference or hysteresis between the Vt+ and Vt− input
switching threshold voltages is an important attribute with
slow transitioning signals. The Schmitt trigger input pins are Hysteresis
an essential feature in the pulse generation and signal
conditioning circuits that use an external resistor and
capacitor to delay the input signal.

VOL

VT− VT+ VINPUT

Figure 2. The inputs of the configurable logic gates

have Schmitt trigger inputs with hysteresis that
prevent glitching on the output signal

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 AND8408/D

Pulse Generation Circuits delay the low−to−high and/or high−to−low transition times
Often it is necessary to delay either one or both edges of of the output signal by an amount that is proportional to the
a clock signal. Figures 3, 4 and 5 provide edge delay circuits RC product. Note that the delay times td1 and td2 of the dual
that are created by adding an external resistor and capacitor delay circuit will not be equivalent due to the hysteresis of
to the input pin of the logic gate. The resistor and capacitors the Schmitt trigger inputs.

Dual Edge Delay

R
IN’
IN OUT IN

IN’

OUT
R
IN’
IN OUT td1
td2

OUT

Figure 3. A resistor, capacitor and buffer / inverter delay the leading and rising edges of an input pulse

Leading Edge Delay

IN
IN’ IN
OUT

R
C
IN’

OUT

IN
IN’ OUT td

R
C

OUT

Figure 4. A leading edge delay circuit is created with a resistor, capacitor and an AND / NAND gate

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 AND8408/D

Trailing Edge Delay

IN
IN’ OUT

IN
R
C

IN’

OUT
IN
IN’ OUT
td
R
C
OUT

Figure 5. The trailing edge delay circuit is provided with a resistor, capacitor and OR / NOR gate

Edge detectors are a convenient circuit to generate a leading and trailing edges of the input signal. The pulse
second timing signal after the detection of the rising or widths of the two pulses (tw1, tw2) are proportional to the
falling edge of a clock signal. An exclusive OR gate provides value of the resistor and capacitor. In contrast, the leading
a dual edge detector circuit, as shown in Figures 6 and 7. In and trailing edge detection circuits, shown in Figures 8
addition, the dual edge detector circuit functions as a and 9, use an AND / NAND gate to provide a single
frequency doubler because a pulse is created on both the detection pulse.

Dual Edge Detector / Frequency Doubler−Option I

IN
IN’ OUT
IN

R
C
IN’

OUT

IN
OUT tw1
IN’
tw2

R
C

OUT

Figure 6. A resistor, capacitor and XOR / XNOR gate provides one option to create a
dual edge detector or frequency doubler

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 AND8408/D

Dual Edge Detector / Frequency

Doubler−Option II IN

IN
IN
IN
IN’ OUT

R
IN’
C

OUT

tw1
tw2

IN

IN’

IN
IN’ IN’ OUT

R
IN’
C

OUT

Figure 7. A resistor, capacitor and XOR gate with an inverted input forms an alternative method to create a dual
edge detector or frequency doubler

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 AND8408/D

Leading Edge Detector

IN

IN
IN’ IN’ OUT
IN’
R
C IN’

OUT
IN
IN’ IN’ OUT
tw

R
C

OUT

Figure 8. The leading edge detector circuit is provided by a resistor, capacitor and
AND / NAND gate with an inverted input

Trailing Edge Detector

IN
IN
IN IN
IN’ OUT

R
C

IN’

IN
IN
OUT OUT
IN’

R
C tw

OUT

Figure 9. A trailing edge detector is created from a resistor, capacitor and an

AND / NAND gate with an inverted input

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 AND8408/D

Signal Conditioning Circuits application is to use the configurable gate to shift the input
Configurable logic ICs can function as a multiplexer or and output logic levels, as shown in Figure 11. Note that the
voltage translator. The ‘97’, ‘98’ and ‘99’ devices contain a overvoltage tolerance feature is not available in all
2−to−1 selector that is useful in data multiplexing configurable gates; however, it is a standard feature in the
applications, as shown in Figure 10. Another popular ON Semiconductor devices.

2−to−1 Multiplexer / Selector

IN1 / IN2

IN1
IN1
OUT
IN2

IN2

IN1 / IN2

OUT

IN1

OUT
IN2

OUT

IN1 / IN2 IN1 IN2

Figure 10. The configurable logic gate can be used as a two−to−one multiplexer / selector

Voltage Translator
(VIN > VCC)
IN VIN
VCC

VIN

IN OUT

OUT
VCC

Figure 11. The overvoltage tolerant (OVT) feature on the input pin provides a simple method to create a
high−to−low voltage logic translator

The power indicator circuit shown in Figure 12 provides voltage supply has stabilized. In contrast, a diode is used to
a low cost alternative to analog comparator circuits that quickly discharge the capacitor at powerdown and provide
monitor the amplitude of a voltage supply. The external a signal that can be used to initiate the shutdown of power
resistor and capacitor delay the powerup sequence until the sensitive components.

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 AND8408/D

Power Indicator Powerup Powerdown

VA

VA

D R
VB
VB

PWR
VIN

C
VIN
td2 << td1 VA

td1 td2

PWR
VB

Figure 12. A ‘Power Good’ indicator can be created from a diode, resistor, capacitor and buffer
The circuit provides a delay at powerup and a quick warning at powerdown

Switch debouncing, oscillators and Non−Return−to−Zero buffer gate. Figure 14 provides an example of a simple
(NRZ) to Return−to−Zero (RZ) data converters are oscillator circuit that can be used to create either a clock or
additional circuits that can be implemented with a gated clock signal. The AND gate can be used to combine
configurable gate. A switch debouncer circuit is shown in a clock signal with a NRZ input signal to create a RZ output
Figure 13 that is formed with two resistors, a capacitor and signal, as shown in Figure 15.

Switch Debouncer
VCC Switch Position
Open−to−Close Close−to−Open

R1

R2 VIN

VIN OUT
td1 td2

C R1 >> R2
td1 a R2 x C
td2 a R1 x C
OUT

Figure 13. The switch debouncer circuit provides time delays that prevent glitching on the output signal

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 AND8408/D

Oscillators
1
R f req. ^
0.8 R C

OUT OUT

ON / OFF

OUT

C ON / OFF OUT

Figure 14. An oscillator can be created with a capacitor, resistor and inverter
Substituting a NAND gate for the inverter creates a gated oscillator

NRZ−to−RZ Data Converter

NRZ Input

NRZ Input
RZ Output Clock
Clock

RZ Output

Data Pattern 0 1 1 0 1 1 0

Figure 15. A Non−Return−to−Zero (NRZ) input signal can be converted to a Return−to−Zero (RZ) output with an
AND gate

References
1. Chenier, G. “Configurable Logic gates’ Schmitt Inputs Make Versatile Monostables”, EDN, May 25, 2006.

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 AND8408/D

APPENDIX A: ON Semiconductor’s Configurable Multifunction Logic Gates

Device P/N# Features
‘57’ NL7SZ57 • SC−88 Package
• OVT Inputs
• VCC = 1.65 to 5.5 V

NLX1G57 • ULLGA6 Package

• OVT Inputs
• VCC = 1.65 to 5.5 V
‘58’ NL7SZ58 • SC−88 Package
• OVT Inputs
• VCC = 1.65 to 5.5 V

NLX1G58 • ULLGA6 Package

• OVT Inputs
• VCC = 1.65 to 5.5 V
‘97’ NL7SZ97 • SC−88 Package
• OVT Inputs
• VCC = 1.65 to 5.5 V

NLX1G97 • ULLGA6 Package

• OVT Inputs
• VCC = 1.65 to 5.5 V
‘98’ NL7SZ98 • SC−88 Package
• OVT Inputs
• VCC = 1.65 to 5.5 V

NLX1G98 • ULLGA6 Package

• OVT Inputs
• VCC = 1.65 to 5.5 V
‘99’ NLX1G99 • ULLGA8 Package
• OVT Inputs
• VCC = 1.65 to 5.5 V
• Output Enable

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