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    B) All Sub-Parts of A Question Must Be Answered at One Place Only, Otherwise It Will Not Be Valued. C) Missing Data Can Be Assumed Suitably

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    Gayathri Kalyankar
    This document appears to be an exam for a course on switching theory and logic design. It contains 18 questions across two parts - Part A contains 10 short answer questions worth a total of 25 marks, and Part B contains 8 longer answer questions worth 10 marks each for a total of 50 marks. The questions cover topics like sequential circuits, synchronous vs asynchronous circuits, Boolean algebra, SOP and POS forms, multiplexers, ASM charts, PROMs, shift registers, PLAs, decoders, flip-flops, binary conversions, K-maps, adders and more.

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    B) All Sub-Parts of A Question Must Be Answered at One Place Only, Otherwise It Will Not Be Valued. C) Missing Data Can Be Assumed Suitably

    Uploaded by

    Gayathri Kalyankar
    32 views1 page
    This document appears to be an exam for a course on switching theory and logic design. It contains 18 questions across two parts - Part A contains 10 short answer questions worth a total of 25 marks, and Part B contains 8 longer answer questions worth 10 marks each for a total of 50 marks. The questions cover topics like sequential circuits, synchronous vs asynchronous circuits, Boolean algebra, SOP and POS forms, multiplexers, ASM charts, PROMs, shift registers, PLAs, decoders, flip-flops, binary conversions, K-maps, adders and more.

    Original Title

    A17-STLD-(ECE)-24-11-2018-(Reg)-SET-2

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    This document appears to be an exam for a course on switching theory and logic design. It contains 18 questions across two parts - Part A contains 10 short answer questions worth a total of 25 marks, and Part B contains 8 longer answer questions worth 10 marks each for a total of 50 marks. The questions cover topics like sequential circuits, synchronous vs asynchronous circuits, Boolean algebra, SOP and POS forms, multiplexers, ASM charts, PROMs, shift registers, PLAs, decoders, flip-flops, binary conversions, K-maps, adders and more.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    32 views1 page

    B) All Sub-Parts of A Question Must Be Answered at One Place Only, Otherwise It Will Not Be Valued. C) Missing Data Can Be Assumed Suitably

    Uploaded by

    Gayathri Kalyankar
    This document appears to be an exam for a course on switching theory and logic design. It contains 18 questions across two parts - Part A contains 10 short answer questions worth a total of 25 marks, and Part B contains 8 longer answer questions worth 10 marks each for a total of 50 marks. The questions cover topics like sequential circuits, synchronous vs asynchronous circuits, Boolean algebra, SOP and POS forms, multiplexers, ASM charts, PROMs, shift registers, PLAs, decoders, flip-flops, binary conversions, K-maps, adders and more.

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    © All Rights Reserved
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    Download as doc, pdf, or txt
    of 1

    SET-2

    H.T No Regulations:
    Sreenidhi Institute of Science and Technology A17
    (An Autonomous Institution)
    Code No: 6CC02 Date: 24-Nov-2018 (FN)
    B.Tech II-Year I-Semester End External Examination, November - 2018 (Regular)
    SWITCHING THEORY AND LOGIC DESIGN (ECE)
    Time: 3 Hours Max.Marks:75
    Note: a) No additional answer sheets will be provided.
    b) All sub-parts of a question must be answered at one place only, otherwise it will not be valued.
    c) Missing data can be assumed suitably.

    Part - A Max.Marks:25
    ANSWER ALL QUESTIONS.
    1. Draw the basic sequential circuit block diagram and explain. [3M]
    2. Compare synchronous and asynchronous sequential circuits. [3M]
    3. State and prove the commutative and associative law of Boolean algebra. [3M]
    4. Discuss about sop and pos forms. [3M]
    5. Write short notes on multiplexers. [3M]
    6. Define ASM Chart. [2M]
    7. What are the differences between sequential and combinational circuits? [2M]
    8. What is PROM explain briefly? [2M]
    9. Convert the (1010111)2 to decimal. [2M]
    10. Discuss about triggering. [2M]

    Part – B Max.Marks:50
    ANSWER ANY FIVE QUESTIONS. EACH QUESTION CARRIES 10 MARKS.
    11. a) Explain in detail about shift registers. [3M]
    b) Design a mod-10 ripple counter using T Flip-Flops and explain its operation. [7M]
    12. a) What is PLD? Explain in detail about PLA? [5M]
    b) Draw a state diagrams of a sequence detector which can detect 101. [5M]
    13. a) Convert the given Gray code number to equivalent binary 001001011110010. [5M]
    b) Convert (E1F9.0BC)16 to decimal, binary and octal. [5M]
    14. a) Minimize the following expressions using K-map and realize using NAND Gates. [5M]
    f = Σm(1, 3, 5, 8, 9, 11, 15) + d(2, 13).
    b) Simplify the following Boolean function using Tabular method. [5M]
    F(A, B, C, D)=Σm(0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
    15. a) Design 3 to 8 decoder using NAND gates? [5M]
    b) Discuss three applications of multiplexers and distinguish between a multiplexer [5M]
    and a decoder.
    16. a) What is Flip-Flop? Explain excitation tables of any four Flip-flops. [6M]
    b) What are the fundamentals of Sequential machine operations? [4M]
    17. a) Obtain the 1’s and 2’s complement of the following binary numbers [5M]
    i) 1010101 ii) 0111000 iii) 0010001 iv) 10000 v) 011000
    b) What do you mean by K-map? Name it advantages and disadvantages? [3M]
    c) Distinguish between a half-adder and a full-adder. [2M]
    18. a) Explain Master slave JK Flip-Flop with the help of neat diagram. [4M]
    b) Explain the design of ring counter using shift registers. [3M]
    c) Design a full adder using PLA. [3M]
    -- 00 -- 00 –

    Page 1 of 1

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