20a04504a Computer Architecture & Organization
20a04504a Computer Architecture & Organization
20a04504a Computer Architecture & Organization
B.Tech III Year I Semester (R20) Regular & Supplementary Examinations January 2024
COMPUTER ARCHITECTURE & ORGANIZATION
(Electronics & Communication Engineering)
Time: 3 hours Max. Marks: 70
PART – A
(Compulsory Question)
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1 Answer the following: (10 X 02 = 20 Marks)
(a) Write about register transfer notations. 2M
(b) For what reason devices generate interrupts? 2M
(c) List the four basic functions of the CPU. 2M
(d) Write the address sequencing capabilities required in a control memory. 2M
(e) Explain the conversion of octal number to hexadecimal number with an example. 2M
(f) Design an Adder to add two 4-bit numbers. 2M
(g) Explain significance of Memory hierarchy. 2M
(h) Discuss about possible modes of data transfer. 2M
(i) What is Parallel processing? 2M
(j) Describe the need for inter processor communication. 2M
PART – B
(Answer all the questions: 05 X 10 = 50 Marks)
6 Show the step by step multiplication process using booth algorithm when the following binary 10M
numbers are multiplied (+15)*(-13). Assume 5-bit registers that hold signed numbers and draw
the flow chart for the corresponding example.
OR
7 Draw and explain the addition and subtraction of floating-point numbers. 10M
8 Construct an Associative memory page table with number of words equal to the number of 10M
blocks in the main memory.
OR
9 Discuss about Set Associative mapping. 10M
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