Tema 4

Curso de Doctorado Microelectrnica analgica
Nuevas tcnicas de diseo de muy baja tensin de alimentacin
Ramn Gonzlez Carvajal Marzo, 2004

Ramn Gonzlez Carvajal 1 of 98
Low-Voltage/ Low-Power Analog Circuit Design Techniques: Roadmap

Low voltage (LV) and low-power supply circuit design techniques are addressed in this tutorial. In particular: 1. Introduction; 2. Transistor models capable to provide performance and power consumption tradeoffs; 3. Low voltage implementation techniques, such as floating gates, bulk driven and level-shifters; 4. Low Power implementation techniques like classAB circuits and operation in moderate inversion 5. LV-LP circuit implementations examples.
Motivation
The need for analog circuits in modern mixed-signal VLSI chips for multimedia, perception, control, instrumentation medical electronics and telecommunication is very high. What are the challenges in designing low voltage circuits ? - To operate with power supplies smaller than 3.3 volts - To design circuits with the same performance or better than circuits designed for larger power supplies - To perform with technologies smaller than 0.5 micron -To come with new design alternatives,
( continues)
Why are we concerned in designing low voltage circuits ? - Designers can not use conventional cascode structures, and other conventional design methodologies. - Circuits should have the same performance or better than circuits designed for larger power supplies - Circuit performance with technologies smaller than 0.5um must be better than circuits for larger technologies. -Third-generation communication applications require circuits ( and systems) with improved dynamic range over a much wider bandwidth. - New building blocks and system must be designed to satisfy the needs of portable, lighter and faster equipment
( continues)
Why dont we use two supply voltages for digital and analog? - The need for LV-LP mixed-signal circuits with only one voltage supply - The need for lower VDD digital circuits with better performaces and lower cost. - New technologies offer improved speed at lower power consumption (lower VDD): - In analog circuits lower VDD does not always mean lower power consumption - The selection of the operation region for the transistor: - Optimum selection to minimize power consumption and/or area to satisfy specs. - Typical strong and weak inversion cases not always lead to optimum designs. - Other methods to design are recommended: One equation transistor
Issues about low power supply voltage

Scaling down size technology and supply voltage does not scale linearly the VTH hat
VTH
VTH
Mister 5 volts IC
Mister 0.8 volts IC

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Ramn Gonzlez Carvajal
LV Analog Circuits
LV Problem Description:
The minimum VDD for this circuit is VT+2VDSsat We can define LV as: VTp, VTn<VDD< VTp+ VTn This means that a simple Differential pair has a very limited input signal swing with these restrictions.
Signal Range
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Threshold and VDSAT do not scale down linearly with power supply nor with smaller size technologies. Let us consider an illustrative example of a cascode and a simple inverting amplifiers, assume transistors MC and MS carry the same current IL, VT= 0.75V and
VDS(SAT)=0.2V
Keeping the same output voltage swing for both
circuits involve the tradeoffs shown in the plot of transistor sizes and GBW vs. Power Supply Voltage
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One-equation, Transistor model

Weak Inversion: mnimum of gm/ID Strong Inversion: maximum of gm/ID Moderate Inversion:
Minimum area, maximum speed and power. Minimum power, maximum area.
Optimum power-area-speed tradeoff to operate with LV and LP
C. C. Enz, F. Krummenacher, and E. A. Vittoz, An analytical MOS transistor model valid in all regions ofo peration and dedicated to low-voltage and low-current applications, Analog Integrated Circuits and Signal Processing, vol. 8, pp. 83114, 1995.
How to determine how much bias current is needed for certain application ?
When a designer operates transistors in saturation, what does it mean VDS > VDS(SAT) ? Can a circuit have their transistors operating in the transition region ? What transistor model equation can be employed ?
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One Equation-All Regions Transistor Model

Features of ACM model: physics-based model, universal and continuous expression for any inversion, independent of technology, temperature, geometry and gate voltage, same model for analysis, characterization and design. Main design equations: (design parameters: I, gm, if)
1+ I = tgmn 1+ if 2
fT =
t 2( 1 + i f 1) 2L2
gm W 1 = L Coxt 1 + i f 1
VDSAT
( 1+ i
1 + 4
I drain current in transistor gm transconductance in saturation n slope factor t thermal voltage if inversion level of the transistor defined as , where I = nC W if = I Is 2 L is the normalization current.
s ox 2 t
if << 1 weak inversion, inversion.

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W = L
gm if >> 1 strong I 2Coxt g n 1 t m Ramn Gonzlez Carvajal
A design procedure for an amplifier may consist of: Obtain the transconductance (gm) as a function of GBW and load capacitance; Determine fT from the speed specifications. Usually, fT should be 3 to 10 times larger than the GBW or the highest frequency at which the circuit operates. Obtain inversion level if from fT (Eq. (1d)), i.e. if = ((fT L2)/ (t) + 1)2 1. Derive other parameters, such as, working currents, geometry ratios, and drain-source saturation voltages from eqs. (1a), (1f), and (1e) respectively.
One Equation-All Regions Transistor Model
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Meaning of the equation for several tradeoffs
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Normalized Current
if = ID IS
Transconductance-to-Current Ratio
t ng m 2 = ID 1 + 1 + id
tgm 0 I D 10
I S = nCox
t2 W
2 L
ID: saturation current IS: normalization current n: slope factor

10
-1
( (
) theory (n=1.35) ) simulation
(o o o o o o) experiment
10
-2
10
-2
10
-1
10
10
10
10
10
WI
MI
SI
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The intrinsic cutoff frequency

fT f o 2 1 + i f 1
Drain-to-source saturation voltage

VDSsat
t fo = 2L2
10
3
( 1+ i
1 + 4
fT fo
10
VDSsat t
10
10
10
1
10
10
10
-1
10 -2 10
-2
10
-1
10
10
10
10
10
10 -2 10
10
-1
10
10
10
10
10
id
WI MI SI WI MI SI
id
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Correlation Between Area and Frequency Response
CL GBW WL 2 Cox fT
Correlation Between Junction Capacitance (CJ) and Frequency Response Parasitic capacitance GBW/fT
CJ = CJ W L DIF
LDIF W CJ
CJ CJ L DIF GBW 2 CL C L fT ox
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A comparison between BJT and MOSFET properties

BIPOLAR
IBIAS=IC
MOS
IBIAS=ID
DC Circuit
Transconductance -to-current-ratio (gm/ID) DC Gain (Avo) Gain-Bandwidth Product (GBW) Intrinsic Cutoff Frequency (fT) Minimum Output Voltage (VO)
CL + VI -
+ VO -
CL
+ VI -
+ VO -
gm 1 = IC t
gm 1 2 = I D t n (1 + 1 + i d ) A vo VA 2 = n (1 + 1 + i ) t d
2 1 ID n (1 + 1 + i ) 2CL t d
A vo =
VA t
1 IC GBW = 2CL t 1 fT 2
VCEsat 6 to 8 t
GBW =
1 fT 2( 1 + i d 1) 2 VDSsat = ( 1 + i d 1) + 4 t
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LV analog design strategies
Problem discussion. Bulk-driven transistors. Floating-gate transistors. DC level shifters. Dynamic level Shifters
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LV-LP analog design circuits Objective:

The design of cells (operational transconductance amplifiers, operational amplifier, current mirrors, etc) with following restrictions: Power Supply VSUP=VDD-VSS~VT All transistors working in saturation As mutch as possible signal range at bith input and ouptu nodes Minimum power consumption. The design of systems with these cells: Continuous-time and Discrete-Time filters. Continuous-Time and Discrete , VCO, PLL, Mixer.
Bulk-Driven MOS Transistor Characteristics

ID vs. VBS or VGS of bulk-driven and conventional gate-driven MOS 8mA transistors
6mA 1.5V ID VGS VBS 2mA Drain Current
4mA Bulk-Source Driven Gate-Source Driven
0mA -3V
-1.5V
0V
1.5V
3V
Gate-Source or Bulk-Source Voltage

Bulk-driven transistors
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Overhead of Bulk-Driven MOS Transistors

Ib1 Vx M1 Vin Vdd Vdsat,Ib1 SRVX, Swing range of Vx -Vss Vdsat,Ib1 Vb Ib2 Vout Ib1 Vy M1 Vb Vin Vin Vdd Swing range of Vy Ib2 Vout M2
M2
Vdsat,M1
(a)
VGS,M2 -Vss SRVY=Vsup-Vdsat,Ib1-VGS,M2
(b)
SRVX=Vsup-Vdsat,Ib1-Vdsat,M1
= Vsup-Vdsat,Ib1-Vdsat,M2-VT
The bulk-driven amplifier is more suitable for low voltage operation. Please notice that the maximum allowable voltage at Vx is VDIODE.
Advantages of Bulk-Driven MOS Transistors

The depletion characteristic allows zero, negative, and even small positive values of bias voltage to achieve the desired dc current. This can lead to larger input common mode voltage range and voltage swing that could not otherwise be achieved at low power supply voltages. ( Please refer the following example in this section and bulkdriven differential pair discussed in following sections ) We can use the conventional gate to modulate the bulk-driven MOS transistor. Example
Assume for the low voltage amplifiers, power supply voltage is Vsup = Vdd+|Vss|<VDIODE+Vdsat , where VDIODE is the forward Si diode cut-in voltage. The voltage swing of Vx ( Figure a, the amplifier with bulk-driven MOS FETs ) has only 2Vdsats decrease over Vsup. In such a low voltage, the conventional gate-driven amplifier ( Figure b ) fails to operate or may be greatly limited in voltage swing.
Disadvantages of Bulk-Driven MOS Transistors

The transconductance of a bulk-driven MOS FET is substantially smaller than a conventional gate-driven MOS transistor. This may result in lower GBW and worse frequency response, but better linearity and smaller power supply requirements. For a conventional gate-driven MOSFET, the frequency response capacity is described by its transitional frequency, fT, gm f T , gate driven = 2 C gs For the bulk-driven MOSFET, fT is given by g mb g m fT ,bulk driven = = 2 (Cbs + Cbsub ) 2 (Cbs + Cbsub ) where is the ratio of gmb to gm and typically has a value in the range of 0.2 to 0.4.
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For typical saturated strong inversion MOSFET operation, the following approximation stands,
fT ,bulk driven
3 .8
fT , gate driven
Another disadvantage of bulk-driven MOSFETs is that the polarity of the bulk-driven MOSFETs is process related. For an P well CMOS process, we only have N channel bulk-driven MOSFETs available, and for N well CMOS process, only P channel MOSFETs. This limits its application. We can not use bulk-driven MOS transistors in some circuit structures which requires both N and P MOSFETs.
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MOS transistors can be laid out in the same well, thus their characteristics will match better. Bulk driven transistors are in differential wells, it is inconvenient to design some circuits which require tight matching between transistors. For bulk-driven MOSFETs, it is not easy to utilize some layout techniques such as interdigitized and common centroid layout to make good matching. Potentials to turn on the parasitic BJT transistors which may result in latch-up problem The equivalent noise of a bulk-driven MOS amplifier is larger than a conventional gate-driven MOS amplifier.
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Floating Gate Transistors

The floating gate voltage VF ,assuming that the initial charge QF in the floating gate is zero,,is described by:
VF = w0V0 + w1V1+ w2V2 + .. + wnVn

Where
wi = Ci/CTOT
CTOT = C0 + C1 + C2 +.+ Cn
Metal
Poly II Poly I
VG1 VG2 VG3 S

N Diffusion
CG1 VG1 VG2 VGn CGn CG2
CFGD
VG1 VG2 VGn D
CFGS CFGB (b) Schematic Symbol (c) Equivalent Circuit

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(a) Layout
Floating Gate MOS Transistors

CG (control Gate) Poly - II Cg Poly - I CO = Cgs + Cgb + Cgd S D CT= CO + Cg
Assuming Cg >> Cgd,Cgb, an approximate IDS can be obtained: IDS=Koeff [( VCGS-VT,eff)VDS-CT VDS2/2Cg] IDS =Kseff ( VCGS-VT,eff)2 Where:
VT,eff =VTCO - QFG/Cg
ohmic saturation
Koeff = Kp(Cg/CT)(W/L),
Kseff =Kp(Cg/CT)2(W/L),
What is the effect of the FG on the transconductance and the output conductance, in the saturation region ?
gm = ( 2K2eff IDS)2 = Cg gcm/CT go = gco + Cgd gm/Cg

Where gcm and gco are the conventional transconductance and the output conductance of the conventional MOS transistor.
Thus, the FGT has a smaller transconductance and a larger output conductance than conventional MOS transistor
Multiple Input Floating Gate MOS D/A Converter

Basic idea
We know that the floating gate voltage VFG is a weighted sum of the multiple inputs, it is possible to read out the VFG. We can utilize the characteristic of floating MIFG MOS transistors to build D/A converters. Practically, we can have a good matching property of capacitors in conventional CMOS processes. These are the starting point of realizing a MIFG MOS D/A converter. It is possible to realize a n-bit D/A converter using one floating gate MOS transistors as shown below. The main problem of this implementation is that the larger of n, the larger ratio of the biggest capacitor CGn-1 over CG0. That is Bit n-1
M1 Bit 1 Bit 0 Vo Ib
CGn 1 = 2 n 1 CG 0
Multiple-Input Floating Gate MOS Transistors

How about to realize several small D/A converter with fewer bits, such as 3 to 5 bits, and then add the outputs of these small D/A converters together by different weights, as shown in the following diagram ( a 8-bit D/A converter ).
The weights
bit_7*Vref bit_6*Vref bit_5*Vref bit_4*Vref
2-1 2-2 2-3 2-4 2-1 2-2 Vout
bit_3*Vref bit_2*Vref bit_1*Vref bit_0*Vref
2-1 2-2 2-3 2-4

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Multiple-Input Floating Gate MOS Transistors

The circuit
bit_3*Vref bit_2*Vref bit_1*Vref bit_0*Vref Vset1 bit_7*Vref bit_6*Vref bit_5*Vref bit_4*Vref Vset2 Vdd
M1
Ib
M2
Vset3
M3
Vb
Vout
M4 M5
M6 M7
M8 M9
M10 M11
-Vss
Vset1~Vset3 are used to tune the zero point of the D/A converter.
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Example of OTAs using different approaches: Conventional, Floating Gate, and Bulk Driven
GM VIN IOUT 1.2 AMI Technology Vdd=-Vss= 1.35V RBIAS IBIAS VBIAS
VOUT = GMROUTVIN
VDD
ROUT = 8.3 Mohms

M7 M9 M10 M8
VOFFSET
ISS VSS Vout
ViM5
M1 M3
M2 M4
Vi+ M6
EXPERIMENTAL TEST SETUP

VSS
DESIGN A - REFERENCE OTA
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DESIGN A - REFERENCE OTA
Input Ch1 160mVpp @ 1 Hz Output Ch2 18mVpp
THD ~ -28dBm ~ 3.9% @160mVpp, 1Hz

DESIGN B - CURRENT DIVISION OTA and Source Degeneration

VDD
M9 M10 M4 M3 M11
M12
ISS VSS MM1
M14
M15
Vi-
M1 M16
M2
MM2 Vi+
Vout
VDD ISS
M8
M6
M17
M18
M5
M7
VSS Ramn Gonzlez Carvajal
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DESIGN B - CURRENT DIVISION and SD OTA
Input Ch1 214mVpp @ 1 Hz Output Ch2 16mVpp
THD ~ -30dBm ~ 3.2% @214mVpp, 1Hz

DESIGN C - FLOATING GATE OTA, plus SD and CD
VDD M8 M9 ISS VSS MM1 M1 M2 Vb MM2 Vout ViM5 M3 M4 VSS

M7 M10
Vi+ M6
DESIGN C - FLOATING GATE OTA
Input Ch1 214mVpp @ 1 Hz Output Ch2 15.2mVpp
THD ~ -34dBm ~ 2% @214mVpp, 1Hz

DESIGN D - BULK DRIVEN OTA, PLUS CD AND SD

VDD M8 M9 ISS VSS MM1 M1 M2 VG MM2 Vout ViM5 M3 M4 VSS
M7 M10
Vi+ M6
DESIGN D - BULK DRIVEN OTA
Input Ch1 214mVpp @ 1 Hz Output Ch2 15.2mVpp
THD ~ -39dBm ~ 1.1% @214mVpp, 1Hz

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SIMULATION VS EXPERIMENTAL RESULTS

1.2 micron CMOS Technology
SIMULATED RESULTS EXPERIMENTAL RESULTS
PAR \ DES A B C D A B C D GM (nA/V) 11.6 11.55 11.51 11.24 10.5 9.3 8.7 8.8 @ 1Hz 0.1 0.098 0.047 0.025 <1 <1 <1 <1 () Offset (mV) 0.07 0.027 -0.086 0.045 -1.8 -1.9 -1.5 0.647 THD (%) 1@162 1@240 1@330 1@900 3.9@160 5.6@242 3.2@330 5.9@900 mVpp mVpp mVpp mVpp mVpp mVpp mVpp mVpp THD (%) @ 3.9 3.2 2 1.1 214mVpp IBIAS(nA) 2 100 200 500 4 120 230 560 VDD= |V | 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 SS (V) BIAS (V) N/A N/A -1.35 -1.35 N/A N/A -1.35 -1.35
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References
1. C. Galup-Montoro, etc., Series-Parallel Association of FETs for High Gain and High Frequency Applications, IEEE JSSC, Sept. 1994 2. D. Ceuster, etc., Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors, Electronics Letters, Feb. 1996 3. P. Furth, H. Ommani, A 500-nW Floating-Gate Amplifier with Programmable Gain, IEEE 1999 4. I. Fujimori, T. Sugimoto, A 1.5V, 4.1mW Dual-Channel Audio Delta-Sigma D/A Converter, IEEE JSSC, Dec. 1998 5. Personal note from Dr. Ugur Cilingiroglu 6. Yunchu Li, examples and SPICE tables 7. A.I.A. Cunha, M.C. Schneider, and C. Galup-Montoro, An MOS transistor model for analog circuit design, IEEE J. Solid-State Circuits, vol. 33, No. 10, pp 15101519, Oct. 1998
Quasi floating gate circuits

v1 v2
N-well
Source Drain To Vss
Poly I Poly II Active Metal Contact
Gate capacitively coupled to signals V1,V2,Vn Gate connected to supply rail using a very large valued resistor Rlarge sets quiescent gate voltage to the supply rail voltage and minimizes supply requirement Rlarge implemented using reverse biased PN junction
vn (a) v1 v2 C1 C2 Cn vn VSS vG Cgs vs Cgb vb C'gd Cgd
Rleak
vd
(b)
QFG PMOS transistor: a) Layout b) Equivalent circuit

Quasi floating gate circuits

Advantages
No charge trapped as in true floating gate transistors Well defined gate quiescent voltage at supply rail minimizes circuits supply requirements Input signals can have arbitrary DC components
Drawbacks
Rlarge forms high pass circuit with signal coupling capacitors swing at junction implementing Rlarge must be limited to avoid forward biasing the junction PN junction nonlinear can introduce distortion for gate swings
Level shifters
DC Level shifting techniques can be used to reduce the effective threshold voltage of MOS transistors
a) Conventional Cascode mirror: Vin=2VGS= 2Vth+2VDSsat; Vout=VGS+VDSsat=Vth+2VDSsat Vtotal=Vin+Vout=3Vth+4VDSsat b) Cascode mirror with DC level shifters Vin=2VTH+2VDSsat-2Vb; Vout=Vth+2VDSsat-Vb Vtotal=3Vth+4VDSsat-3Vb=3VTH+4VDSsat Where: If VTH=VTH-Vb Vb=VTH then VTH= 0 Then Vtotal= 4VDSsat (<1V)
DC Level shifting equivalent to reduction of effective threshold voltage!

"Current mirrors with low input voltage requirements for built in current sensors," J.
Ramrez-Angulo, 1994 IEEE ISCAS, pp. 529- 532, London, England, May 30- June 2, 1994 Ramn Gonzlez Carvajal 46 of 98
Floating level shifters

A Vb A B
Ip
In
A
I
A
+ Vb _
In
+ Vb _
Ip
+ Vb _
I
B
(a)
I1
(c)
1 2
A
B Vb
C
B
I1+ I2
(d)
(e)
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Additional Implementations of DC level shifters
Floating levels shifters

Remarks: One of the terminals of the floating voltage source requires to be connected to a circuits high impedance node, the other terminal to a low impedance node. Above circuits can be used to implement both static and dynamic floating sources
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Floating level shifters

Examples: Class AB CMOS inverters with VDD<VthN+|VthP|
I
Vb
Vout Vout Vout
Vb
Rb
(a)
(b)
(c)
(a) Low-Voltage CMOS inverter using Floating voltage sources (b)Resistor-current source implementation (c) switched implementation
Dynamic floating voltage sources

Principle: Rearrange non-inverting configuration by inserting a source Vs in series between output and negative op-amp input terminals and connecting the positive terminal to one of the supply rails
"Low-voltage CMOS amplifiers with wide input-output swing based on a novel scheme, J. Ramrez-Angulo, A Torralba, R.G. Carvajal and J.Tombs, IEEE Transactions on Circuits and Systems-I, vol. 47, No. 5, May 2000, pp. 772-774.
a) Op-amp in voltage follower configuration. b) Grounding the op-amp input and inserting a FVCVS in the feedback path c) implementation of FVCVS with resistor and current sources Ramn Gonzlez Carvajal 50 of 98
Practical implementation of the FVCVS: a) STEP 1: Voltage-to-current conversion using transresistance amplifier. b) STEP 2: Current-to-voltage conversion inserting the FVCVS in the feedback path of the main operational amplifier OA.
Vref
OA
A'
Q (A-1)*I b
Vout
A*Ib
A
R
A*Ib
B
Q (A-1)*I b
B'
Implementation of an amplifier with gain A using the FVCVS technique. This circuit replaces the circuit in figure b above. Ib and Ib Q are obtained using two copies of the circuit in figure 2a, with inputs Vs and Vs Q, respectively.
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Dynamic floating voltage sources

Vs STAGE 1 V b = f(Vs) Vref TRANSCONDUCTANCE AMPLIFIER STAGE 2 FLOATING TRANSIMPEDANCE AMPLIFIER V2 V1
D Vs Ib Vref k*I b V1
Rb
Ib
DA
Vc
Rb n V2 k*I b
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Applications: Operational Amplifiers

Basic Element Input Differential Pair Output Stage Output Quiescent Current Control
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AO: Architecture
M in1
Idp Rc Cc Vout
M in2
Output Stage (figure 2a or 3)
X
Idp 2
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AO: Output Stage

Ib V o ViN M2 ViP M2 ViN M1 V o ViN M2 ViP M1 V o
a)
b)
c)
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AO: Output stage

M1 Vi M2 V o Vb Vi M2 M1 V o
a)
b)
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AO: Architecture
Idp M1 ViM2 Vi+ Vb Idp/2 VDD
Vy
Moutp Vo Moutn
Vx
Rc Cc
GND
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AO: Output stage

R in series configuration
Improves with Cbp High output impedance current sources are needed
Ir Y VAB + X Ir M outn R V M outp
R with high-resistive poly Parasitics are very important
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AO: Quiescent current control

I2 = I1 M2 I 'r V2 V1 + DA R' + I 'r VAB
M1
I1
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AO: Quiescent current control

I2 = I1 M2 R' Y VAB + X M outn R Vout M outp
Ic
Q V1 =VX
M1
I1
Ic 2
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AO: quiescent current control

IM outp IM outn
Vout
VX
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AO: Input Stage FG

C1 Vi C1 V Ccm C1 Ccm Vi n
FGi-
Ccm VFGi+ Vout C1 Ccm Vout
Vi +
(a)
C2 C1 Ccm C1 Vi + Ccm Vout Vin + Vout+ Vin C1 Ccm C1 Ccm C2
(b)
Vi -
Vout+
Vout -
(c)
(d)
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AO: Input Stage FG
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AO: Input Stage FG
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AO: Input Stage FG

Simulation Minimum VDD Input Range Output Range Offset DC Gain Phase Margin GB PSRR CMRR THD (100 kHz) Slew Rate Peak output Current 1.15 V 1.2 V 1.2 V 0.2 mV 60 dB 70
o
Experimental 1.1 V 1.2 V 1.2V 1 mV 70o 5 MHz 0.1 % 7 V/s -
VDD W/L (M1, M2) W/L (Mb) W/L (Moutn) W/L (Moutp) Idp IoutQ RC CC CL
1.2 V 2000/2 350/2 600/2 1800/2 100 A 30 A 600 30pF 50 pF
5 MHz 40dB 47 dB 0.09 % 7 V/s 0.8 mA
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AO: Common Mode FG

Vout+ C VoutVa
_ +
Cm
Vcntcm
VDD M1 ViVb
Idp M2 Vi+ Vb
VDD
Cm Va' Vrefcm
_ + + _
Moutp
Vo-
Moutp
Moutn
Vo+ Moutn
(a)
Ibias1 3 1
Vcntcm
Cc Rc
GND
Vcntcm
Mcm
Rc Cc
GND GND
Ibias2 M3 M4 2 MLS Ibias1/2 3
(b)
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Input stage: BE
R2 R1
Vb
OPA2
+
R2
R1
Ib
Rb
- OPA2
Ib
+
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Input Stage: BE
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Input stage: BE
Simulation Minimum V DD Input Range Output Range Offset DC Gain Phase Margin GB PSRR CMRR THD (100 kHz) Slew Rate Peak output Current 1.15 V 1.2 V 1.2 V 0.2 mV 60 dB 70 o 10 MHz 40dB 47 dB 0.09 % 7 V/s 0.8 mA Experimental 1.15 V 1.2 V 1.2V 1 mV 65
VDD W/L (M1, M2) W/L (Mb) W/L (Moutn) W/L (Moutp) Idp IoutQ RC CC CL
1.2 V 2000/2 350/2 600/2 1800/2 100 A 30 A 600 30pF 50 pF
9 MHz 0.1 % 7 V/s -
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Input Stage: BD
Ib
A
Vref
C
A
Vref
DA
OA
R
Ib
B
Vout
Ib
A
Vs
R
Ib
Vcn
B
(a)
( b)
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Input Stage: BD
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AO: Quiescent Current Control

V CM-ADJ
M in1
Idp Rc Cc Vout
+
Vin Idp 2
M in2
Output Stage (figure 1c or 1d)
CL
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S1 M1 V1 S3 Vy M outp
I Moutp
Ib Ca Cb Vout
I M outp
I M outn
Ib
I Moutn
Vx V2 S2 S4 M outn
VX
M2
Vout
IM outp
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M b1 M b2 M outp Vout Vz M b3 Vy X Cy Cx M outn
Ib
IM outp
IM outn
Vout
VX
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Units DC Gain Phase Margin Unity Gain fequency Quiescent output current Supply current PSRR CMRR THD (1kHz) VCM-ADJ * Slew Rate * Peak output Current * DB Deg MHz (A) (A) dB dB dB mV V/s A Output Stage of figure 1c 70 dB 70o 15 MHz 75 290 40dB 47 dB 65 600 12 400 Output Stage of figure 1d 60dB 75o 18 MHz 200 900 35dB 54dB 60 900 6 2000
Units VDD Moutn Moutp M1(Mb1/Mb2) M2 (Mb3) Min1, Min2 Idp Ib Ca (CX) Cb (CY) V W/L W/L W/L W/L W/L A A pF pF
Output Stage of figure 1c 1.5 100/1 300/1 30/1 10/1 500/1 200 7.5 2 1
Output Stage of figure 1d 1.8 720/1 2000/1 2000/1 720/1 500/1 200 200 6 2.6
(CL=10pF, VDD=1.4, CC=10pF, RC=500,). (*) Transient response, 0.3V peak square input signal
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Low-Voltage amplifiers using DC floating sources

Applications:
Low-voltage continuous-time amplifiers based on inverting opamp configuration (Assume single supply voltage VDDand signal Vin=Vs(t)+VDD/2)
Approach:
Keep both input terminals of op-amp closte to one of the supply rails by Inserting a floating DC source with value Vbat=VDD/2 in series with negative op-amp input.
"A simple technique for low-voltage op-amp operation in continuous-time," J. Ramrez-Angulo, A Torralba, R.G. Carvajal and J.Tombs, IEE Electronics Letters, vol. 35, No. 4, February 18th, 1999, pp. 263-264
R2
RF
R1 VDD/2
Vin
Vin
R1 VDD/2
R1
_ +
Vout
_
I
+ Vin _
Vout I
R2
+ _
Vbat
_
Vout
_+
R1 RF
(a)
(b)
(c)
Low voltage amplifier based on DC floating sources (a) Standard inverting configuration (b) wideband constant bandwidth configuration based on current sensing c) Fully differential version of circuit of Fig. a
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V. Low voltage class AB two stage CMOS operational

Icnt
Vi-
Vi+
Vb
+
Vo
Vout
(a)
Icnt Ib Icnt
Vb
Vi-
Vi+
+_
Vb
_
Vout
Vo-
Vo+ Ib
_+
Basic scheme of low voltage two stage class A/AB op-amp based on inverted battery technique: (a) Single ended scheme, (b) fully differential scheme.
Ib Icnt
(b)
"Class AB output stage for low voltage CMOS op-amps with accurate quiescent current control," Torralba, R.G Carvajal,J. Martinez-Heredia and J. Ramirez-Angulo, Electronics Letters, vol. 36, No. 21, 12th October 2000, pp. 1753-1754. Ramn Gonzlez Carvajal
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IIIa. Multiple Input Floating Gate Transistors

v1 v2
Poly I Poly II Active Metal Contact N-well
Source Drain
vn
(a) Cgs vFG
vs v1 v2 vn vd (b)
v1 v2
C1 C2 Cn
vs Cgb vb
vn (c)
Cgd
vd
Multiple Input Floating Gate Transistor: (a) Layout (b) symbol (c) equivalent circuit model.
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IIIa: Multiple input floating gate transistors

Low voltage operation using multiple input floating gate transistors
Floating gate voltage (VFG) in a MIFG transistor is a linear weighted addition of control input voltages V1, V2, Vn
VFG = (C1V1+C2V2 )/(C1+C2)= (VinC1+VbiasC2)/(C1+C2) Vbias for C2>>C1 Basic principle for low voltage operation: Use one terminal for biasing purposes (to set VGQ close to one of the supply rails) and the remaining terminals for signal injection
"Low-Voltage OTA architectures Using Multiple Input Floating gate Transistors," J. Ramrez-Angulo, S.C. Choi, G. GonzalezAltamirano, IEEE Transactions on Circuitsand Systems, vol. 42, No. 12, pp.971-974, November 1995
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IIIa: Multiple input floating gate transistors

Differential voltage in floating gate differential pair: VFGd = Vd1 a1 + Vd2 a2 +..+ Vdn an VFGd = VFG1-VFG2, Vdi=Vi1-Vi2, ai=Ci/(C1+C2+..+Cn)
VFG1Q=VFG2Q= Vbias [Cbias/(Cbias+C1+C2)]=Vbias Vdd Reduced threshold voltage + Linear combination of differential control voltages allows for great design flexibility [2]
"MITE Circuits: The Continuous time counterpart to switched capacitor circuits," Jaime Ramirez-Angulo and Antonio Lopez, IEEE Transactions on Circuits and Systems, special issue on applications of floating gate transistors, vol. 48, No. 1, February 2001
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IIIa: Floating gate transistors
Single ended two input case C1 C2 VG = VBIAS + Vin C1 + C 2 C1 + C 2 Effective threshold voltage
C1 Vth' = Vth VBIAS C1 + C 2

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IIIa. Example of Low voltage CMOS inverter using FG transistors
Vb1
Vin
Vout
Vb2
Low voltage CMOS Inverter with programmable gain and threshold

"Modeling Multiple-Input Floating Gate Transistors for Analog Signal Processing," J. Ramrez-Angulo, G. GonzalezAltamirano and S.C. Choi, IEEE International Symposium on Circuits and Systems, Hong Kong, June 9-12, 1997
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1.2 V MIFG Rail to Rail op-amp
"Low-voltage CMOS Op-amp with rail-to-rail signal swing for continuous-time signal processing using multiple-input floating-gate transistors," J. Ramirez-Angulo, R. G. Carvajal, J. Tombs, and A. Torralba, IEEE Transactions on Circuits and Systems, Vol. 48, No. 1, Jan. 2001, pp. 110-116
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IIIa. Floating gate transistors

Drawback:
Vn+ Cn
V1
Ib
C1 Vn-
C1 C2 C3
V2 V3 Clarge
+ + + + _ Vout
V1+ C1 C1
V1-
Charge trapped in floating gate can lead to large (temperature dependent) DC offsets** Clarge forms voltage divider with feedback elements CF=Ctotal-Clarge Effective gain-bandwidth product Of floating gate circuit is reduced by relatively large factor K= Clarge/(Ctotal-Clarge)
C3
Clarge Clarge
C2 C1
_ _
_
Vbias
(a)
(b)
+ _
CF=Ctotal-Clarge Clarge
(c)
(a) MIFG low-voltage differential pair (b) MIFG low-voltage summing amplifier (c) Analysis of gain-bandwidth product
Solution to trapped charge in floating gate transistors,E. Rodriguez-Villegas, H. Barnes, Electronics Letters, 8th September 2003 Vol. 39 No. 19
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IIIb. Open loop applications of QFG Transistors

RL + VOUT RL
C VIN1+ C VIN2+ M1 M2
C VIN1C VIN2+ VIN2M5 (a) VIN1-
C C M3 M4
C C
VIN1+ VIN2-
VBIAS
4IBIAS
MRlarge2 C1 Vclk Vin MRlarge1 Vclksh MpassN (b) Vclkn C2 Vclknsh MpassP Vout Chold
a) Low-voltage QFG mixer (b) Low voltage rail to rail sample and hold using QFG switch
1. 2. A New Analogue Switch for Very Low Voltage Applications, F. Muoz, J. Ramrez-AnguloLopez-Martin R.G. Carvajal A. Torralba1 B. Palomo and M. Kachare, IEE Electronics Letters, May 2003; v.39, no.9, p.701-702. A new Family of Low-Voltage Analog Circuits Based on Quasi Floating Gate Transistors, J. Ramirez-Angulo, C. Urquidi, R.G. Carvajal, A. Lopez-Martin, IEEE Transactions on Circuits and Systems, II v. 50, No. 5 May 2003, pp. 214-220
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IIIb. Closed loop applications of QFG transistors

SWN ANC SW3 A3C QFGMOS1 C
VI+ SW2 A2C

SW1 A1C SWN ANC SW3 A3C
_ + _ +
C QFGMOS2
VO+
VO-
VI-
SW2 A2C SW1 A1C
Digitally programmable gain QFG amplifier

Very Low Voltage Analog Signal Processing Based on Quasi-Floating Gate Transistors, J. Ramirez-Angulo , A. J. LpezMartn , R. G. Carvajal , and F. Muoz , IEEE Journal of Solid State Circuits, February 2004 (in print) Ramn Gonzlez Carvajal
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LV Transconductors
R
v in
I in
1 + G= R -
I in
LOW- VOLTAGE DIFFERENTIAL CURRENT-MODE SIGNAL PROCESSOR
I OUT
Vdd 2
-Vout
I OUT
+Vout
Current mode signal processing circuits: A possible solution to LV design Need for a V/I transducer cell Need for a I/V transducer cell
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LV OTA
Vctrl
M1P M 1PP
Itop=I+
V in
Iin=0 Ibottom =I+

M2
DA +
I +=Iout
V ref
M2P
VIN
I+
+
BT I -= -Iout
M 2PP
1 G= R
I-
Vin=Vs+Vcm
I=Itop=Ibottom=(Vin-Vref)/R=(Vs+Vcm-Vref)/R Iout =Is+Icm ; Is=Vs/R ; Icm=(Vcm-Vref)/R

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LV OTA
vin
Iin BT
1 G= R
+ -
I o+ IovIN
Iin
I o+ SET +
vcm
Icm '
+ -
Io-
BT
Icm '
Common mode components cancellation
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LV OTA
vin + 1 vin Io+ BT
+ -
I o-
BT
+ -
vin + vin - 2
1
Io+
+ -
FDT
I o-
G=
1 R
Differential version Intrinsic common mode components cancellation

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LV OTA
vIN+ vIN+ FDT 1 G= R + RL RL -
vo vo +
2 RL Ad = R
Applications: LV Instrumentation amplifier Resistors R y RL can be matched with high accuracy

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LV OTA
Applications: Common mode control in Operational Amplifiers.
vo+
3 4 vCM
(a)
I Vo+
BT
+ Moutp VDD
+ _
_ +
4 3
CM
CONTROL
CMFN
v
Idp M1 ViVb Moutn M2
VDD
vo-
BT
+ -
I Vo- v
CM
vo-
Moutp Vi+ Vb
CONTROL
vo+
Moutn
Cc
Rc
MCM
GND
Rc
Cc GND
vdesCM
BT
+ -
GND
I CM
COMMON-MODE FEEDBACK NETWORK
(b)
FULLY DIFFERENTIAL OP-AMP
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LV OTA
7.5 DC TRANSFER CURVES (uA) 5.0 2.5 0 -2.5 -5.0 -7.5 -600 -300 0 300
Io+
dB(Io+) (dB)
-90 -100
Cursor 1:
-110 -120 -130 -140
FREQ=41.547869E6 IDB(RL1)=-103.18864
Io600
dB(Io+)
10e3 10e6 FREQUENCY (Hz) 10e9
VIN1 (mV)
DC Characteristic
AC Characteristic
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LV OTA
Experimental DC characteristic
Experimental transient response for different RL (f=100kHz)

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LV OTA
Output spectrum: THD < 1%
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References
[1] [2] J. H. Huijsing, and D. Linebarger, Low voltage operational amplifier with rail-torail input and output stages, IEEE Journal of Solid-State Circuits, vol. SC-20, no. 6, pp. 1144-1150, December 1985 W.-C. S. Wu, W. J. Helms, J. A. Kuhn, and B. E. Byrkett, Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges, IEEE Journal of Solid-State Circuits, vol. 29 , no. 1, pp. 63-66, January 1994 R. Hogervorst, R. J. Wiegerink, P. A. L. de Jong, J. Fonderie, R. F. Wassenaar, and J. H. Huijsing, CMOS low-voltage operational amplifiers with constant-gm railto-rail input stage, IEEE Proc. ISCAS 1992, pp. 2876-2879 R. Hogervost, J. P. Tero, R. G. H. Eschauzier and J. H. Huijsing, A compact power-efficient 3-V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries, IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp. 15051513, December 1994 R. Hogervorst, S. M. Safai, and J. H. Huijsing, A programmable 3-V CMOS railto-rail opamp with gain boosting for driving heavy loads, IEEE Proc. ISCAS 1995, pp. 1544-1547 J. H. Huijsing, R. Hogervorst, and K.-J. de Langen, Low-power low-voltage VLSI operational amplifier cells, IEEE Trans. Circuits and Systems-I, vol. 42. no. 11, pp. 841-852, November 1995
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[3]
[4]
[5]
[6]
References ( contd )
[7] W. Redman-White, A high bandwidth constant gm, and slew-rate rail-to-rail CMOS input circuit and its application to analog cell for low voltage VLSI systems, IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp. 701-712, May 1997 [8] C. Hwang, A. Motamed, and M. Ismail, LV opamp with programmable rail-torail constant-gm, IEEE Proc. ISCAS 1997, pp. 1988-1959 [9] C. Hwang, A. Motamed, and M. Ismail, Universal constant-gm input-stage architecture for low-voltage op amps, IEEE Trans. Circuits and Systems-I, vol. 42. no. 11, pp. 886-895, November 1995 [10] R. Hogervost, J. P. Tero, and J. H. Huijsing, Compact CMOS constant-gm rail-torail input stage with gm-control by an electronic zener diode, IEEE Journal of Solid-State Circuits, vol. 31, no. 7, pp. 1035-1040, July 1996 [11] M. Wang, T. L. Mayhugh, Jr., S. H. K. Embabi, and E. Snchez-Sinencio, Constant-gm rail-to-rail CMOS op-amp input stage with overlapped transition region, IEEE Journal of Solid-State Circuits, vol. 34, no. 2, pp. 148-156, February 1999 [12] G. Ferri and W. Sansen, A rail-to-rail constant-gm low-voltage CMOS operational transconductance amplifier, IEEE Journal of Solid-State Circuits, vol. 32, no. 10, pp. 1563-1567, October 1997
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References ( contd )
S. Sakurai and M. Ismail, Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage, IEEE Journal of Solid-State Circuits, vol. 31, no. 2, pp. 146156, February 1996 [14] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, Simple rail-to-rail low-voltage constant transconductance CMOS input stage in weak inversion, Electronics Letters, vol. 29, no. 12, pp. 1145-1147, June 1993 [15] V. I. Prodanov and M. M. Green, Simple rail-to-rail constant transconductance input stage operating in strong inversion, IEEE 39th Midwest Symposium on Circuits and Systems, vol 2, pp. 957-960, August 1996 [16] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, A low voltage CMOS op amp with a rail-to-rail constant-gm input stage and a class AB rail-to-rail output stage, IEEE Proc. ISCAS 1993, vol. 2, pp. 1314-1317, May 1993 [17] J. F. Duque-Carrillo, J. M. Valverde, and R. Perez-Aloe, Constant-gm rail-to-rail commonmode range input stage with minimum CMRR degradation, IEEE Journal of Solid-State Circuits, vol. 28, no. 6, pp. 661-666, June 1993 [18] A. L. Coban and P. E. Allen, A low-voltage CMOS op amp with rail-to-rail constant-gm input stage and high-gain output stage, IEEE Proc. ISCAS 1995, vol. 2, pp. 1548-1551, April-May 1995 [19] J.F.Duque-Carrillo et al, 1-V Rail-to-Rail Operational Amplifiers in Standard CMOS Technology IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 33-44, January 2000
[13]
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Curso de Doctorado Microelectrnica analgica

Nuevas tcnicas de diseo de muy baja tensin de alimentacin

Ramn Gonzlez Carvajal Marzo, 2004

Low-Voltage/ Low-Power Analog Circuit Design Techniques: Roadmap

Issues about low power supply voltage

Mister 0.8 volts IC

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Keeping the same output voltage swing for both

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One-equation, Transistor model

Optimum power-area-speed tradeoff to operate with LV and LP

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One Equation-All Regions Transistor Model

if << 1 weak inversion, inversion.

gm if >> 1 strong I 2Coxt g n 1 t m Ramn Gonzlez Carvajal

One Equation-All Regions Transistor Model

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Meaning of the equation for several tradeoffs

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ID: saturation current IS: normalization current n: slope factor

) theory (n=1.35) ) simulation

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The intrinsic cutoff frequency

Drain-to-source saturation voltage

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Correlation Between Area and Frequency Response

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A comparison between BJT and MOSFET properties

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LV analog design strategies

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LV-LP analog design circuits Objective:

Bulk-Driven MOS Transistor Characteristics

6mA 1.5V ID VGS VBS 2mA Drain Current

4mA Bulk-Source Driven Gate-Source Driven

Gate-Source or Bulk-Source Voltage

Ramn Gonzlez Carvajal

Overhead of Bulk-Driven MOS Transistors

VGS,M2 -Vss SRVY=Vsup-Vdsat,Ib1-VGS,M2

Advantages of Bulk-Driven MOS Transistors

Disadvantages of Bulk-Driven MOS Transistors

Ramn Gonzlez Carvajal

Disadvantages of Bulk-Driven MOS Transistors

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Disadvantages of Bulk-Driven MOS Transistors

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Floating Gate Transistors

VF = w0V0 + w1V1+ w2V2 + .. + wnVn

VG1 VG2 VG3 S

CG1 VG1 VG2 VGn CGn CG2

VG1 VG2 VGn D

CFGS CFGB (b) Schematic Symbol (c) Equivalent Circuit

Floating Gate MOS Transistors

gm = ( 2K2eff IDS)2 = Cg gcm/CT go = gco + Cgd gm/Cg

Multiple Input Floating Gate MOS D/A Converter

Multiple-Input Floating Gate MOS Transistors

bit_7*Vref bit_6*Vref bit_5*Vref bit_4*Vref

2-1 2-2 2-3 2-4 2-1 2-2 Vout

bit_7Vref bit_6Vref bit_5Vref bit_4Vref

bit_3Vref bit_2Vref bit_1Vref bit_0Vref