System Buses

Review 2
 describe computer functions
– fetch and execute cycles
– interrupts
– multiple interrupts
– I/O function

Lecture 3. Dr. B.Kovalerchuk 2

 Bus Interconnection
 bus structure
 multiple bus hierarchies
 elements of bus design

Lecture 3. Dr. B.Kovalerchuk 3

 Bus Interconnection

 Define bus. Bus - communication pathway

connecting two or more devices.
 Describe a key characteristic of a bus
 A shared transmission medium. Multiple devices
connect to the bus, and a signal transmitted by any
one device is available for reception by all other
devices attached to the bus.

Lecture 3. Dr. B.Kovalerchuk 4

 Bus structure
 Define a system bus
 A bus that connects major computer components
(CPU, memory, I/O ) One or more system buses
may be used.
 Describe types and number of bus lines
 50 to 100 separate lines.
 data, address, and control lines.

 power distribution lines.

Lecture 3. Dr. B.Kovalerchuk 5

 What is the typical width of a data bus?
 8, 16, or 32 separate lines.
 How many bits each line carries at a time?
 1 bit
 What is the key factor determining overall system
performance?
 The width of the bas

Lecture 3. Dr. B.Kovalerchuk 6

 Which device puts the address of the desired data on the
address lines?
 CPU
 What determines the maximum possible memory?
 The width/length of the address
 What is the typical function of the higher-order bits?
 To select a particular module.
 What is the typical function of the lower-order bits on the
bus?
 To select a memory location or I/O port within module

Lecture 3. Dr. B.Kovalerchuk 7

 What is the function of control line?
 To control the access to data and address lines, because data
and address lines are shared by all components.
 What do control signals transmit?
 Command information
 Timing information, indicating the validity of data and address
information

Lecture 3. Dr. B.Kovalerchuk 8

 Describe elements of typical control lines
 Memory Write, Memory Read,
 I/O Write, I/O Read,

 Transfer ACK (Acknowledge),

 Bus Request, Bus Grant,

 Interrupt Request, Interrupt ACK,

 Clock, Reset.

Lecture 3. Dr. B.Kovalerchuk 9

Describe operations of the bus
 To send data:
(1) obtain the use of the bus
(2) transfer data via the bus
 To request data
(1) obtain the use of the bus
(2) transfer request to the other module.
(3) wait for second module to send the data.

Lecture 3. Dr. B.Kovalerchuk 10

 Read Memory
Write Data
N Words
Instruc- Control
Address 0 tions Signals
CPU
Data N-1 Data
Data
Interrupt
Read Signals
Write Internal
I/O Module Data
Address
Internal M Ports External
Data Data
External Interrupt
Data signals

Lecture 3. Dr. B.Kovalerchuk 11

 Does an I/O module controls only one external device?
 May control more than one device.
 What is the name of the interface to an external device?
 Port
 Does a port have an unique address?
 Yes

 May I/O module be able to send interrupt

signals to the CPU?
 Yes

Lecture 3. Dr. B.Kovalerchuk 12

 Is the I/O module allowed to exchange the data
directly with memory without going through the
CPU?
 Yes
 What is the name of a mechanism for that?
 Direct memory access(DMA).
 What is the most common interconnection
structure?
 The bus, and various multiple-bus structures.

Lecture 3. Dr. B.Kovalerchuk 13

 What is the reason for
Multiple-Bus Hierarchies?
 Situation:
– More devices connected to the bus
– Rapid growth of data rates generated by attached devices
(graphics and video controllers, network interfaces)
 Problems -- bus is a bottleneck for performance:
– Greater propagation delay
 time for devices to coordinate the use of the bus.
 frequent pass of control from one device to another.
– Insufficient capability of the bus
 Solutions:
– increase the data rate that the bus can carry
– wider buses
– multiple buses (generally laid out in a hierarchy).

Lecture 3. Dr. B.Kovalerchuk 14

 What is the traditional bus
architecture ?
 Local bus
– connects the processor to a cache memory
– supports one or more local devices.

 The cache memory controller

– connects the cache to this local bus
– connects to a system bus (to which is attached
all of the main memory modules)

Lecture 3. Dr. B.Kovalerchuk 15

 Traditional Bus Architecture
 Cache structure insulates the processor from
a requirement to frequently access main
memory
 Frequently access main memory moves off
of the local bus onto a system bus.
 I/O transfers to and from the main memory
across the system bus do not interfere with
the processor’s activity.
Lecture 3. Dr. B.Kovalerchuk 16
 Traditional Bus Architecture
 I/O controllers <-> expansion bus <->
system bus.
 An expansion bus interface buffers data
transfers between the system bus and the
I/O controllers on the expansion bus.
 This solution allows us to insulate memory-
to processor traffic from I/O traffic.

Lecture 3. Dr. B.Kovalerchuk 17

 Traditional Bus Architecture
Local Bus
Processor Cache buffer

Local I/O
controller
Main
Memory

System Bus

Expansion buffer
Bus Interface Serial
Network

Modem I/O controllers

Expansion Bus
Lecture 3. Dr. B.Kovalerchuk 18
 What is the High-Performance Ar.?

 The traditional bus architecture -- bottleneck in

performance
– growing demand from the I/O devices
 High-performance architecture approach
– a high-speed bus
– a bridge between the processor’s bus and the high-speed
bus.
– This arrangement is sometimes known as a mezzanine
architecture

Lecture 3. Dr. B.Kovalerchuk 19

 High-Performance Architecture
Main

Local Bus Memory

Processor Cache
/Bridge
System Bus

Graphic Video LAN

High-Speed Bus

Expansion
Bus Interface Serial
FAX

Modem

Expansion Bus
Lecture 3. Dr. B.Kovalerchuk 20
 High-Performance
Architecture
 A local bus connects the processor to the cache
controller, which is in run connected to a system bus
that supports main memory.
 The cache controller is integrated into bridge, or
buffering device, that connects to the high-speed
bus. this bus supports connections to a high-speed
LANs, video and graphics workstation controllers,
as well as interface controllers to local peripheral
buses.
 Lower-speed devices are supported off an expansion
bus, with an interface buffering traffic between the
expansion bus and the high-speed bus.
Lecture 3. Dr. B.Kovalerchuk 21
High-Performance Architecture
 The advantage of this arrangement is that
 the high-speed bus brings high-demand devices into
closer integration with the processor and
 at the same time is independent of the processor.

 Thus differences in processor and high-speed bus

speeds and signal line definitions are tolerated.
 Changes in processor architecture do not affect the
high-speed bus, and vice versa.

Lecture 3. Dr. B.Kovalerchuk 22

 Which elements of bus of bus
design do you know?
 Type Bus Width
 Dedicated Address
 Multiplexed Data
 Method of Arbitration Data Transfer Type
 Centralized Read
 Distributed Write
 Timing Read-modify-write
 Synchronous Read-after-write
 Asynchronous Block
Lecture 3. Dr. B.Kovalerchuk 23
 Describe Bus Types
 Two generic types of bus lines:
 -dedicated - multiplexed
 A dedicated bus line is permanently assigned:
– to one function;
– to a physical subset of computer components.

Lecture 3. Dr. B.Kovalerchuk 24

 What is the time multiplexing?

 the same bus connections are used for the

subsequent read or write data transfer.

Lecture 3. Dr. B.Kovalerchuk 25

Describe Methods of arbitration
 centralized
 a single hardware device referred to as a bus
controller or arbiter, is responsible for allocating
time on the bus-separate module or part of CPU
 distributed
 each module contains access control logic and the
modules act together to share the bus.
 the purpose of both methods is to designate
one device as a master.

Lecture 3. Dr. B.Kovalerchuk 26

 What is the timing?
 Timing refers to the way in which events are
coordinated on the bus.
 What is the difference between synchronous
and asynchronous timing?
 With synchronous timing the occurrence of events on
the bus is determined by a clock.
 With asynchronous timing, the occurrence of one
event on the bus follows and depends on the
occurrence of a previous event.
Lecture 3. Dr. B.Kovalerchuk 27
 Describe difference between
two Data Transfer Types
 All buses support:
– write ( master --> slave )
– read (slave --> master)
 multiplexed address/data bus
– specifying the address
– transferring the data.
 dedicated address and data buses
– the address is put on the address bus and
remains there while
– the data are put on the data bus.

Lecture 3. Dr. B.Kovalerchuk 28

What is the essence of Multiplexed
address/data bus ?
 Write
– specifying the address
– transferring the data.
 Read
– wait while the data is being fetched from the
slave to be put on the bus.

Lecture 3. Dr. B.Kovalerchuk 29

 What is the essence of dedicated
address and data buses
 ADDRESS
– is put on the address bus
– remains there while the data are put on the data bus.
 WRITE
– the master puts the data onto data bus as soon as
 the address has stabilized
 slave has recognized its address.

 READ
– the slave puts the data onto the data bus as soon as it
 has recognized its address
 has fetched the data.

Lecture 3. Dr. B.Kovalerchuk 30