1

BIT MANIPULATION INSTRUCTIONS

LOGIC INSTRUCTIONS SHIFT INSTRUCTIONS ROTATE INSTRUCTIONS

AND , OR , XOR , NOT , TEST, ROL , ROR , RCL , RCR

BT, BTC, BTR, BTS

LOGICAL SHIFTS ARITHMETIC SHIFTS

SHL , SHR, SHRD, SHLD SAL , SAR

LOGIC INSTRUCTIONS

All logic instructions are binary except NOT which is unary. The syntax of the instructions is:

AND Destination , Source

OR Destination , Source
XOR Destination , Source
TEST Destination , Source
NOT Destination

 The result of the operation is stored in the Destination, which must be a register or a memory location.
 The Source may be a constant, register, or memory location.
 The Destination and Source cannot both be memory locations.
 The Destination and Source must be of the same size.

All logic instructions, except TEST, may modify the Destination operand. The TEST instruction does not modify any
of its operands; however it affects the flags similar to the AND instruction.

All logic instructions, except NOT, affect the flags: If the result in the Destination is zero, the Zero flag is set,
otherwise it is cleared. The Carry- and Overflow- flags are always cleared. NOT does not affect any flag.

A logic instruction operates on each corresponding Destination-Source bit pair. The truth tables for logic instructions
are:

Bit1 Bit2 Bit1 AND Bit2 Bit1 TEST Bit2 Bit1 OR Bit2 Bit1 XOR Bit2
0 0 0 0 0 0

0 1 0 0 1 1

1 0 0 0 1 1

1 1 1 1 1 0

Bit NOT Bit

0 1

1 0

Example:

MOV BL , 01010111B
AND BL , 11110000B
____________________________
Result in BL : 01010000B
 2

Setting, clearing and inverting selected bits in the Destination operand

One use of AND, OR, and XOR is to modify selected bits in the Destination operand. To do this, a Source bit pattern
known as a mask is constructed. The mask bits are chosen so that the selected bits are modified in the desired manner
when an instruction of the form:
LOGIC_INSTRUCTION Destination , Mask
is executed. The Mask bits are chosen based on the following properties of AND, OR, and XOR :

If X represents a bit (0 or 1) then:

X AND 0 = 0 X OR 0 = X X XOR 0 = X

X AND 1 = X X OR 1 = 1 X XOR 1 = X

Thus:
1. The AND instruction can be used to clear specific Destination bits while preserving the others. A zero mask bit
clears the corresponding Destination bit; a one mask bit preserves the corresponding destination bit.

Example: XXXXXXXXB Destination

AND 00101011B Mask
00X0X0XXB

2. The OR instruction can be used to set specific Destination bits while preserving the others. A one mask bit sets the
corresponding Destination bit; a zero mask bit preserves the corresponding Destination bit.

Example: XXXXXXXXB Destination

OR 11101001B Mask
111X1XX1B

3. The XOR instruction can be used to invert specific Destination bits while preserving the others. A one mask bit
inverts the corresponding Destination bit; a zero mask bit preserves the corresponding Destination bit.

Example: XXXXXXXXB Destination

XOR 10000101B Mask

XXXXXXXXB

Examples:
 The instruction
AND BL , 11110000B
clears the 4 low-order bits of BL while leaving the 4 high-order bits unchanged.
 The instruction
OR AX , 1100000000000000B
Sets bits 15 and 14 of AX while leaving other bits unchanged.
 The instruction
XOR CL , 00001010B
Inverts bits 1 and 3 of CL while preserving the others.

 Write instructions to make the high 3 bits of CL equal to the high 3 bits of AL and the low 5 bits of CL equal to the
low 5 bits of BL, i.e., CL should have the bit pattern:

a7 a6 a5 b4 b3 b2 b1 b0

Solution:
PUSH BX
MOV CL , AL
AND CL , 11100000B
AND BL , 00011111B
OR CL , BL
POP BX
 3

Changing a letter to its opposite case

 Suppose CL contains a lowercase alphabetic letter. To change that letter to uppercase, we subtract 20H from CL:
SUB CL , 20H
 Suppose BL contains an uppercase alphabetic letter. To change that letter to lowercase, we add 20H to BL:
ADD BL , 20H

 For any alphabetic letter, bit 5 of its ASCII code is 1; but for the corresponding uppercase letter bit 5 is 0. The
remaining bits are similar:

Letter ASCII code Letter ASCII code

‘a’ 0110 0001B ‘A’ 0100 0001B
‘b’ 0110 0010B ‘B’ 0100 0010B
‘c’ 0110 0011B ‘C’ 0100 0011B
. .
. .
. .
‘y’ 0111 1001B ‘Y’ 0101 1001B
‘z’ 0111 1010B ‘Z’ 0101 1010B

Thus a lowercase alphabetic letter can also be converted to uppercase by clearing bit 5 of its ASCII code. This can be
done by using an AND instruction with the mask 11011111B or 0DFh. Example:

MOV DL , ‘j’
AND DL , 11011111B

An uppercase alphabetic letter can also be converted to lowercase by setting bit 5 of its ASCII code. This can be done
by using an OR instruction with the mask 00100000B or 20H. Example:

MOV AL , ‘M’
OR AL , 00100000B

To convert a lowercase or uppercase letter to its opposite case we need only invert bit 5 of its ASCII code. This can
be done by using an XOR instruction with the mask 00100000B.

Converting an ASCII digit to a Decimal digit and vice versa

An ASCII digit (‘0’, ‘1’, ‘2’, ‘3’, ‘4’, ‘5’, ‘6’, ‘7’, ‘8’, or ‘9’) has an ASCII code which is 30H more than the
corresponding Decimal digit. Thus one way of converting an ASCII digit to the corresponding Decimal digit we
subtract 30H from the ASCII digit. Example:
MOV DH , ‘4’
SUB DH , 30H
Similarly one way of converting a Decimal digit to the corresponding ASCII digit is to ADD 30H to the Decimal digit.
Example:
MOV CL , 8
ADD CL , 30H
However, if we compare the ASCII codes of corresponding ASCII- and Decimal-digits:

Decimal digit ASCII code ASCII digit ASCII code

0 0000 0000B ‘0’ 0011 0000B
1 0000 0001B ‘1’ 0011 0001B
2 0000 0010B ‘2’ 0011 0010B
. .
. .
. .
8 0000 1000B ‘8’ 0011 1000B
9 0000 1001B ‘9’ 0011 1001B
 4

We see that bits 5 and 6 of a Decimal digit are both 0, whereas bits 5 and 6 of the corresponding ASCII digit are both 1.
The remaining bits are similar. Thus another way of converting an ASCII digit to the corresponding Decimal digit is to
use the AND instruction with the mask 00001111B (i.e. 0FH) or with the mask 11001111B (i.e. 0CFH) to clear bits 5
and 6 of the ASCII digit. Example:

MOV BH , ‘3’
AND BH , 0FH

Similarly, another way of converting a Decimal digit to the corresponding ASCII digit is to use the OR instruction with
the mask 00110000B (i.e. 30H) to set bits 5 and 6 of the Decimal digit. Example:

MOV CH , 6
OR CH , 00110000B

Examining selected bits in the Destination Operand

The Logic Instructions can be used to examine the status of selected bits in the destination operand. Examples:

 Check if bit 2 of AL is set or clear:

. . .
PUSH AX
AND AL , 00000100B
POP AX
JZ BIT_IS_CLEAR
.
. ; action if bit 2 is set
.
JMP DONE
BIT_IS_CLEAR:
.
. ; action if bit 2 is clear
.
DONE:

Note: This example can be solved using the TEST instruction:

TEST AL , 00000100B
JZ BIT_IS_CLEAR
.
. ; action if bit 2 is set
.
JMP DONE
BIT_IS_CLEAR:
.
. ; action if bit 2 is clear
.
DONE:

 Check whether bits 0, 2, 4 and 5 of DL are all clear:

TEST DL , 00110101B
JZ ALL_4_BITS_CLEAR
.
. ; action if any of bits 0, 2, 4, and 5 is set
.
JMP DONE
ALL_4_BITS_CLEAR:
.
. ; action if each of bits 0, 2, 4, and 5 is clear
.
DONE:
 5

 Check if any of bits 0, 2, 4 and 5 of DL is clear:

PUSH DX
OR DL , 11001010B
CMP DL , 11111111B
POP DX
JNE AT_LEAST_ONE_BIT_CLEAR
.
.
.
JMP DONE
AT_LEAST_ONE_BIT_CLEAR:
.
.
.
DONE:

 Check if each of bits 5, 3, and 1 of CL are set:

PUSH CX
AND CL , 00101010B
CMP CL , 00101010B
POP CX
JE ALL_3_BITS_SET
.
. ; action if any of bits 5, 3, and 1 is not set
.
JMP DONE
ALL_3_BITS_SET:
.
. ; action if each of bits 5, 3, and 1 is set
.
DONE:

Note: This example can also be solved using the OR instruction:

PUSH CX
OR CL , 11010101B
CMP CL , 11111111B
POP CX
JE ALL_3_BITS_SET
.
. ; action if any of bits 5, 3, and 1 is not set
.
JMP DONE
ALL_3_BITS_SET:
.
. ; action if each of bits 5, 3, and 1 is set
.
DONE:
 6

 INT 16H, function 02H can be used to examine the keyboard flags at the BIOS data area, at the Segment: Offset
address 0000:0417h. The function returns in the AL register the keyboard flags. If a flag is set to 1 then it indicates
that a particular control key has been pressed as shown below:

7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1

Insert on Right shift key down

Caps Lock on Left shift key down
Num Lock on Ctrl key down
Scroll Lock on Alt key down

If the fragment below is executed, a jump to label L1 is taken if the Alt-Ctrl-Right shift key combination has been
pressed:

MOV AH , 02H
INT 16H
AND AL , 00001101B
CMP AL , 00001101B
JE L1
JMP L2
L1:
.
.
.
L2:
 Determine if any of the four lowest bits of SI contains a 1:

TEST SI , 000FH
JNZ TRUE
.
.
.
JMP DONE
TRUE:
.
.
.
DONE:
 Check whether a 16-bit memory operand NUM contains an even or an odd number:
(Note: An even number contains a 0 in bit 0; whereas an odd number contains a 1)

TEST NUM , 0001H

JZ EVEN_NUMBER
.
.
.
JMP DONE
EVEN_NUMBER:
.
.
.
DONE:
 7

 Determine if bits 5, 4, and 3 of AL contain 101 :

PUSH AX
AND AL , 00111000B
CMP AL , 00101000B
POP AX
JE TRUE
.
.
.
JMP DONE
TRUE:
.
.
.
DONE:

 Determine whether both AL and BH are zero:

PUSH AX
OR AL , BH
POP AX
JZ TRUE
.
.
.
JMP DONE
TRUE:
.
.
.
DONE:

 Determine whether bits 7 and 6 of BL have the same state as bits 7 and 6 of AL :

PUSH BX
XOR BL , AL
AND BL , 11000000B
POP BX
JZ SAME_STATE
.
.
.
JMP DONE
SAME_STATE:
.
.
.
DONE:

 Let bi denote bit i of BL. Modify BL such that:

1 if b0 = b1 = b2

b3 = 

0 Otherwise

leave the other bits of BL unchanged.

 8

TEST BL , 00000111B
JZ SETBIT3 ; Jump if bits 0, 1, and 3 are all clear
PUSH BX
AND BL , 00000111B
CMP BL , 00000111B
POP BX
JE SETBIT3 ; Jump if bits 0, 1, and 3 are all set
AND BL , 11110111B ; Clear bit 3 while preserving the rest
JMP DONE
SETBIT3: OR BL , 00001000B ; Set bit 3 while preserving the others
DONE:

Clearing a general-purpose register operand or a memory operand to zero

A register operand can be cleared to zero using any of the instructions: MOV, SUB, AND, and XOR. Examples:
MOV BL , 0
SUB AX , AX
AND CL , 0
XOR DH , DH

A memory operand can be cleared to zero using either the MOV or AND instruction. Examples:
MOV VAR1 , 0
AND ARRAY[2] , 0

The NOT and NEG instructions

The NOT instruction, whose syntax is:
NOT Destination
is a logical instruction which inverts all the bits of a register or memory operand, i.e., it forms the 1’s complement of
the operand. The NEG (NEGate) instruction, whose syntax is:
NEG Destination
is an arithmetic instruction which forms the 2’s complement (i.e., 1’s complement + 1) of an operand.

BIT test instructions

The 80386 and higher 8086 processors contain additional test instructions that test bit positions. These instructions do
not accept byte operands:

Instruction Operands Comment

BT BT (Bit Test) tests the destination bit specified by the source and places the value
of the bit in the Carry flag.
BTC r/m16 , r16 BTC (Bit Test and Complement) tests the destination bit specified by the source,
it copies that bit to the Carry flag, and complements (i.e., inverts) the original bit
r/m 16 , imm8
in the destination.
BTR
r/m 32 , r32 BTR (Bit Test and Reset) tests the destination bit specified by the source, copies
r/m 32 , imm8 that bit to the Carry flag, it then clears the original bit in the destination.
BTS BTS (Bit Test and Set) tests the destination bit specified by the source, copies that
bit to the Carry flag, it then sets the original bit in the destination.

Examples:
(a) BT AX , 4
JC L2 ; Jump if bit 4 of AX is set
. . .
L2: . . .

(b) MOVZX EAX, BYTE PTR DS:[04A2H] ; copy memory byte into 32-bit register
BTC EAX, 2 ; test and compliment bit number 2
MOV DS:[04A2H], AL ; write modified byte back to memory
JC bit2set ; branch if original bit number 2 was set

(c) BTR MY_FLAG, 7 ; Clear the high-order bit of byte MY_FLAG

JNC NOT_SET ; branch if the original bit was clear
 9

OTHER INSTRUCTIONS THAT MANIPULATE BITS

(a) BSF (Bit Scan Forward), and BSR (Bit Scan Reverse) instructions
These instructions are available in 80386 and higher Intel processors:

Instruction Operands
BSF r16 , r/m 16
BSR r32 , r/m 32

BSF scans a source word or double-word for a one-bit, from the rightmost bit towards the leftmost bit. If a one-bit
is found, the bit position of this rightmost one-bit is stored in the destination register, and the Zero Flag (ZF) is
cleared. If the source is zero, the Zero Flag is set, and the value of the destination register is undefined.

BSR scans a source word or double-word for a one-bit, from the leftmost bit towards the rightmost bit. If a one-bit
is found, the bit position of this leftmost one-bit is stored in the destination register, and the Zero Flag (ZF) is
cleared. If the source is zero, the Zero Flag is set, and the value of the destination register is undefined.

Examples:
1. MOV EAX, 60000000H
BSF EBX, EAX ; EBX  29 , ZF  0

2. MOV ECX, TABLESIZE –1 ; index of last entry in double-word TABLE

L1: BSR EAX, TABLE[ECX*4] ; scan for non-zero bit
JNZ FOUND_ONE_BIT
LOOP L1
NO_ONE_BIT_FOUND:
.
.
.
JMP DONE
FOUND_ONE_BIT:
.
.
.
DONE:

(b) LAHF (Load AH with Flags) and SAHF (Store AH in FLAGS/EFLAGS)

LAHF copies the low-order byte of the FLAGS register or the EFLAGS register into the AH register. It thus copies
SF, ZF, AF, PF, and CF to AH bits 7, 6, 4, 2, and 0, respectively. The contents of the remaining bits (5, 3, and 1)
are undefined.

7 6 5 4 3 2 1 0
SF ZF AF PF CF

Fig: Low-order byte of the FLAGS or EFLAGS register

SAHF copies the contents of the AH register into bits 7, 6, 4, 2, and 0 of the FLAGS or the EFLAGS register.