DSDE 152

Digital System Design

Lecture 7: Timing Diagram and

Gated Latches
Spring 2021
Dr. Shawkat S. Khairullah
Department of Computer Engineering 1
University of Mosul
 9- Timing diagram
• A race condition or race hazard is a flaw in an electronic
system or process whereby the output and/or result of the
process is unexpectedly and critically dependent on the
sequence or timing of other events.

• qSR=110→SR=00 → SR=01 → SR=00 → SR=10

S(set)
tpd X

Q ∆t q
tpd
R (reset) (delay)
2
2 tpd
Standard Symbols for Storage Elements

• Latches S S D D

R R C C

• Master-Slave: SR SR D with 1 Control D with 0 Control

(a) Latches
Postponed output
indicators S S D D

C C
R R C C

• Edge-Triggered: Triggered SR Triggered SR Triggered D Triggered D

Dynamic (b) Master-Slave Flip-Flops

indicator D D

C C

Triggered D Triggered D
(c) Edge-Triggered Flip-Flops
Gated S-R Latches

(set) S
Q
S Q
C C

R Q'
Q
(reset) R

(set)S
X

C
4
Q ∆t q
(delay)
(reset) R
 Characteristic equation
V1  C  S (set)S V1
V2

V 2  V1  q  C  S  q C

V3  C  R V3
Q ∆t
(delay)
q

(reset) R
Q  V 2 V 3
Q  CS qCR

Q  C  S  R  q C  q  R 5
 State diagram & ASM chart
0
a

CSR
101 0
C.S.R
111
1
CSR CSR
000 000
a b 001 1
001
0 1 b
010 010
011 011
100 100
101 CSR 110
111
1
110 C.R

0 6
Karnaugh map

Overlay
adjacency

CSR
q 000 001 011 010 100 101 111 110
Q=
0 0 0 0 0 0 0 0 1

1 1 1 1 1 1 0 0 1

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Gated D Latches

S
D
D Q Q

Q
C Q
R SR latch

8
Gated D Latches
S
D
D Q Q

Q
C Q
R SR latch

Q  ~ S  D  q ~ R Q  C  D  q C  q  D
CD CD
CD CD q 00 01 11 10
10
00 00
Q=
01 01
10 11 0 0 0 1 0
a b
0 1
1 1 1 1 0 9
CD
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Gated T Latches
T Q T S Q

C C

Q
R Q

Q  q  C T  q  C  q T
CT CT
CT CT q 00 01 11 10
11
00 00
Q=
01 01
10 10 0 0 0 1 0
a b
0 1
1 1 1 0 1 10
CT
11
Gated J-K Latches
J Q J J
S Q
Q
C C C

C Q Q
K R Q
K

Q  S RqR
S  q C  J
R  q C  K

11
Q  q C  J  q C  q  K
Gated J-K Latches
Overlay
adjacency 0
a

CJK
q 000 001 011 010 100 101 111 110
Q=
0 0 0 0 0 0 0 1 1 0
C.J

1
1 1 1 1 1 1 0 0 1

CJK 1
b
101
111

CJK CJK
000
000 a b 001 0
001 0 1 C.K
010
010 011
011 100
1 12
100 110
101 CJK
110
111
Thank you

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