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Computer Architecture and Opera2ng System

Prof. Indranil Sengupta

Department of Computer Science and Engineering
IIT Kharagpur

Design of Control Unit

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Basic Concept
• Any digital circuit module consists of two components:
a) Data Path – performs data transfer and processing opera=ons.
(Adder, mul=plier, mul=plexer, register, bus, counter, decoder, etc.)
b) Control Unit – generates control signals for the data path for sequencing of
the opera=ons.
(Basically a finite-state machine)
Control signals

Control Control Unit Status signals

inputs Datapath
Data
outputs
Control Data
outputs inputs
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Control signals

Control Control Unit Status signals

inputs
Datapath
Data
outputs
Control Data
outputs inputs

• The control unit receives:

• External control inputs
• Status signals generated by the datapath
• The control unit sends:
• Control signals for ac=va=ng the datapath components
• Control outputs

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Types of Control Units

• Two dis=nct classes:
a) Non-programmable or hardwired
b) Programmable or microprogrammed
• A hardwired control unit has dedicated circuits, and does not fetch or
sequence instruc=ons from any memory.
• A microprogrammed control unit has a separate memory where the
informa=on regarding control signals and sequencing is stored.
• For example, a micro-program counter (μPC) points to the next set of control
signals (microinstruc=on word) to be fetched from memory.

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Recall how an instruc2on gets executed

repeat forever
// till power off or Fetch
// system failure
{
Fetch instruction Memory
Decode
Decode instruction
Execute instruction
} Execute

Fetch-Decode-Execute Cycle

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Requirements for Execu2ng an Instruc2on

• Example: ADD R1,R2,R3

• Requirements for understanding the mechanism:
• The necessary registers must be present.
• The internal organiza=on of the registers must be known.
• The data path must be known.
• For instruc=on execu=on, a number of micro-opera1ons are carried out on
the data path.
• An instruc=on consists of several micro-opera1ons or micro-instruc1ons.
• May involve movement of data.

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Kinds of Data Movement Inside the CPU

• Broadly three types:

a) Register to Register
b) Register to ALU
c) ALU to Register
• Data movement must be supported in the data path by:
• The Registers
• The Bus (single or mul=ple)
• Some temporary registers, mul=plexers, etc.

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Single Bus Organiza2on

Internal Processor Bus

PC
Instruc=on Decoding .. Control
MAR
and Control Unit . signals
MEMORY
MDR
IR
4
Y R0
General-purpose
Select MUX R1 Registers
..
Func=on
.
ALU Carry-in
select Rn-1

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Example: Single Internal Bus Organiza2on

Single Bus Organiza0on
• All the registers and various units are connected
Internal Processor Bus
using a single internal bus.
PC
• Registers R0-Rn-1 are general-purpose registers Instruc3on Decoding .. Control
MAR
and Control Unit . signals

used for various purposes. MEMORY

MDR
IR
• Y and Z are used for storing intermediate results 4
Y R0
and never used by instruc=ons explicitly. Select MUX R1
General-purpose
Registers
..
• The mul=plexer selects either a constant 4 or Func3on
.
ALU Carry-in
select Rn-1
output of register Y.
Z
• When PC is incremented, a constant 4 has to be
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Single Bus Organiza0on

• The instruc=on decoder and control unit is Internal Processor Bus

responsible for performing the ac=ons specified PC

Instruc3on Decoding .. Control
by the instruc=on loaded into IR. MAR
and Control Unit . signals
MEMORY

• The decoder generates all the control signals in MDR

IR
4
the proper sequence required to execute the Y R0
General-purpose
MUX
instruc=on specified by the IR. Select R1
.. Registers

Func3on
.
• The registers, the ALU and the interconnec=ng select
ALU Carry-in
Rn-1

bus are collec=vely referred to as the datapath. Z

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Kinds of Opera2ons
• Transfer of data from one register to another.
MOVE R1, R2 // R1 = R2
• Perform arithme=c or logic opera=on on data loaded into registers.
ADD R1, R2 // R1 = R1 + R2
• Fetch the content of a memory loca=on and load it into a register.
LOAD R1, LOCA // R1 = Mem[LOCA]
• Store a word of data from a register into a given memory loca=on.
STORE LOCA, R1 // Mem[LOCA] = R1

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Three Bus Organiza2on

• A typical 3-bus architecture for the processor datapath is shown in

the next slide.
• The 3-bus organiza=on is internal to the CPU.
• Three buses allow three parallel data transfer opera=ons to be carried out.
• Less number of cycles required to execute an instruc=on compared to
single bus organiza=on.

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Bus A Bus B Bus C

PC

Register File
4 M
U A
X
L
U

Instruc=on Decoder

IR
Data
MDR
Memory
MAR Address

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Control Signals for Register-Register and

Register-Memory Transfers

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Organiza2on of a Register
Riin
• A register is used for temporary storage of data
(parallel-in, parallel-out, etc.).
• A register Ri typically has two control signals.
• Riin : used to load the register with data from the Register Ri
bus.
• Riout : used to place the data stored in the
register on the bus.
Riout
• Input and output lines of the register Ri are
connected to the bus via controlled switches.

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Riin

• When (Riin = 1), the data available

on bus is loaded into Ri. Register Ri

Riout

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Riin

• When (Riout = 1), the data from

register Ri are placed on the bus. Register Ri

Riout

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R1in

Register-Register Transfer
MOVE R1, R2 // R1 = R2 Register R1

• Enable the output of R2 by seing R2out = 1.

R1out
• Enable the input of register R1 by seing R1in = 1.
R2in
• All opera=ons are performed in synchronism with the
processor clock.
• The control signals are asserted at the start of the clock
cycle. Register R2
• Ajer data transfer the control signals will return to 0.
• We write as T1: R2out , R1in
R2out

Time Step Control Signals

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Riin
ALU Opera2on
Ri
ADD R1, R2 // R1 = R1 + R2 Riout

Yin
• Bring the two operands (R1 and R2) to the two
inputs of the ALU. Y
4
One through Y (R1) and another (R2) directly from
internal bus. S MUX

• Result is stored in Z and finally transferred to R1. ALU

T1: R1out , Yin Zin
T2: R2out , SelectY, ADD, Zin Z
T3: Zout , R1in Zout

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Fetching a Word from Memory

• The steps involved to fetch a word from memory:

• The processor specifies the address of the memory loca=on in MAR where
the data or instruc=on is stored.
• The processor requests a Read opera=on.
• The informa=on to be fetched can either be an instruc=on or an operand of
the instruc=on.
• The data read is brought from the memory to MDR.
• Then it can be transferred to the required register or ALU for further
opera=on.

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Storing a Word into Memory

• The steps involved to store a word into the memory:

• The processor specifies the address of the memory loca=on in MAR where
the data is to be wriken.
• The data to be wriken in loaded into MDR.
• The processor requests a Write opera=on.
• The content of MDR will be wriken to the specified memory loca=on.

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Connec2ng MDR to Memory Bus and Internal Bus

Memory bus MDRinE MDRin

Internal processor
bus
MFC Memory MDR

MAR MDRoutE MDRout

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• Memory read/write opera2on:

• The address of memory loca=on is transferred to MAR.
• At the same =me a read/write control signal is provided to indicate the opera=on.
• For read the data from memory data bus comes to MDR by ac=va=ng MDRinE.
• For write the data from MDR goes to memory data bus by ac=va=ng the signal MDRoutE.
Connec&ng MDR to Memory Bus and Internal Bus
Memory bus MDRinE MDRin

Internal processor
bus
MFC Memory MDR

MAR MDRoutE MDRout

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• When the processor sends a read request, it has to wait un=l the data is read from the memory and
wriken into MDR.
• To accommodate the variability in response =me, the processor has to wait un=l it receives an indica=on
from the memory that the read opera=on has been completed.
• A control signal called Memory Func1on Complete (MFC) is used for this purpose.
• When this signal is 1, indicates that the content of the specified loca=on is read and are available on the data
line of the memory bus.
Connec&ng
• Then the data can be madeMDR totoMemory
available MDR. Bus and Internal Bus
Memory bus MDRinE MDRin

Internal processor
bus
MFC Memory MDR

MAR MDRoutE MDRout

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Fetch a word: MOVE R1, (R2)

1. MAR ← R2
Control steps:
2. Start a Read opera=on on the memory bus
a) R2out , MARin , Read
3. Wait for the MFC response from the memory b) MDRinE , WMFC
4. Load MDR from the memory c) MDRout , R1in
5. R1 ← MDR

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Store a word: MOVE (R1), R2

1. MAR ← R1 Control steps:

2. MDR ← R2 a) R1out , MARin
b) R2out, MDRin , Write
3. Start a Write opera=on on the memory bus
c) MDRoutE , WMFC
4. Wait for the MFC response from the memory

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Execu2on of a Complete Instruc2on

Riin
ADD R1, R2 // R1 = R1 + R2
Ri
Riout
T1: PCout, MARin, Read, Select4, ADD, Zin Yin
T2: Zout, PCin, Yin, WMFC
Y
4
T3: MDRout, IRin S MUX

T4: R1out, Yin, SelectY ALU

Zin
T5: R2out, ADD, Zin
Z
T6: Zout, R1in Zout

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Example for a Three Bus Organiza2on

SUB R1, R2, R3 // R1 = R2 – R3 Bus A Bus B
Incrementer
Bus C

PC

Register File

T1: PCout, R = B, MARin , READ, IncPC 4 M

U A
X
L
T2: WMFC U

Instruc*on Decoder
T3: MDRoutB , R = B, IRin
IR
Data
T4: R2outA , R3outB , SelectA, SUB, R1in , End MDR
Memory
MAR Address

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