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In A Logic Circuit A Hazard Is Independent Form

The document discusses several topics related to logic circuits and hazards. It begins by stating that a hazard in a logic circuit is independent of delay, clock pulses, latches, or feedback. Dynamic hazards can occur in a circuit with multiple paths and different delays. Switch logic is fast for large arrays and uses complementary switches. Gate logic is also called restoring logic. The document also discusses programmable logic devices like PALs, PLAs, CPLDs and FPGAs. It covers topics like state representation in ASM charts, integrated circuit classifications, MOSFET components, and ARM processor features like low cost and power consumption.

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87 views

In A Logic Circuit A Hazard Is Independent Form

The document discusses several topics related to logic circuits and hazards. It begins by stating that a hazard in a logic circuit is independent of delay, clock pulses, latches, or feedback. Dynamic hazards can occur in a circuit with multiple paths and different delays. Switch logic is fast for large arrays and uses complementary switches. Gate logic is also called restoring logic. The document also discusses programmable logic devices like PALs, PLAs, CPLDs and FPGAs. It covers topics like state representation in ASM charts, integrated circuit classifications, MOSFET components, and ARM processor features like low cost and power consumption.

Uploaded by

win papasan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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In a logic circuit a Hazard is independent form

A. Delay Existing
B. Clock Pulses
C. Latches
D. Feedback
ANSWER: A

Static hazard can be detected by using k-map in


A. Two level sum of products
B. Two level of product of sum
C. Both (1) and (2)
D. Neither (1) nor (2)
ANSWER: C

In dynamic hazards multiple output transition can occur if


A. Circuit have single path with different delay
B. Circuit have multiple paths with different delay
C. Circuit have multiple paths with single delay
D. Circuit have single path with single delay
ANSWER: B
Switch logic approach is fast for
A. large arrays
B. small arrays
C. very large arrays
D. not at all fast for any type
ANSWER: A

Switch logic is designed using


A. complementary switches
B. silicon plates
C. conductors
D. resistors
ANSWER: A

Gate logic is also called as


A. transistor logic
B. switch logic
C. complementary logic
D. restoring logic
ANSWER: D
A GAL is essentially a ………….
a) non-reprogrammable PAL
b) PAL that is programmed only by the manufacturer
c) very large PAL
d) reprogrammable PAL
Answer: d

By adding an OR gate to a simple programmable logic device (SPLD) the


foundation for a(n) ……….. is made possible.
a) PAL
b) PLA
c) CPLD
d) EEPROM
Answer: a

The difference between a PLA and a PAL is:


a) The PLA has a programmable OR plane and a programmable AND plane, while
the PAL only has a programmable AND plane.
b) The PAL has a programmable OR plane and a programmable AND plane, while
the PLA only has a programmable AND plane.
c) The PAL has more possible product terms than the PLA.
d) PALs and PLAs are the same thing.
Answer: a
The complex programmable logic device (CPLD) contains several PAL-type
simple programmable logic devices (SPLDs) called:
a) macrocells
b) microcells
c) AND/OR arrays
d) fuse-link arrays
Answer: a

Timing performance of a design is measure by which simulation mode?


a. Behavioural
b. Gate-level
c. Switch-level
d. Transistor-level
Answer:-b. Gate-level

What is common in Mealy & Moore machines?


a. Combinational output signal
b. Clocked Process
c. Both a and b
d. None of the above
Answer:-b. Clocked Process
Field-programmable gate arrays (FGPAs) use ………. memory technology,
which is ………….
a) DRAM, nonvolatile
b) SRAM, nonvolatile
c) SRAM, volatile
d) RAM, volatile
Answer: c

What programmable technology is used in FPGA devices?


a) SRAM
b) FLASH
c) Antifuse
d) All of the above
Answer: d

Which is the main programming unit in FPGA?


a) Programmable AND Array
b) Configurable Logic Block
c) Programmable OR Array
d) None of the above
Answer:-b
In ASM charts state box is represented in which shape?
A) Oval
B) Cube
C) Triangle
D) Rectangular
Answer: D) Rectangular

In ASM charts decision box is represented in which shape?


A) Oval
B) Cube
C)Triangle
D)Diamond
Answer: D) Diamond

In ASM charts conditional output box is represented in which shape?


A) Oval
B) Cube
C) Triangle
D) Rectangular
Answer: A) Oval
A classification of integrated circuits with complexities of 30 to 300 equivalent
gates on a single chip is known as?
A. VLSI
B. SSI
C. LSI
D. MSI
ANSWER: D

Which is the high-level representation of VLSI design?


A. problem statement
B. logic design
C. HDL program
D. functional design
ANSWER: A

VLSI technology uses ........ to form integrated circuit.


A. transistors
B. switches
C. diodes
D. buffers
ANSWER: A
Source in MOS transistors is doped with ........ material
A. n-type
B. p-type
C. n & p type
D. none of the mentioned
ANSWER: A

TTL is a class of digital circuits built from


A. Resistors only
B. BJT (Bipolar Junction Transistors) only
C. JEFT only
D. Both option a and b
ANSWER:D

Which insulating layer is used in the fabrication of MOSFET?


A. Silicon Nitride
B. Aluminum sulphate
C. Copper sulphate
D. Silicon dioxide
ANSWER: D
Most look-up tables in field-programmable gate arrays (FGPAs) use ……….
inputs, resulting in ……… possible outputs.
a) 4,16
b) 8,16
c) 4,12
d) 6,12
Answer: a

A hazard is existed in a circuit


A. When a circuit has the possibility of producing a glitch
B. When a circuit has the possible tolerance to filter a glitch
C. When a circuit has the maximum probability to stop unwanted glitch
D. When a circuit is on its minimum limit to removing glitch
ANSWER: A

What is the design flow of VLSI system?


i. architecture design
ii. market requirement
iii. logic design
iv. HDL coding
A. ii-i-iii-iv
B. iv-i-iii-ii
C. iii-ii-i-iv
D. i-ii-iii-iv
ANSWER: A
The main importance of ARM micro-processors is providing operation with
______
a) Low cost and low power consumption
b) Higher degree of multi-tasking
c) Lower error or glitches
d) Efficient memory management

Answer: a
Explanation: The Stand alone feature of the ARM processors is that they’re
economically viable.

Memory can be accessed in ARM systems by __________ instructions.


i) Store
ii) MOVE
iii) Load
iv) arithmetic
v) logical
a) i, ii, iii
b) i, ii
c) i, iv, v
d) iii, iv, v

Answer: b

Which of the following is not a stage of pipeline of a RISC processor?


a) read registers and decode the instructions
b) fetch instructions from registers
c) write result into a register
d) access an operand in data memory

Answer: b
Explanation: There are 5 stages in pipelining. They are
1. Fetch instructions from memory
2. Read registers and decode the instructions
3. Execute the instructions or calculate an address
4. Access an operand in data memory
5. Write result into a register.

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