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Cycle Test 3 Set 2

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22 views

Cycle Test 3 Set 2

Uploaded by

nithya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SRM INSTITUTE OF SCIENCE AND TECHNOLOGY

RAMAPURAM CAMPUS
DEPARTMENT OF EEE
18EEC203J - DIGITAL SYSTEM DESIGN
CYCLE TEST 3
YEAR/SEM - II/ III DATE:
Maximum marks – 50 DURATION: MIN

PART A (50*1 =50)


Answer All the MCQs

1. The truth table for an S-R flip-flop has how many VALID entries?
a) 1 b) 2 c) 3 d) 4
Ans:c
2. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
Ans:C
3. The logic circuits whose outputs at any instant of time depends only on the present input but also on the
past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
Ans:b
4. How many types of flip-flops are?
a) 2
b) 3
c) 4
d) 5
Ans : C
5. The characteristic of J-K flip-flop is similar to
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
d) None of the Mentioned
Ans: a

6. How is a J-K flip-flop made to toggle?


a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
Ans: d
7. How many natural states will there be in a 4-bit ripple counter?
a) 4
b) 8
c) 16
d) 32
Ans: C
8. How many different states does a 3-bit asynchronous counter have?
a) 2
b) 4
c) 8
d) 16
Ans:c
9. From the K-map given below, what would be the state equation of D Flip Flop?

a. Qn+1 = QnD
b. Qn+1 = QnD
c. Qn+1 = D’
d. Qn+1 = D
Ans :d
110. Which type of memory elements are used in synchronous sequential circuits?

a. Clocked Flip flops


b. Unclocked Flip flops
c. Time Delay Elements
d. All of the above

Ans:a
11. PAL refers to ____________
a) Programmable Array Loaded
b) Programmable Logic Array
C ) Programmable Array Logic
d) Programmable AND Logic
Ans:b
12. PLA contains ____________
a) AND and OR arrays
b) NAND and OR arrays
c) NOT and AND arrays
d) NOR and OR arrays
Ans: a
13. If a PAL has been programmed once ____________
a) Its logic capacity is lost
b) Its outputs are only active HIGH

c) Its outputs are only active LOW


d) It cannot be reprogrammed
Ans:d
14. The FPGA refers to ____________
a) First programmable Gate Array
b) Field Programmable Gate Array
c) First Program Gate Array
d) Field Program Gate Array
Ans:b
15. The most basic form of behavioral modeling in VHDL is_______
a) IF statements
b) Assignment statements
c) Loop statements
d) WAIT statements
Ans: b
16. Which of the following is defined in structural modeling?
a) The structure of circuit
b) Behavior of circuit on different inputs
c) Data flow form input to output
d) Functional structure
Ans: a

17. Which is not a removable drive?


a. Super disk
b. b. Jaz
c. c. Hard disk
d. d. Drive
Ans: C
18. A ------------ is a semiconductor memory device used to store information, which is permanent in nature
a. ROM
b. b. RAM
c. c. K map
d. d. Table
Ans:a
19. How are the design specifications represented in the behavioral modeling style of VHDL?
a. Boolean equation
b. Truth table
c. Logical diagram
d. State diagram
Ans:b
20. The ripple counter is one kind of
a. sequential counter
b. asynchronous counter
c. synchronous counter
d. up-down counter.
Ans: b
21. 2’s complement of binary number 0101 is ………..
a. 1011
b. 1111
c. 1101
d. 1110
Ans: a
22. A device which converts BCD to seven segments is called
……..
a. Encoder
b. Decoder
c.Multiplexer
d. None of these
Ans : b
28. The expression Y = pM (0, 1, 3, 4) is …………..
a. POS
b. SOP
c. Hybrid
d. none of these
Ans: a
29. The basic storage element in a digital system is ………….
a. flipflop
b. counter
c. multiplexer
d. encoder
Ans: a
30. A full adder can be made out of …………
a. two half adders
b. two half adders and a OR gate
c.Two half adders and a NOT gated
d. three half adders
31. The output of a half adder is ……….
a. Sum
b. Sum and Carry
c. Carry
d. none of these
Ans: b
32. Which device has one input and many outputs?
a. Multiplexer
b. Demultiplexer
c.Counter
d. Flip flop
Ans: b
33. A carry look ahead adder is frequently used for addition
because
a. it costs less
b. it is faster
c. it is more accurate
d. uses fewer gates
Ans: b
34. 1’s complement of 11100110 is ……………….
a. 00011001
b. 10000001
c. 00011010
d. 00000000
Ans: a
35. In 1-to-4 demultiplexer, how many select lines are required?
a. 2
b. 3
c. 4
d. 5
Ans: a
36. How many Flip-Flops are required for mod–16 counter

a. 5
b. 6
c. 3
d. 4
Ans: d
37. EPROM contents can be erased by exposing it to

(A) a. Ultraviolet rays.


b. I b. infrared rays.
c. Burst of microwaves.
d. Intense heat radiations.
Ans Ans: a

38. The code where all successive numbers differ from their preceding number by single
bit is
a. Binary code
. b. BCD.
c. Excess – 3.
d. Gray.
Ans:d
39. Which of the following is the fastest logic
a. TTL
b. ECL
c. CMOS
d. LSI
Ans: b
40. Which of the memory is volatile memory
(A)
a. ROM
b. R AM
c. PROM
d. EEPROM
41. The device which changes from serial data to parallel data is
a. COUNTER
b. MULTIPLEXER
c. DEMULTIPLEXER
d. FLIP-FLOP
The pr Ans: c
42. The process of entering data into a ROM is called
(A) a. burning in the ROM
programming the ROM
c. changing the ROM
d. charging the ROM
Ans:: b
43 43. 43. The output of SR flip flop when S=1, R=0 is
a. 1
b. 0
c. No change
d. High impedance
Ans: a
The 44. The excess-3 code of decimal 7 is represented by
a. 1100.
b. 1001.c. 1011
d. 1010.
Ans: d
45. The decimal equivalent of Binary number 10101 is
a. 21
b. 31
c. 26
d. 28
Ans: a
46. or 46. JK flipflop J = 0, K=1, the output after clock pulse will be
a. 1
b. no change c. 0 d. high impedance.
Ans: c
47. 47. Which of following consume minimum power?
a. TTL
.b. CMOS.
c. DTL d. RTL.
Ans: b
48. Which of following requires refreshing?
a. SRAM
b. DRAM
c. ROM d. EPROM.
Ans: b
49. VLSI chip utilizes
a. CMOS
b. b. BJT
c. c. NMOS
d. d. All the Above
Ans: d
50. Why antifuses are implemented in a PLD?
a. To protect from high voltage
b. To increase memory
c. As a switching device
d. to implement the programmes
Ans: d
Ans: d

Ans

Ans
Ans

An
38.

Ans

Ans
51.

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