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DSDV Assignment 2

This document is an assignment sheet from Rajeev Institute of Technology, Hassan for their Digital System Design using Verilog course. It contains 10 questions related to digital logic design topics like carry lookahead adders, binary subtractors, priority encoders, magnitude comparators, decoders, flip-flops and counters. The questions range from basic concepts to more complex logic design problems. Students are asked to explain concepts, draw logic diagrams, derive characteristic equations and implement logic functions using multiplexers and decoders.

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36 views

DSDV Assignment 2

This document is an assignment sheet from Rajeev Institute of Technology, Hassan for their Digital System Design using Verilog course. It contains 10 questions related to digital logic design topics like carry lookahead adders, binary subtractors, priority encoders, magnitude comparators, decoders, flip-flops and counters. The questions range from basic concepts to more complex logic design problems. Students are asked to explain concepts, draw logic diagrams, derive characteristic equations and implement logic functions using multiplexers and decoders.

Uploaded by

h.s.surabhi2005
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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R AJEEV I NST I T UT E OF T ECHNOLOGY , HASSAN

Plot 1-D, Growth Center, Industrial Area, B-M Bypass Road, Hassan, Karnataka 573201

Department of Electronics and Communication Engineering


Assignment No 2 Scheme 2022
Course Name Digital system Design using Verilog Course Code 22BEC302
Submission Date

Q.No Question CO RBT


1 Explain carry look ahead adder with General and sigma block 2 L2
2 Explain Binary Subtractor and Adder (Half & Full) with K-map and logical
2 L2
representation of equations for sum and carry.
a) Define Encoder? Explain 8:3 priority encoder
b) Implement f(abcd)=∑m(0,4,8,10,14,15)
3 2 L1,L2
i) Using 8:1 Mux with a,b,c as selected lines
ii) 4:1 mux with a,b as select lines.
4 Design 1-bit and 2-bit magnitude comparators and also draw the logic diagram. 2 L3
Design the condensed truth table for a 4 to 2 line priority encoder with a valid
5 o/p where the highest priority is given to the least bit position or i/p with lowest 2 L3
index & obtain the minimal sum expression for the o/ps.
Realize the Boolean expression using 3:8 decoder and two OR gates and Nor
6 gates 2 L3
i) f1=∑m(1,3,4,6,7) ii) f2=∑m(0,2 ,4,7)
Write a note on Master slave SR flip-flop timing diagram with function table
7 3 L2
and logic diagram.
8 Write a Characteristic equation for SR,T,D and JK FF 3 L1
Write a note on Master slave JK flip-flop timing diagram with function table
9 3 L2
and logic diagram.
a) Define Counter? Ex[plain Binary Ripple Counter with neat diagram
10 b) What is Register? Explain any two classification registers with neat 3 L1,L2
block diagram.

Signature of the Faculty Signature of the HOD


(Mr. Ravi L.S) (Dr. Aravind B N)

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