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    Task 3

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    pratapsneh.sp

    Copyright:

    © All Rights Reserved
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    Task 3

    Uploaded by

    pratapsneh.sp
    7 views6 pages

    Original Title

    task 3

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    Copyright:

    © All Rights Reserved
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    Download as docx, pdf, or txt
    7 views6 pages

    Task 3

    Uploaded by

    pratapsneh.sp

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    You are on page 1of 6

    Contents sheet for TASK III to be included in the front/index sheet of VTOP

    TASK file document

    Sl.no Components Page Student RA


    . no., Check Check
    mark
    mark

    PART I-Multiplexer based Design

    ✔ ✔
    1 Aim

    2 Components Required and Tools Required

    3 Procedure

    4 Pin diagram

    5 Truth Table and boolean expression of Multiplexer,


    Demultiplexer.

    6 Multiplexer Theory

    7 Demultiplexer Theory

    8 Block diagram /Circuit diagram for implementing


    16 :1 MUX using 8:1 MUX

    9 Block diagram and Circuit diagram for implementing


    8:1 MUX using 4 :1 MUX

    10 Block diagram and Circuit diagram for


    Contents sheet for TASK III to be included in the front/index sheet of VTOP
    TASK file document

    implementing 4: 1 MUX using 2: MUX

    11 SOP canonical expression of MUX and circuit


    implemented in MUX

    12 POS canonical expression of MUX and circuit


    implemented in MUX

    13 Circuit diagram of 2:1 MUX Circuit using SOP


    Equation -- AOI circuit

    14 Circuit diagram of 2:1 MUX Circuit using POS


    Equation --- OAI circui

    15 Circuit diagram of 2:1 MUX Circuit using SOP


    Equation --- NAND circuit

    16 Circuit diagram of 2:1 MUX Circuit using POS


    Equation --- NOR circuit

    17 Implementation steps for Task I and II using 4:1


    Multiplexer

    18 Implementation steps for Task I and II using 8:1


    Multiplexer

    19 Multisim live / Circuitverse.org Simulation link for


    Multiplexer based circuit implemented using 8:1
    Multiplexer

    20 Multisim live / Circuitverse.org Simulation link for


    Contents sheet for TASK III to be included in the front/index sheet of VTOP
    TASK file document

    Multiplexer based circuit implemented using 4:1


    Multiplexer

    21 IC inter-connection diagram for 2:1 MUX HW


    connection in breadboard

    22 Verilog code:SL

    23 Verilog code:BL

    24 Verilog code:DFL

    25 Verilog code : Conditional Operator

    26 Test Bench

    27 Snip of Output waveform with respective code

    28 Online Verilog code Simulation links

    29 Result

    30 Inference

    PART II - Demultiplexer / Decoder based Design

    1 Aim
    Contents sheet for TASK III to be included in the front/index sheet of VTOP
    TASK file document

    2 Components Required and Tools Required

    3 Procedure

    4 Pin diagram

    5 Truth Table and boolean expression of


    Encoder(4:2,8:3), Decoder(2:4,3:8)with active low and
    active high logic.

    6 Block diagram for implementing 3 :8 Decoder using


    2:4 Decoder

    7 Block diagram for implementing 2: 4 Decoder using


    1:2 Decoder

    8 Decoder theory

    9 Encoder and Priority Encoder Theory

    10 AOI logic circuit of 2:4 Decoder

    11 NAND logic circuit of 2:4 Decoder

    12 AOI logic circuit of 4:2 encoder

    13 NAND logic circuit of 4:2 encoder


    Contents sheet for TASK III to be included in the front/index sheet of VTOP
    TASK file document

    14 Implementation steps for Task I & II using Decoder

    15 Proof of Task I (SOP) implemented using Decoder


    Active Low logic in the simulator using snipping tool

    16 Proof of Task I (SOP) implemented using Decoder


    Active High logic in the simulator using snipping tool

    17 Proof of Task I (POS) implemented using Decoder


    Active Low logic in the simulator using snipping tool

    18 Proof of Task I (POS) implemented using Decoder


    Active High logic in the simulator using snipping tool

    19 Verilog code for 2:4 Decoder (BL, DFL)

    20 Verilog code of 3:8 Decoder

    (BL, DFL)

    21 Verilog code for 2:4 and 3:8 Decoder (SL)

    22 Verilog Test Bench of Decoder

    23 Snip of Verilog code output with links

    24 Result
    Contents sheet for TASK III to be included in the front/index sheet of VTOP
    TASK file document

    25 Inference

    Lab TASK III Signature of lab technician / lab


    Title: Implementation of combinational circuits using Multiplexer,
    Slot: RA or LAB JF with date a
    Decoder/Demultiplexer.
    Name of the LAB RA or LAB JF : nd time:
    TRA Mobile no:

    Lab Student Name: SNEH PRATAP


    sl.no.:
    1
    Mobile no.: 9810031629
    Reg.no.:22BCE2965
    Email ID: sneh.pratap2022@vitstudent.ac.in

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