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Latch

This document provides information on the DM74ALS373 Octal D-Type TRI-STATE Transparent Latch integrated circuit. It describes the features and specifications of the chip, which includes 8 transparent D-type latches, TRI-STATE buffer-type outputs that can directly drive bus lines, and an output control input that can place the outputs in normal or high-impedance states. The document also provides pinout diagrams, electrical characteristics, and application information.

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Eduardo Monge Jiménez
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© Attribution Non-Commercial (BY-NC)
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203 views

Latch

This document provides information on the DM74ALS373 Octal D-Type TRI-STATE Transparent Latch integrated circuit. It describes the features and specifications of the chip, which includes 8 transparent D-type latches, TRI-STATE buffer-type outputs that can directly drive bus lines, and an output control input that can place the outputs in normal or high-impedance states. The document also provides pinout diagrams, electrical characteristics, and application information.

Uploaded by

Eduardo Monge Jiménez
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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DM74ALS373 Octal D-Type TRI-STATE Transparent Latch

March 1996

DM74ALS373 Octal D-Type TRI-STATE Transparent Latch


General Description
These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads The high-impedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components They are particularly attractive for implementing buffer registers I O ports bidirectional bus drivers and working registers The eight latches of the ALS373 are transparent D-type latches While the enable (G) is high the Q outputs will follow the data (D) inputs When the enable is taken low the output will be latched at the level of the data that was set up A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state In the high-impedance state the outputs neither load nor drive the bus lines significantly The output control does not affect the internal operation of the latches That is the old data can be retained or new data can be entered even while the outputs are off

Features
Y Y

Switching specifications at 50 pF Switching specifications guaranteed over full temperature and VCC range Advanced oxide-isolated ion-implanted Schottky TTL process Functionally and pin for pin compatible with LS TTL counterpart Improved AC performance over LS373 at approximately half the power TRI-STATE buffer-type outputs drive bus lines directly

Connection Diagram
Dual-In-Line Package

TL F 6220 1

Order Number DM74ALS373WM DM74ALS373N or DM74ALS373SJ See NS Package Number M20B M20D or N20A

TRI-STATE is a registered trademark of National Semiconductor Corporation C1996 National Semiconductor Corporation TL F 6220 RRD-B30M36 Printed in U S A

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Absolute Maximum Ratings


Supply Voltage Input Voltage Voltage Applied to Disabled Output Operating Free Air Temperature Range DM74ALS Storage Temperature Range Typical iJA N Package M Package 7V 7V 5 5V 0 C to a 70 C
b 65 C to a 150 C

Note The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics table are not guaranteed at the absolute maximum ratings The Recommended Operating Conditions table will define the conditions for actual device operation

57 0 C W 76 0 C W

Note This product meets application requirements of 500 temperature cycles from b 65 C to a 150 C

Recommended Operating Conditions


Symbol VCC VIH VIL IOH IOL tW tSU tH TA
The (

Parameter Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Width of Enable Pulse High or Low Data Setup Time Data Hold Time Free Air Operating Temperature

Min 45 2

Nom 5

Max 55

Units V V

08
b2 6

V mA mA ns ns ns

24 10 10v 7v 0 70

v) arrow indicates the negative edge of the enable is used for reference

Electrical Characteristics
over recommended operating free air temperature range All typical values are measured at VCC e 5V TA e 25 C Symbol VIK VOH Parameter Input Clamp Voltage High Level Output Voltage Conditions VCC e 4 5V II e b18 mA VCC e 4 5V VCC e 4 5V to 5 5V IOH e b400 mA VOL II IIH IIL IO IOZH IOZL ICC Low Level Output Voltage Input Current at Max Input Voltage High Level Input Current Low Level Input Current Output Drive Current Off-State Output Current High Level Voltage Applied Off-State Output Current Low Level Voltage Applied Supply Current VCC e 4 5V VCC e 5 5V VIH e 7V VCC e 5 5V VIH e 2 7V VCC e 5 5V VIL e 0 4V VCC e 5 5V VCC e 5 5V VO e 2 7V VCC e 5 5V VO e 0 4V VCC e 5 5V Outputs Open Outputs High Outputs Low Outputs Disabled 9 16 17 VO e 2 25V
b 30

Min

Typ

Max
b1 5

Units V V V

IOH e b2 6 mA

24 VCC b 2

33

IOL e 24 mA

0 35

05 01 20
b0 1 b 112

V mA mA mA mA mA mA mA mA mA

20
b 20

16 25 27

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Switching Characteristics over recommended operating free air temperature range (Note 1)
Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Output Enable Time to High Level Output Output Enable Time to Low Level Output Output Disable Time from High Level Output Output Disable Time from Low Level Output Conditions VCC e 4 5V to 5 5V RL e 500X CL e 50 pF From Data Data Enable Enable Output Control Output Control Output Control Output Control To Any Q Any Q Any Q Any Q Any Q Any Q Any Q Any Q Min 2 4 6 7 6 5 2 2 Max 12 16 22 23 18 20 10 12 Units ns ns ns ns ns ns ns ns

Note 1 See Section 5 for test waveforms and output load

Function Table
Output Control L L L H Enable G H H L X D H L X X Output Q H L Q0 Z

L e Low State H e High State X e Dont Care Z e High Impedance State Q0 e Previous Condition of Q

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Logic Diagram

TL F 6220 2

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Physical Dimensions inches (millimeters)

S O Package (M) Order Number DM74ALS373WM NS Package Number M20B

Small Outline Package (SJ) Order Number DM74ALS373SJ NS Package Number M20D

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DM74ALS373 Octal D-Type TRI-STATE Transparent Latch

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N) Order Number DM74ALS373N NS Package Number N20A

LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user
National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018

2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness

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National Semiconductor Europe Fax a49 (0) 180-530 85 86 Email europe support nsc com Deutsch Tel a49 (0) 180-530 85 85 English Tel a49 (0) 180-532 78 32 Fran ais Tel a49 (0) 180-532 93 58 Italiano Tel a49 (0) 180-534 16 80

National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960

National Semiconductor Japan Ltd Tel 81-043-299-2308 Fax 81-043-299-2408

National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

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