A Simplified Test Set for Op Amp Characterization

National Semiconductor
A Simplified Test Set for Op Application Note 24
Amp Characterization M. Yamatake
April 1986

INTRODUCTION POWER SUPPLY

The test set described in this paper allows complete quanti- Basic waveforms and dc operating voltages for the test set
tative characterization of all dc operational amplifier param- are derived from a power supply section comprising a posi-
eters quickly and with a minimum of additional equipment. tive and a negative rectifier and filter, a test set voltage
The method used is accurate and is equally suitable for lab- regulator, a test circuit voltage regulator, and a function gen-
oratory or production testÐfor quantitative readout or for erator. The dc supplies will be discussed in the section deal-
limit testing. As embodied here, the test set is conditioned ing with detailed circuit description.
for testing the LM709 and LM101 amplifiers; however, sim- The waveform generator provides three output functions, a
ple changes discussed in the text will allow testing of any of g 19V square wave, a b 19V to a 19V pulse with a 1% duty
the generally available operational amplifiers. cycle, and a g 5V triangular wave. The square wave is the
Amplifier parameters are tested over the full range of com- basic waveform from which both the pulse and triangular
mon mode and power supply voltages with either of two wave outputs are derived.
output loads. Test set sensitivity and stability are adequate The square wave generator is an operational amplifier con-
for testing all presently available integrated amplifiers. nected as an astable multivibrator. This amplifier provides
The paper will be divided into two sections, i.e., a functional an output of approximately g 19V at 16 Hz. This square
description, and a discussion of circuit operation. Complete wave is used to drive junction FET switches in the test set
construction information will be given including a layout for and to generate the pulse and triangular waveforms.
the tester circuit boards. The pulse generator is a monostable multivibrator driven by
FUNCTIONAL DESCRIPTION the output of the square wave generator. This multivibrator
is allowed to swing from negative saturation to positive satu-
The test set operates in one of three basic modes. These
ration on the positive going edge of the square wave input
are: (1) Bias Current Test; (2) Offset Voltage, Offset Current
and has a time constant which will provide a duty cycle of
Test; and (3) Transfer Function Test. In the first two of these
approximately 1%. The output is approximately b19V to
tests, the amplifier under test is exercised throughout its full a 19V.
common mode range. In all three tests, power supply volt-
ages for the circuit under test may be set at g 5V, g 10V,
g 15V, or g 20V.

TL/H/7190 – 1

FIGURE 1. Functional Diagram of Bias Current Test Circuit

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C1995 National Semiconductor Corporation TL/H/7190 RRD-B30M115/Printed in U. S. A.

The triangular wave generator is a dc stabilized integrator The bias current display of Figure 2 has the added advan-
driven by the output of the square wave generator and pro- tage that incipient breakdown of the input stage of the de-
vides a g 5V output at the square wave frequency, inverted vice under test at the extremes of the common mode range
with respect to the square wave. is easily detected.
The purpose of these various outputs from the power supply If either or both the upper or lower trace in the bias current
section will be discussed in the functional description. display exhibits curvature near the horizontal ends of the
oscilloscope face, then the bias current of that input of the
BIAS CURRENT TEST
amplifier is shown to be dependent on common mode volt-
A functional diagram of the bias current test circuit is shown age. The usual causes of this dependency are low break-
in Figure 1 . The output of the triangular wave generator and down voltage of the differential input stage or current sink.
the output of the test circuit, respectively, drive the horizon-
tal and vertical deflection of an oscilloscope. OFFSET VOLTAGE, OFFSET CURRENT TEST
The device under test, (cascaded with the integrator, A7), is The offset voltage and offset current tests are performed in
connected in a differential amplifier configuration by R1, R2, the same general way as the bias current test. The only
R3, and R4. The inputs of this differential amplifier are driven difference is that the switches S5a and S5b are closed on
in common from the output of the triangular wave generator the same half-cycle of the triangular wave input.
through attenuator R8 and amplifier A8. The inputs of the The synchronous operation of S5a and S5b forces the ampli-
device under test are connected to the feedback network fier under test to draw its input currents through matched
through resistors R5 and R6, shunted by the switch S5a and high and low input resistors on alternate halves of the input
S5b. triangular wave. The difference between the voltage drop
The feedback network provides a closed loop gain of 1,000 across the two values of input resistors is proportional to the
and the integrator time constant serves to reduce noise at difference in input current to the two inputs of the amplifier
the output of the test circuit as well as allowing the output of under test and may be measured as the vertical spacing
the device under test to remain near zero volts. between the two traces appearing on the face of the oscillo-
scope.
The bias current test is accomplished by allowing the device
under test to draw input current to one of its inputs through Offset voltage is measured as the vertical spacing between
the corresponding input resistor on positive going or nega- the trace corresponding to one of the two values of source
tive going halves of the triangular wave generator output. resistance and the zero volt baseline. Switch S6 and Resis-
This is accomplished by closing S5a or S5b on alternate tor R9 are a base line chopper whose purpose is to provide
halves of the triangular wave input. The voltage appearing a baseline reference which is independent of test set and
across the input resistor is equal to input current times the oscilloscope drift. S6 is driven from the pulse output of the
input resistor. This voltage is multiplied by 1,000 by the function generator and has a duty cycle of approximately
feedback loop and appears at the integrator output and the 1% of the triangular wave.
vertical input of the oscilloscope. The vertical separaton of Figure 3 is a photograph of the various waveforms present-
the traces representing the two input currents of the amplifi- ed during this test. Offset voltage and offset current are
er under test is equivalent to the total bias current of the displayed at a sensitivity of 1 mV and 100 nA per division,
amplifier under test. respectively, and both parameters are displayed over a
The bias current over the entire common mode range may common mode range of g 10V.
be examined by setting the output of A8 equal to the amplifi-
er common mode range. A photograph of the bias current
oscilloscope display is given as Figure 2 . In this figure, the
total input current of an amplifier is displayed over a g 10V
common mode range with a sensitivity of 100 nA per vertical
division.

TL/H/7190 – 3
FIGURE 3. Offset Voltage, Offset Current
and Common Mode Rejection Display

TL/H/7190–2
FIGURE 2. Bias Current and Common
Mode Rejection Display

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 TL/H/7190 – 4
FIGURE 4. Functional Diagram of Transfer Function Circuit

TRANSFER FUNCTION TEST

A functional diagram of the transfer function test is shown in
Figure 4 . The output of the triangular wave generator and
the output of the circuit under test, respectively, drive the
horizontal and vertical inputs of an oscilloscope.
The device under test is driven by a g 2.5 mV triangular
wave derived from the g 5V output of the triangular wave
generator through the attenuators R11, R12, and R1, R3 and
through the voltage follower, A7. The output of the device
under test is fed to the vertical input of an oscilloscope.
Amplifier A7 performs a dual function in this test. When S7 is
closed during the bias current test, a voltage is developed
across C1 equal to the amplifier offset voltage multiplied by
the gain of the feedback loop. When S7 is opened in the
transfer function test, the charge stored in C1 continues to
provide this offset correction voltage. In addition, A7 sums
TL/H/7190 – 5
the triangular wave test signal with the offset correction volt-
age and applies this sum to the input of the amplifier under FIGURE 5. Transfer Function Display
test through the attenuator R1, R3. This input sweeps the Gain is displayed as the slope, DVOUT/DVIN of the transfer
input of the amplifier under test g 2.5 mV around its offset function. Gain linearity is indicated change in slope of the
voltage. VOUT/VIN display as a function of output voltage. This dis-
play is particularly useful in detecting crossover distortion in
Figure 5 is a photograph of the output of the test set during
a Class B output stage. Output swing is measured as the
the transfer function test. This figure illustrates the function
vertical deflection of the transfer function at the horizontal
of amplifier A7 in adjusting the dc input of the test device so
extremes of the display.
that its transfer function is displayed on the center of the
oscilloscope face.
The transfer function display is a plot of VIN vs VOUT for an
amplifier. This display provides information about three am-
plifier parameters: gain, gain linearity, and output swing.

3
NOTE: All resistor valves
in ohms.
All resistors (/4W, 5%
unless specified
otherwise.

TL/H/7190 – 6
FIGURE 6. Power Supply and Function Generator

DETAILED CIRCUIT DESCRIPTION comprising R7, R8, R9, R10, and R26. The output of this
divider is a 10V to a 2.5V according to the position of S2a
POWER SUPPLIES
and is fed to the non-inverting, gain-of-two amplifier, A2. A2
As shown in Figure 6 , which is a complete schematic of the is powered from a 28V and provides a 20V to a 5V at its
power supply and function generator, two power supplies output. A3 is a unity gain inverter whose input is the output
are provided in the test set. One supply provides a fixed of A2 and which is powered from b28V. The complementa-
g 20V to power the circuitry in the test set; the other pro- ry outputs of amplifiers A2 and A3 provide dc power to the
vides g 5V to g 20V to power the circuit under test. circuit under test.
The test set power supply regulator accepts a 28V from the LM101 amplifiers are used as A2 and A3 to allow operation
positive rectifier and filter and provides a 20V through the from one ground referenced voltage each and to provide
LM100 positive regulator. Amplifier A1 is powered from the protective current limiting for the device under test.
negative rectifier and filter and operates as a unity gain in-
verter whose input is a 20V from the positive regulator, and FUNCTION GENERATOR
whose output is b20V. The function generator provides three outputs, a g 19V
The test circuit power supply is referenced to the a 20V square wave, a b19V to a 19V pulse having a 1% duty
output of the positive regulator through the variable divider cycle, and a g 5V triangular wave. The square wave is the

4
basic function from which the pulse and triangular wave are operated synchronously from the output of Q11. During the
derived, the pulse is referenced to the leading edge of the transfer function test, Q6 and Q7 are switched on continu-
square wave, and the triangular wave is the inverted and ously by turning off Q11. R42 and R45 maintain the gates of
integrated square wave. the FET switches at zero gate to source voltage for maxi-
Amplifier A4 is an astable multivibrator generating a square mum conductance during their on cycle. Since the sources
wave from positive to negative saturation. The amplitude of of these switches are at the common mode input voltage of
this square wave is approximately g 19V. The square wave the device under test, these resistors are connected to the
frequency is determined by the ratio of R18 to R16 and by output of the common mode driver amplifier, A8.
the time constant, R17C9. The operating frequency is stabi- The input for the integrator-feedback buffer, A7, is selected
lized against temperature and power regulation effects by by the FET switches Q4 and Q5. During the bias current and
regulating the feedback signal with the divider R19, D5 and offset voltage offset current tests, A7 is connected as an
D6. integrator and receives its input from the output of the de-
Amplifier A5 is a monostable multivibrator triggered by the vice under test. The output of A7 drives the feedback resis-
positive going output of A4. The pulse width of A5 is deter- tor, R40. In this connection, the integrator holds the output
mined by the ratio of R20 to R22 and by the time constant of the device under test near ground and serves to amplify
R21C10. The output pulse of A5 is an approximately 1% duty the voltages corresponding to bias current, offset current,
cycle pulse from approximately b19V to a 19V. and offset voltage by a factor of 1,000 before presenting
them to the measurement system. FET switches Q4 and Q5
Amplifier A6 is a dc stabilized integrator driven from the am-
are turned on by switch section S1b during these tests.
plitude-regulated output of A4. Its output is a g 5V triangular
wave. The amplitude of the output of A6 is determined by FET switches Q4 and Q5 are turned off during the transfer
the square wave voltage developed across D5 and D6 and function test. This disconnects A7 from the output of the
the time constant Radj C14. DC stabilization is accomplished device under test and changes it from an integrator to a
by the feedback network R24, R25, and C15. The ac attenua- non-inverting unity gain amplifier driven from the triangular
tion of this feedback network is high enough so that the wave output of the function generator through the attenua-
integrator action at the square wave frequency is not de- tor R33 and R34 and switch section S1a. In this connection,
graded. amplifier A7 serves two functions; first, to provide an offset
voltage correction to the input of the device under test and,
Operating frequency of the function generator may be var-
second, to drive the input of the device under test with a
ied by adjusting the time constants associated with A4, A5,
g 2.5 mV triangular wave centered about the offset voltage.
and A6 in the same ratio.
During this test, the common mode driver amplifier is dis-
TEST CIRCUIT abled by switch section S1a and the vertical input of the
A complete schematic diagram of the test circuit is shown in measurement oscilloscope is transferred from the output of
Figure 7 . The test circuit accepts the outputs of the power the integrator-buffer, A7, to the output of the device under
supplies and function generator and provides horizontal and test by switch section S1d. S2a allows supply voltages for
vertical outputs for an X-Y oscilloscope, which is used as the device under test to be set at g 5, g 10, g 15, or g 20V.
the measurement system. S2b changes the vertical scale factor for the measurement
oscilloscope to maintain optimum vertical deflection for the
The primary elements of the test circuit are the feedback
particular power supply voltage used. S4 is a momentary
buffer and integrator, comprising amplifier A7 and its feed-
contact pushbutton switch which is used to change the load
back network C16, R31, R32, and C17, and the differential
on the device under test from 10 kX to 2 kX.
amplifier network, comprising the device under test and the
feedback network R40, R43, R44, and R52. The remainder of A delay must be provided when switching from the input
the test circuit provides the proper conditioning for the de- tests to the transfer function tests. The purpose of this delay
vice under test and scaling for the oscilloscope, on which is to disable the integrator function of A7 before driving it
the test results are displayed. with the triangular wave. If this is not done, the offset cor-
rection voltage, stored on C16, will be lost. This delay be-
The amplifier A8 provides a variable amplitude source of
tween opening FET switch Q4, and switch Q5, is provided by
common mode signal to exercise the amplifier under test
the RC filter, R35 and C19.
over its common mode range. This amplifier is connected as
a non-inverting gain-of-3.6 amplifier and receives its input Resistor R41 and diodes D7 and D8 are provided to control
from the triangular wave generator. Potentiometer R37 al- the integrator when no test device is present, or when a
lows the output of this amplifier to be varied from g 0 volts faulty test device is inserted. R41 provides a dc feedback
to g 18 volts. The output of this amplifier drives the differen- path in the absence of a test device and resets the integra-
tial input resistors, R43 and R44, for the device under test. tor to zero. Diodes D7 and D8 clamp the input to the integra-
tor to approximately g .7 volts when a faulty device is inserted.
The resistors R46 and R47 are current sensing resistors
which sense the input current of the device under test. FET switch Q1 and resistor R28 provide a ground reference
These resistors are switched into the circuit in the proper at the beginning of the 50-ohm-source, offset-voltage trace.
sequence by the field effect transistors Q6 and Q7. Q6 and This trace provides a ground reference which is indepen-
Q7 are driven from the square wave output of the function dent of instrument or oscilloscope calibration. The gate of
generator by the PNP pair, Q10 and Q11, and the NPN pair, Q1 is driven by the output of monostable multivibrator A5,
Q8 and Q9. Switch sections S1b and S1c select the switch- and shorts the vertical oscilloscope drive signal to ground
ing sequence for Q8 and Q9 and hence for Q6 and Q7. In during the time that A5 output is positive.
the bias current test, the FET drivers, Q8 and Q9, are Switch S3, R27, and R28 provide a 5X scale increase during
switched by out of phase signals from Q10 and Q11. This input parameter tests to allow measurement of amplifiers
opens the FET switches Q6 and Q7 on alternate half cycles with large offset voltage, offset current, or bias current.
of the square wave output of the function generator. During Switch S5 allows amplifier compensation to be changed for
the offset voltage, offset current test, the FET drivers are 101 or 709 type amplifiers.

5
 NOTE: All resistors 1/4W, 5% unless specified otherwise *2N3819
matched for on resistance within 200X Select for BVGS l 45V TL/H/7190 – 7
FIGURE 7. Test Circuit

CALIBRATION 3. Transfer Function (Figure 5 )

Calibration of the test system is relatively simple and re- VIN 0.5 mV/div.
quires only two adjustments. First, the output of the main VOUT 5V/div. @ Vs g 20V
regulator is set up for 20V. Then, the triangular wave gener-
5V/div. @ Vs g 15V
ator is adjusted to provide g 5V output by selecting Radj.
This sets the horizontal sweep for the X-Y oscilloscope 2V/div. @ Vs g 10V
used as the measurement system. The oscilloscope is then 1V/div. @ Vs g 5V
set up for 1V/division vertical and for a full 10 division hori- DVOUT
zontal sweep. Gain e
DVIN
Scale factors for the three test positions are:
CONSTRUCTION
1. Bias Current Display (Figure 2 )
Test set construction is simplified through the use of inte-
Ibias total 100 nA/div. vertical
grated circuits and etched circuit layout.
Common Mode Voltage Variable horizontal
Figure 8 gives photographs of the completed tester. Figure
2. Offset Voltage-Offset Current (Figure 3 ) 9 shows the parts location for the components on the circuit
Ioffset 100 nA/div. vertical board layout of Figure 10 . An attempt should be made to
Voffset 1 mV/div. vertical
Common Mode Voltage Variable horizontal

6
adhere to this layout to insure that parasitic coupling be- S3, S4 Grayhill 30-1 Series 30 subminiature
tween elements will not cause oscillations or give calibration pushbutton switch
problems.
S5, S6 Alcoswitch MST-105D SPDT
Table I is a listing of special components which are needed
to fit the physical layout given for the tester. CONCLUSIONS
TABLE I. Partial Parts List A semi-automatic test system has been described which will
T1 Triad F-90X completely test the important operational amplifier parame-
ters over the full power supply and common mode ranges.
S1 Centralab PA2003 non-shorting
The system is simple, inexpensive, easily calibrated, and is
S2 Centralab PA2015 non-shorting equally suitable for engineering or quality assurance usage.

TL/H/7190 – 8
FIGURE 8a. Bottom of Test Set

7
 TL/H/7190 – 9
FIGURE 8b. Front Panel

TL/H/7190 – 10
FIGURE 8c. Jacks

8
 TL/H/7190 – 11
FIGURE 9. Component Location, Top View

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A Simplified Test Set for Op Amp Characterization

TL/H/7190 – 12
FIGURE 10. Circuit Board Layout

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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