ES2C4: Computer Architecture and Systems

2022-2023

Lecture 10
Instruction Set Architecture (ISA) -
Part 1
Dr. D. D. Iliescu
School of Engineering, University of Warwick

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Contents 1. I/O Interfaces
1.1. Peripherals
1.2. Interface Units
2. Memory Mapped I/O and
1. Assembly Language and Embedded I/O Systems
2.1. Memory mapped I/O

Instructions 2.2. Embedded I/O Systems

3. Nucleo32 boards *
3.1. Pinout
3.2. MCU
1.1. Introduction to ARM architecture 3.3. GPIO

1.2. Instructions
2. Operand Locations
2.1. Registers
2.2. Constants/Immediates
2.3. Memory
3. Operations
3.1. Logical Operations
3.2. Shift Instructions
3.3. Multiplication Operations * Only as further
information for lab
and assignment,
not for exam

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1. Assembly Language and Instructions
1.1. Introduction to ARM architecture

▪ Computer architecture refers to attributes that have a direct impact on the

logical execution of a program, in other words the programmer’s view of the
computer.
• Also known as Instruction Set Architecture (ISA) Insert figure here
• Defined by the instruction set and operand locations
• Instruction: words/commands in a computer language
- Assembly Language: human-readable representation of the computer’s native language
- Machine language: computer-readable format (1’s and 0’s)
• Instruction set: computer’s vocabulary
• Operands:
- Source operands: values on which operations are performed
- Destination operands: are (or hold) the result of operations
• Instructions need a physical address from which to get the value of operands:
- Registers, Constants and Memory
▪ Microarchitecture: how to implement an architecture in hardware
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1. Assembly Language and Instructions
1.1. Introduction to ARM architecture (cont.)

▪ Different architectures exists (e.g. ARM, x86, PowerPC)

• ARM developed in the 1980’s by Advanced RISC Machines company is a family
of RISC - ISAs
• RISC-V architecture developed at UC Berkeley in 2010 is an open standard ISA
• RISC-V architecture was the first widely accepted open-source computer
architecture
• Nearly 10 billion ARM processors sold/year
• ARM instruction operands includes registers, memory and constants

▪ Architecture Design Principles

• Simplicity favours regularity
• Make the common case fast
• Smaller is faster
• Good design demands good compromises

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1. Assembly Language and Instructions
1.2. Instructions

▪ Addition C Code Generic RISC-V assembly code

source
a = b + c; add a, b, c operands
mnemonic ARM Assembly code
destination ADD R0, R1, R2
operands

▪ Subtraction C Code Generic RISC-V assembly code

a = b - c; sub a, b, c
• (only the mnemonic changes) mnemonic ARM Assembly code
SUB R0, R1, R2
Simplicity favours regularity
- Consistent instruction format
- Same number of operands (two sources and one destination)
- Easier to encode and handle in hardware

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1. Assembly Language and Instructions
1.2. Instructions (cont.)

▪ More complex code is handled by multiple simple instructions.

C Code Generic RISC-V assembly code

a = b + c - d; add t, b, c
Semicolon indicates a
//Comment in C sub a, t, d single line comment
ARM Assembly code (the only comment
allowed)
ADD R4, R1, R2 ;Comment in ARM
SUB R0, R4, R3
Make the common case fast
- RISC-V and ARM includes only simple, commonly used instructions
- Hardware to decode and execute instructions can be simple, small, and fast
- More complex instructions (that are less common) performed using multiple simple
instructions
- RISC V and ARM are reduced instruction set computer (RISC), with a small number of
simple instructions
- Other architectures, such as Intel’s x86, are complex instruction set computers (CISC)
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1. I/O Interfaces
Summary

▪ 1.1. Introduction to ARM architecture

• Instruction Set Architecture (ISA)
• Microarchitecture – implementation of ISA in hardware
• Architecture Design Principles

▪ 1.2. Instructions
• reduced instruction set
• Complex instructions performed using multiple simple instructions

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2. Operand Locations
2.1. Registers

▪ Registers are faster than memory.

▪ ARM has 16 registers.
▪ Each register is 32 bits.
▪ ARM architecture is a “32-bit architecture” because it operates on 32-bit
data. (until recently, when it has been extended to 64 bit)
C Code ARM assembly code
Preceeded by letter R a = b + c; ;R0=a, R1=b, R2=c
Register Name Use ADD R0, R1, R2
R0 Argument, return value, temporary variables
R1, R2, R3 Argument, temporary variables
R4 to R11 Saved variables C Code ARM assembly code
R12 Temporary variable
a = b + c - d; ADD R4, R1, R2
R13 (SP) Stack pointer SUB R0, R4, R3
R14 (LR) Link register
R15 (PC) Program counter ARM register set

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2. Operand Locations
2.2. Constants/Immediates

▪ Immediates are unsigned 8 to 12-bit numbers

▪ Many instructions can use constants or immediate operands, for example:
ADD and SUB
▪ Value is immediately available from instruction
C Code ARM assembly code
a = 4 + 7; ;R5 = a, R6 = c
c = a – 5; ADD R5, #4, #7
SUB R6, R5, #5
▪ Generate small constants using move (MOV)
▪ Constant must have < 8 bits of precision
▪ MOV can also be used on two registers (copy the value of one into another)
C Code ARM assembly code
//int: 32-bit signed word ;R5 = a, R6 = b, R7 = c
inta = 18; MOV R5, #18 ; a = 18 dec. not.
int b = 0xA2; MOV R6, #0xA2 ; b = 0xA2 hex.
int c = a; MOV R7, R5 ; c = a
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2. Operand Locations
2.3. Memory

▪ Instructions sometimes require too much data to fit in only 16 registers.

▪ Therefore, more data is stored in memory.
▪ Memory is large, but slow.
▪ Commonly used variables are kept in registers.
▪ Byte-Addressable Memory
• Each data byte has unique address
• 32-bit word = 4 bytes, so word address increments by 4

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2. Operand Locations
2.3. Memory (cont.) e.g. Read a word of data at
memory address 8 into R3
▪ Memory read called load
ARM assembly code
▪ Mnemonic: load register (LDR) MOV R2, #0
▪ Format: LDR R0, [R1, #12] LDR R3, [R2, #8]
▪ Address calculation:
Address = (R2+ 8) = 0+8 = 8
• add base address (R1) to the offset (12) R3 = 0x01EE2842 after load
• address = (R1 + 12)
▪ Result:
• R0 holds the data at memory address
(R1 + 12)

▪ Any register may be used as base

address

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2. Operand Locations
2.3. Memory (cont.) e.g. Store the value held in R7 into
memory word 3
▪ Memory write called stores
ARM assembly code
▪ Mnemonic: store register (STR) MOV R5, #0
▪ Format: STR R3, [R5, #12] STR R7, [R5, #0x0C]
▪ Address calculation:
Address = (R5+ 3x4) = 0+12 = 0x0C will
• add base address (R5) to the offset (12) hold, after store, the value of
• address = (R5 + 12) R7 = 0x40F30788
▪ Result:
• R3 holds the data to be stored at
memory address (R5 + 12)

▪ Any register may be used as base

address

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 2. Operand Locations
2.3. Memory (cont.)

▪ Big-Endian & Little-Endian Memory

▪ How to number bytes within a word?
▪ Little-endian: byte numbers start at the little (least significant) end (LSB)
▪ Big-endian: byte numbers start at the big (most significant) end (MSB)

▪ It doesn’t really matter which addressing type used – except when the two
systems need to share data!
Jonathan Swift’s Gulliver’s Travels:
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2. Operand Locations
2.3. Memory (cont.)

▪ Example
▪ Write the assembly code to do the following:
R1 = 5 MOV R1, #5

R2 = 70 MOV R2, #70

R8 = 0xC0 MOV R8, #0xC0

R0 = R1 – R8, SUB R0, R1, R8

R9 = R0 + R2 – R1 SUB R12, R2, R1

ADD R9, R0, R12

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2. Operand Locations
Summary

▪ 2.1. Registers
• 16 Registers
• 32 bit

▪ 2.2. Constants/Immediates
• Value is immediately available from instruction
• Use command MOV

▪ 2.3. Memory
• Byte-Addressable Memory
• Memory command LDR and STR
• Use Litthe-endian unless specified otherwise

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3. Operations
3.1. Logical Operations

▪ These bitwise operations are carried out on two sources.

▪ The first source is always a register and the second source is either an
immediate or a register.
▪ The mnemonics for logical operations are:
• AND, ORR, EOR (XOR), BIC (Bit Clear), MVN (MoVe and Not)

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3. Operations
3.1. Logical Operations (cont.)

▪ AND or BIC (Bit Clear): useful for masking bits

• E.g.: Masking all but the least significant byte of a value
0xF234012F AND 0x000000FF = 0x0000002F
0xF234012F BIC 0xFFFFFF00 = 0x0000002F

▪ ORR: useful for combining bit fields

• E.g.: Combine 0xF2340000 with 0x000012BC:
0xF2340000 ORR 0x000012BC = 0xF23412BC

▪ MVN (MoVe and Not): use for inverting bit fields

• E.g.: Invert 0x0A (binary (all zeros) 1010 -> invert to (all ones) 0101
• MVN R2, #0x0A = 0xFFFFFF05

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3. Operations
3.2. Shift Instructions
Note: An equivalent ASL not used,
▪ LSL: logical shift left by N as it is the same with LSL
• Fill the LSBs with 0
• Original MSBs drop off
• Equivalent to multiplying by 2N Note: An equivalent ROL not used,
e.g. LSL R0, R7, #5 ; R0=R7 << 5 as it is the same as ROR with a
complementary amount
▪ LSR: logical shift right
• Fill the MSBs with 0
• Original LSBs drop off
LSR R3, R2, #31 ; R3=R2 >> 31
▪ ASR: arithmetic shift right
• Fill the MSBs with the old MSB
• Equivalent to dividing by 2N
ASR R9, R11, R4 ; R9=R11 >>> R47:0
▪ ROR: rotate right
• Circular rotation - Empty spots filled with bits shifted off the other end
ROR R8, R1, #3 ; R8=R1 ROR 3
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3. Operations
3.2. Shift Instructions (cont.)

▪ Shift operations using immediates

▪ Shift operations using registers

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3. Operations
3.3. Multiplication Operations

▪ MUL: 32 ×32 multiplication, 32-bit result

• E.g.: MUL R1,R2,R3
Result: R1 = (R2 x R3) 31:0

▪ UMULL: Unsigned multiply long, 32 ×32 multiplication, 64-bit result

• E.g.: UMULL R1,R2,R3,R4
Result: {R1,R2} = R3 x R4 (R2,R3 unsigned)

▪ SMULL: Signed multiply long: 32 ×32 multiplication, 64-bit result

• E.g.: SMULL R1,R2,R3, R4
Result: {R1,R2} = R3 x R4 (R2,R3 signed)

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3. Operations
Summary

▪ 3.1. Logical Operations

• AND, ORR, EOR, BIC, MVN

▪ 3.2. Shift Instructions

• LSL, LSR, ASR, ROR

3.3. Multiplication Operations

• MUL, UMULL, SMULL

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