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Approved by All India Council for Technical Education, New Delhi

Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
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Practical Record File

Student Name : …………………..……………………………………

Course : …………… Branch : ………………

Year : …………… Semester : ………………

Roll No. : …………… Session : Jan.-June 2023

S. No. Experiment Name Page No. Remark

8
 Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
Contact- +91-88889995932/43/45, E-Mail- info@vitmindore.com, Website- www.vitm.edu.in

EXPERIMENT NO…1
AIM:

To verify the Demorgan’s theorem.

APPARATUS REQUIRE0D:

Digital logic trainer and Patch cords.

THEORY:

The digital signals are discrete in nature and can only assume one of the two values O and 1.A
number system based on these two digit is known as binary number system. This is basic of all digital
systems like computers, calculators etc.

Binary Variables can be represented by letter symbol such A,B,X,Y.

The variable can have only one of the two variable possible values at anytime i.e. ‘0’ or ‘1’
Demerger’s Theorems can be proved by fist considering the two variable case and then extending this
result.

DEMORGAN’S THEOREM’S:

PROCEDURE:

DEMORGAN’S THE -1

1. Make the circuit dia. As in fig and connect the inputs of the gate to the input state sockets A,B
and C and output to the output indicators.
2. Set the input combinations one by one by putting input state switches A,B and C either in 0or
1 state.
3. Now verify the output with the help of Truth Table (1)

TRUTH TABLE (1)

A B C A B C A.B.C A.B.C A+B+C

0 0 0 1 1 1 0 1 1
0 0 1 1 1 0 0 1 1
0 1 0 1 0 1 0 1 1
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0 1 1 1 0 0 0 1 1
1 0 0 0 1 1 0 1 1
1 0 1 0 1 0 0 1 1
1 1 0 0 0 1 0 1 1
1 1 1 0 0 0 1 0 0

DEMORGAN’S THEOREM-2:

Make the circuit dia. As shown in fig and connect the inputs o the gate to the input state sockets
A,B and C and output to the output indicators.

1. Set the input combinations one by the putting input state switches A,B and C either ‘0’ or ‘1’
state.
2. Now verify the output with the help of Truth Table (2).

TRUTH TABLE (2)

A B C A B C A.B.C A+B+C A+B+C

0 0 0 1 1 1 0 1 1
0 0 1 1 1 0 1 0 0
0 1 0 1 0 1 1 0 0
0 1 1 1 0 0 1 0 0
1 0 0 0 1 1 1 0 0
1 0 1 0 1 0 1 0 0
1 1 0 0 0 1 1 0 0
1 1 1 0 0 0 1 0 0

RESULT:
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Experiment No. 2

Aim: To study and verify the Truth Tables of AND, OR, NOT, NAND, NOR EXOR logic
gates for positive logic.

Apparatus Required:
Digital logic trainer and Patch cords

Theory:
AND Gate: A multi-input circuit in which the output is 1 only if all inputs are 1.The
symbolic representation of the AND gate is:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are
high. A dot (.) is used to show the AND operation i.e. A.B .

OR gate : A multi-input circuit in which the output is 1 when any input is 1.

The symbolic representation of the OR gate is shown:

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs
are high. A plus (+) is used to show the OR operation.
NOT gate: The output is 0 when the input is 1, and the output is 1 when the
input is 0. The symbolic representation of an inverter is :
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The NOT gate is an electronic circuit that produces an inverted version of the input at its
output. It is also known as an inverter. If the input variable is A, the inverted output is
known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the
outputs.
NAND gate: AND followed by INVERT. It is also known as universal gate.The symbolic
representation of the NAND gate is:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The
outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate
with a small circle on the output. The small circle represents inversion.

NOR gate: OR followed by inverter. It is also known as universal gate.The symbolic

representation is:

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs
of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small
circle on the output. The small circle represents inversion.

EXOR gate: The output of the Exclusive –OR gate, is 0 when it’s two inputs are
the same and it’s output is 1 when its two inputs are different.It is also known as Anti-
coincidence gate.

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its
two inputs are high. An encircled plus sign ( ) is used to show the EOR operation.

Observation Table: LED ON (RED light): Logic 1

LED OFF (Green Light): Logic 0
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Input variables: A, B
Output variable: Y

S. Input(A) Input(B) Output Output Output Output Output Output

(OR) ___ (AND) (OR) (NAND) ____ (NOR) ______ (XOR)
No LED LED
Y=A Y=AB Y=A+B Y = AB Y= A+B Y=A B
1
2
3
4
Calculation:

Results and Analysis:

NOT Gate: When logic 1 is applied to one of NOT gate of 7404 IC, then output becomes
zero. When input LED is ON (RED), the output LED become OFF (Green) vice versa.

OR Gate: The output of an OR gate is a 1 if one or the other or both of the inputs are 1, but a
0 if both inputs are 0. When One or the other or Both of the input LEDS are ON (RED Light),
then output LED is ON(RED) otherwise Output LED is OFF(Green Light)

AND Gate: The output of an AND gate is only 1 if both its inputs are 1. For all other
possible inputs the output is 0.When both the LEDS are On, then output LED is ON (RED
Light) otherwise Output LED is OFF.

NOR Gate: The output of the NOR gate is a 1 if both inputs are 0 but a 0 if one or the other
or both the inputs are 1.
NAND Gate: The output of the NAND gate is a 0 if both inputs are 1 but a 1 if one or the
other or both the inputs are 0.

EXOR gate: The output of the XOR gate is a 1 if either but not both inputs are 1 and a 0 if
the inputs are both 0 or both 1.

RESULT:
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Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
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EXPERIMENT NO…3
AIM: - To verify the Half Adder & Full Adder

APPARATUS REQUIRED:

Digital logic trainer and Patch cords.

THEORY:

Half Adder
With the help of half adder, we can design circuits that are capable of performing simple
addition with the help of logic gates.
Let us first take a look at the addition of single bits.
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10
These are the least possible single-bit combinations. But the result for 1+1 is 10. Though this
problem can be solved with the help of an EXOR Gate, if you do care about the output, the
sum result must be re-written as a 2-bit output.
Thus the above equations can be written as
0+0 = 00
0+1 = 01
1+0 = 01
1+1 = 10
Here the output ‘1’of ‘10’ becomes the carry-out. The result is shown in a truth-table below.
‘SUM’ is the normal output and ‘CARRY’ is the carry-out.

INPUTS OUTPUTS
A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
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1 1 0 1
From the equation it is clear that this 1-bit adder can be easily implemented with the help of
EXOR Gate for the output ‘SUM’ and an AND Gate for the carry. Take a look at the
implementation below.

For complex addition, there may be cases when you have to add two 8-bit bytes together.
This can be done only with the help of full-adder logic.

Full Adder
This type of adder is a little more difficult to implement than a half-adder. The main
difference between a half-adder and a full-adder is that the full-adder has three inputs and two
outputs. The first two inputs are A and B and the third input is an input carry designated as
CIN. When a full adder logic is designed we will be able to string eight of them together to
create a byte-wide adder and cascade the carry bit from one adder to the next.
The output carry is designated as COUT and the normal output is designated as S. Take a
look at the truth-table.
INPUTS OUTPUTS
A B CIN COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
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1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
From the above truth-table, the full adder logic can be implemented. We can see that the
output S is an EXOR between the input A and the half-adder SUM output with B and CIN
inputs. We must also note that the COUT will only be true if any of the two inputs out of the
three are HIGH.
Thus, we can implement a full adder circuit with the help of two half adder circuits. The first
will half adder will be used to add A and B to produce a partial Sum. The second half adder
logic can be used to add CIN to the Sum produced by the first half adder to get the final S
output. If any of the half adder logic produces a carry, there will be an output carry. Thus,
COUT will be an OR function of the half-adder Carry outputs.
.

Single Bit full Adder

With this type of symbol, we can add two bits together taking a carry from the next lower
order of magnitude, and sending a carry to the next higher order of magnitude. In a computer,
for a multi-bit operation, each bit must be represented by a full adder and must be added
simultaneously. Thus, to add two 8-bit numbers, you will need 8 full adders which can be
 Vikrant Institute of Technology and Management, Indore
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formed by cascading two of the 4-bit blocks. The addition of two 4-bit numbers is shown
below.
RESULT:
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EXPERIMENT NO…4
AIM:

To verify the Half Subtractor Full Subtractor

APPARATUS REQUIRED:

Digital logic trainer and Patch cords.

THEORY

The arithmetic operation, subtraction of two binary digits has four possible elementary
operations, namely,

0-0=0
0 - 1 = 1 with 1 borrow
1-0=1
1-1=0

In all operations, each subtrahend bit is subtracted from the minuend bit. In case of the
second operation the minuend bit is smaller than the subtrahend bit, hence 1 is borrowed.

HALF SUBTRACTOR:

A combinational circuit which performs the subtraction of two bits is called half
subtractor. The input variables designate the minuend and the subtrahend bit, whereas the
output variables produce the difference and borrow bits. Half subtractor

The half-subtractor is a combinational circuit which is used to perform subtraction of two

bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D (difference) and B
(borrow).

INPUTS OUTPUTS
A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
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1 1 0 0

Full subtractor

A combinational circuit which performs the subtraction of three input bits is called
full subtractor. The three input bits include two significant bits and a previous borrow bit. A
full subtractor circuit can be implemented with two half subtractors and one OR gate. As in
the case of the addition using logic gates, a full subtractor is made by combining two half-
subtractors and an additional OR-gate. A full subtractor has the borrow in capability (denoted
as BORIN in the diagram below) and so allows cascading which results in the possibility
of multi-bit subtraction. The circuit diagram for a full subtractor is given below.

INPUTS OUTPUTS
A B CIN Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
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RESULT:
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EXPERIMENT NO…5

AIM: -To verify the characteristic table of RS and JK Flip flops .

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. Digital IC trainer kit 1
2. NOR gate IC 7402
3. NOT gate IC 7404
4. AND gate ( three input ) IC 7411
5. NAND gate IC 7400
6. Connecting wires As required

THEORY:

A Flip Flop is a sequential device that samples its input signals and changes its output states
only at times determined by clocking signal. Flip Flops may vary in the number of inputs
they possess and the manner in which the inputs affect the binary states.

RS FLIP FLOP:

The clocked RS flip flop consists of NAND gates and the output changes its state with
respect to the input on application of clock pulse. When the clock pulse is high the S and R
inputs reach the second level NAND gates in their complementary form. The Flip Flop is
reset when the R input high and S input is low. The Flip Flop is set when the S input is high
and R input is low. When both the inputs are high the output is in an indeterminate state.

JK FLIP FLOP:
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The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave
like S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and
the clock pulse, similarly the output Q’ is ANDed with J input and the Clock pulse. When
the clock pulse is zero both the AND gates are disabled and the Q and Q’ output retain their
previous values. When the clock pulse is high, the J and K inputs reach the NOR gates.
When both the inputs are high the output toggles continuously. This is called Race around
condition and this must be avoided.

RS FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:
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CHARACTERISTIC TABLE:

CLOCK INPUT PRESENT NEXT STATUS

PULSE S R STATE (Q) STATE(Q+1)
1 0 0 0 0
2 0 0 1 1
3 0 1 0 0
4 0 1 1 0
5 1 0 0 1
6 1 0 1 1
7 1 1 0 X
8 1 1 1 X

JK FLIP FLOP

LOGIC SYMBOL:

CIRCUIT DIAGRAM:
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CHARACTERISTIC TABLE:

CLOCK INPUT PRESENT NEXT STATUS

PULSE J K STATE (Q) STATE(Q+1)
1 0 0 0 0
2 0 0 1 1
3 0 1 0 0
4 0 1 1 0
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 0

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and observe the status of all the flip flops.
RESULT:
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Experiment No:-06
KIRCHOFF’S ( KCL & KVL ) LAWS

OBJECTIVES:
1. To study Kirchoff’s Current Law ( KCL)
2. To study Kirchoffs Volatge Law .( KVL)

EQUIPMENTS REQUIRED: DC Voltmeter (0 -75), Digital Multimeter Ammeter (1-0-1

mA) 3 No.

COMPONENT USED:- R1=150W , R2=100W, R5 =150W, R3=120W

CIRCUIT DIAGRAM:-

THEORY:-
In many circuits , in which various components are used are in either parallel, in series, or in
series parallel for example , a circuit with two or more batteries connected in its different
branches . Another example is an unbalanced bridge circuit. Hence rules o series & parallel
circuits are not applicable. Such circuits can be easily solved with help of kirchoffs law which
are as follows.
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1. Kirchoff’s current Law

2. Kirchoff’s voltage law.

KIRCHOFF’S CURRENT LAW

It states that in any network of conductors, the algebraic sum of currents meeting at appoint
(at a junction) is ‘0’ In other words, the total current leaving a junction is equal to the total
current entering that point.

Incoming signal + ve & outgoing signal – ve .

Explanation:
Consider in case of 5 currents meeting at junction A of the network is shown in fig.1. All the
currents entering the junction would be taken as positive where as those leaving is
Taken as –ve .

Determination of algebraic sign

We will follow a very simple sign conversion which would apply equally to IR drop &
battery emf’s . A rise (or increase) in voltage would be considered as +ve. & given and + ve
sign & a fall (or decrease) in voltage would be considered -ve & hence given as – ve sign.
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Battery EMF
While going round a loop ( in a direction of our own choice ) if we go from the –ve terminal
of battery to its +ve terminal , there is rise in potential , hence this EMF should be given as +
ve signal .On the other hand if we go from its + ve terminal ti its –ve terminal , there’s a fall
in potential , hence this battery EMF should be given as –ve sign . It is important to note that
algebraic sign of battery EMF is independent of the direction of current flow. (Whether
clockwise or in anticlockwise) through the branch which the battery is connected)

IR drops in series.
If we go through a circuit in the same direction as its current, then there is a fall or decrease
in potential for the simple reason that current always flow from higher to lower potential.
Hence this IR drop should be taken as –ve. However, if we go around the loop in direction
opposite to that of the current there is a rise in voltage. Hence these IR should be taken as
+ve. It clears that the algebraic sign of IR drop across a resister depends on the direction of
current through that
resistor. Consider a
loop, for example,
ABCDA shown in the
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Starting from point A, if we go around the mesh in clockwise direction the different EMF &
IOR drop will have following values and signs.

I1R1 ------ is –ve (fall in potential)

I2R2 ----- - is +ve (rise in potential)
E2 ------ is –ve (fall in potential
I 3R3 ------ is –ve (fall in potential)
E1--------- is +ve (rise in potential)
I 4R4--------- is –ve (fall in potential)

According to KVL
I 1R1 – I 2R2 – E2 - I 3R3 + E1 – I 4R4 = 0
- I1R1 + I2R2 - I3R3 - I4R4 = E2 - E1
I1R1- I2R2 + I3R3 + I4R4 = E1- E2
VR1- VR2 + VR3 + VR4 = E1- E2

PROCEDURE:-
1) Study the front panel of the kit
2) For Kirchoff’s current Law.
1) Connect S1 and S2 to +ve of supply with patch chords.
2) Keep S3 and S4 in off position.
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3) select any point on the kit (For example point B)

4) Connect ammeter in I1, I2 & I3.
5) Switch on the power supply and adjust input voltage V1 & V2
6) Measure the currents & note down the reading
7) Now with the noted value of I1 . I2 & I3 verify the Kirchoffs current law as point B (
I1+I2=I3)
8) Repeat step 4 onwards for different values of V1 & V2.

For Kirchoffs Voltage Law-

1) Connect S1 and S2 to +ve of supply with patch chords.
2) Keep S3 and S4 in off position
3) Switch on the power supply and adjust V1 and V2
4) Measure VR1 & VR2 , VR3 ,VR4& VR5.
5) Select any desired loop say loop (1), apply KVL as per given in
observation table and verify the result.
6) Repeat step (2) onwards for different V1 and V2.

RESULT:-
The current approaching to the junction is equal to currents leaving from the junction. So
KCL is verified similarly voltage supplied to desired loop equals to voltage drop by same
loop so KVL is verified.
 Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
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EXPERIMENT NO: - 7

AIM: To Study the Superposition Theorem

COMPONENT USED: R1=150 W, R2= 330 W, R3=560W

INSTRUMENTS REQUIRED: Required Circuit, Digital Multimeter, Patch Chords, Mili

ammeter

CIRCUIT DIAGRAM:

THEORY: The theory should cover details about following points.

1. Statement of superposition theorem.

2. This theory consist of verification of superposition theorem consist of

Measuring the currents in cases such as those shown in Fig (c) & (d), & Checking the total
current in the case shown in Fig (a)
 Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
Contact- +91-88889995932/43/45, E-Mail- info@vitmindore.com, Website- www.vitm.edu.in

PROCEDURE:

1. Study the circuit diagram provided on the front panel of the kit

2. Note the values of all resistors R1, R2, R3.

3. Connect the miliammeters in the circuit at the respective places.

4. Connect terminal A to 1 & B to 2. Let the current through R2 has to be determined by

using this theorem as shown in Fig.(a)

5. Switch ON the power supply.

6. Keep the voltage source V1 & V2 constant at desired voltage. Note its values. The reading
of three ammeters .

7. Remove V2(By connecting B to 1) only V1 is acting ,find out the voltage V1, Current I2a
,I3a as per Fig (d)

8. Similarly remove V1(by connecting A to 2). Only V2 is acting, find out voltage
V2,Current I1b & I2b as per Fig (c) .
 Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
Contact- +91-88889995932/43/45, E-Mail- info@vitmindore.com, Website- www.vitm.edu.in

9. Algebraically add the current in (7 & 8) above to compare with the currents in (6) above, to
verify the theorem.

10. Verify the theoretical & practical values of current.

11. Repeat the above procedure for different values of V1 & V2.

OBSERVATION TABLE:

CASE 1: BOTH V1 & V2 ARE ACTING

S. No. V1 V2 I1 I2 I3

CASE 2: ONLY V1 IS ACTING ALONE & V2 IS DEACTIVATE

S. No. V1 V2 I1a I2a I3a

CASE 3: ONLY V2 IS ACTING & V1 IS DEACTIVATE

S. No. V1 V2 I1b I2b I3b

CALCULATION:

According to superposition theorem, the branch current (I) is given by

 Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
Contact- +91-88889995932/43/45, E-Mail- info@vitmindore.com, Website- www.vitm.edu.in

I1= I1a + I1b, I2 = I2a + I2b, I3 = I3a + I3b

RESULT & CONCLUSION:

The superposition theorem is applicable to any other input output Variable and to any no. of
inputs.
 Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
Contact- +91-88889995932/43/45, E-Mail- info@vitmindore.com, Website- www.vitm.edu.in

Experiment No:- 08

AIM: - To Plot the phasor diagram of R-L-C Series Circuit.

APPARATUS:-

1 phase, 230 V dimmerstat -1 no.

0-1 Amp, AC Ammeter - 1 No.

0-300 V , AC Voltmeter - 1 No

0-300 V ,1 A, Wattmeter -1 No

Choke 230 V 50 Hz, 0.675 A -1 No.

Rheostat 100 ohm,1.2 A -1 No.

Capacitor 2.5 μf -1 No.

THEORY:-
 Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
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THEORY:- The theory should cover details about following points.

1) Resistance, Reactance and Impedance.

2) Series Resonance

3) Types of Loads

4) Power Factor

5) Expression for current

PROCEDURE:-
 Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
Contact- +91-88889995932/43/45, E-Mail- info@vitmindore.com, Website- www.vitm.edu.in

1. Connect the circuit as shown in figure.

2. Ensure that the dimmerstat is at zero position.

3. Switch on 1-phase ac supply.

4. Increase the output voltage of the dimmerstat slowly upto 100V

5. Note down the readings of ammeter, voltmeter and wattmeter

6.Repeat the above procedure for different values of output voltages of dimmerstat.

PRECAUTIONS:-

1. All connections should be perfectly tight.

2. Do not switch on the supply until and unless the connections are checked by the teacher.

3. Ensure the dimmer stat at zero position and all rheostats to maximum resistance position
before switching the supply ON.

4. Avoid error due to parallel while reading the meters.

5. The current flowing through the rheostat should not exceed their ratings.

OBSERVATION & CALCULATION:

S. Supply
I W VR VL VC R XL XC CosΦ Φ
No. Voltage
 Vikrant Institute of Technology and Management, Indore
Approved by All India Council for Technical Education, New Delhi
Affiliated by Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal and Devi Ahilya Vishwavidyalaya, Indore
Campus: Village- Borkhedi, Mhow, Dist-Indore, Behind Veterinary College AB Road Indore (MP) - 453441
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CONCLUSION: From the phasor diagram for Series R-L-C circuit we have seen that
calculated and observed values of Vs are same.