Introduction To Modulation - Comm - ch1.3
Introduction To Modulation - Comm - ch1.3
B. High-Level AM Transmitter
3. Phase Modulation:
• PM is a type of angle modulation and it is defined as the change in phase of
the carrier signal in correspondence with the amplitude of the message signal.
• Whereas, the frequency and amplitude of the carrier signal stays as constant.
• When the amplitude is positive the phase change in one direction and when
the amplitude is negative phase change in the opposite direction
• The phase of the modulating signal has got infinite points where the phase
shift can take place.
Phase Modulation Waveform and Mathematical Expression
Digital Modulation:
Mathematical Expression:
Mathematical Expression:
Where:
Example of FSK:
Phase Shift Keying (PSK): Phase Shift Keying (PSK) is a digital modulation
technique where the phase of the carrier signal is varied to represent binary data.
Each phase shift corresponds to a different symbol, which encodes the data.
Example of PSK:
Types of PSK:
A. Binary Phase Shift Keying (BPSK): Uses two phases, typically 180 degrees
apart, to represent binary 0 and 1.
B. Quadrature Phase Shift Keying (QPSK): Uses four distinct phase shifts
(e.g., 0°, 90°, 180°, and 270°) to represent two bits of data per symbol.
Advantages of PSK:
• The process in which analog signal is changed into digital signal based on
the information of digital signal.
• Sine-wave is defined by three characteristic i.e. amplitude, frequency and
Phase.
• Binary numbers are defined by 0 & 1.
• Application of analog to digital modulation is to transmission of digital
data over telephonic wire.
M-ary ASK:
• M-ary ASK uses MMM different amplitude levels to represent log2M bits
per symbol. Each amplitude level corresponds to a unique pattern of bits.
• Amplitude Levels: M Levels: Each level represents a different
combination of bits. For example, in 4-ASK (M=4), there are 4 different
amplitude levels representing 2 bits per symbol.
• Mathematical Expression: s(t)=AiCos(2πfct), Where Ai represents one of
the M possible amplitudes.
• Spectral Efficiency: Higher than binary ASK because more bits are
transmitted per symbol, making better use of available bandwidth.
• Error Performance: As M increases, the amplitude levels become closer
together, which can lead to increased susceptibility to noise and
interference, impacting error rates.
• Example:
4-ASK (M=4): Uses 4 different amplitude levels to represent 2 bits per
symbol (00, 01, 10, 11).
16-ASK (M=16): Uses 16 different amplitude levels to represent 4 bits per
symbol.
Advantages of M-ary ASK :
• Higher Data Rate: Transmits more bits per symbol compared to binary
ASK.
• Efficient Bandwidth Use: Can achieve higher data rates within the same
bandwidth.
Disadvantages of M-ary ASK ::
• Noise Sensitivity: As the number of amplitude levels increases, the signal
becomes more susceptible to noise and interference.
• Complexity: Requires more complex detection and demodulation
techniques to differentiate between multiple amplitude levels.
M-ary FSK
• M-ary FSK extends the basic Frequency Shift Keying (FSK) concept by
using MMM different frequencies to represent log2M\log_2 Mlog2M
bits per symbol. Each frequency corresponds to a unique combination of
bits.
• Frequency Levels: M Frequencies: The signal uses MMM different
frequencies to represent log2M bits. For instance, in 4-FSK (M=4), there
are 4 different frequencies, each representing 2 bits.
• Symbol Rate: The rate at which symbols (each representing log2M bits)
are transmitted.
• Bit Rate: The product of the symbol rate and log2M, representing the
number of bits transmitted per second.
• Spectral Efficiency: Generally less efficient compared to M-ary ASK, as
more bandwidth is required to accommodate multiple frequencies.
• Error Performance: M-ary FSK can provide better performance in noisy
environments compared to ASK because the frequency differences are
more distinguishable than amplitude differences.
M-ary PSK:
• 4-PSK (QPSK): Uses 4 distinct phase shifts (0°, 90°, 180°, 270°) to
represent 2 bits per symbol.
• 8-PSK: Uses 8 different phase shifts to represent 3 bits per symbol.
• 16-PSK: Uses 16 different phase shifts to represent 4 bits per symbol.
ASK Modulator
• ASK Modulation
The ASK modulator
block diagram
comprises of the
carrier signal
generator, the binary
sequence from the
message signal and
the band-limited
filter. Following is
the block diagram of
the ASK Modulator.
• The carrier generator,
sends a continuous high-frequency carrier. The binary sequence from the
message signal makes the unipolar input to be either High or Low. The high
signal closes the switch, allowing a carrier wave.
• Hence, the output will be the carrier signal at high input. When there is low
input, the switch opens, allowing no voltage to appear. Hence, the output
will be low.
• The band-limiting filter, shapes the pulse depending upon the amplitude
and phase characteristics of the band-limiting filter or the pulse-shaping
filter.
Asynchronous Demodulator
FSK Demodulator
• There are different methods for demodulating a FSK wave. The main
methods of FSK detection are asynchronous detector and synchronous
detector.
• The synchronous detector is a coherent one, while asynchronous detector
is a non-coherent one.
• The block diagram of Binary Phase Shift Keying consists of the balance
modulator which has the carrier sine wave as one input and the binary
sequence as the other input. Following is the diagrammatic representation.
• The modulation of BPSK is done using a balance modulator, which
multiplies the two signals applied at the input.
• For a zero binary input, the phase will be 0° and for a high input, the phase
reversal is of 180°.
• Following is the diagrammatic representation of BPSK Modulated output
wave along with its given input.
BPSK Demodulator
• By recovering the band-limited message signal, with the help of the mixer
circuit and the band pass filter, the first stage of demodulation gets
completed.
• The base band signal which is band limited is obtained and this signal is
used to regenerate the binary message bit stream.
• In the next stage of demodulation, the bit clock rate is needed at the
detector circuit to produce the original binary message signal.
• If the bit rate is a sub-multiple of the carrier frequency, then the bit clock
regeneration is simplified.
• The block diagram of BPSK demodulator consists of a mixer with local
oscillator circuit, a bandpass filter, a two-input detector circuit.
QPSK Modulator
• The QPSK Demodulator uses two product demodulator circuits with local
oscillator, two band pass filters, two integrator circuits, and a 2-bit parallel
to serial converter. Following is the diagram for the same.
• The two product detectors at the input of demodulator simultaneously
demodulate the two BPSK signals.
• The pair of bits are recovered here from the original data.
• These signals after processing, are passed to the parallel to serial converter.
• DPSK encodes data by varying the phase of the carrier signal relative to
the previous symbol, rather than the absolute phase. This means that the
information is carried by the difference between successive symbols.
• Phase Difference Encoding:: Phase Shifts: Data is encoded in the
difference between the phases of consecutive symbols. For instance, in
binary DPSK (BDPSK), a change in phase represents a binary 1, while no
change represents a binary 0.
• Symbol Rate: The rate at which symbols (phase changes) are transmitted.
Each symbol in DPSK represents a change in phase from the previous
symbol.
• Bit Rate: The product of the symbol rate and the number of bits per
symbol.
• Error Performance: DPSK can offer improved robustness against phase
noise and synchronization errors compared to traditional PSK because it
relies on phase differences rather than absolute phase values.
• Mathematical Representation: For binary DPSK (BDPSK), the modulated signal
s(t)s(t)s(t) can be expressed as:
•
Where: Ac is the amplitude of the carrier signal. Fc is the carrier frequency. Φ
represents the phase shift.
DPSK Modulator
DPSK Demodulator
• In DPSK demodulator, the phase of the reversed bit is compared with the
phase of the previous bit. Following is the block diagram of DPSK
demodulator.
• From the above figure, it is evident that the balance modulator is given the
DPSK signal along with 1-bit delay input.
• That signal is made to confine to lower frequencies with the help of LPF.
• Then it is passed to a shaper circuit, which is a comparator or a Schmitt
trigger circuit, to recover the original binary data as the output.