December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

Reviews of Accelerator Science and Technology

Vol. 4 (2011) 11–40


c World Scientific Publishing Company
DOI: 10.1142/S1793626811000616

Ion Implantation for Semiconductor Doping and Materials Modification

Lawrence A. Larson∗ and Justin M. Williams

Ingram School of Engineering, Texas State University at San Marcos
RFM 5210, 601 University Drive, San Marcos, TX 78666, USA
∗Larry.Larson@txstate.edu

Michael I. Current
Current Scientific
1729 Comstock Way, San Jose, CA 95124, USA
currentsci@aol.com
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com
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In the 50-plus years since the patent was issued to William Shockley in 1957, ion implantation has become a key process
in the commercial production of semiconductor devices, advanced engineering materials and photonic devices. This
article reviews the fundamental concepts of production ion implanters for both the processes used in manufacturing
and also in the design of the tools themselves. Recent publications in the application areas of semiconductors and
materials modification are summarized, focusing on the attendant process effects. These results demonstrate that ion
implantation is a well understood technology with abundant and evolving applications.

Keywords: Ion implantation; semiconductor processing; materials modification.

1. Introduction a dose range from 1010 to over 1018 ions/cm2 . The

This article aims to review the technology of ion specific applications include doping of semiconductor
beam implantation and its many applications in junctions and a rapidly increasing number of materi-
materials processing. The majority of the commercial als modification uses throughout the manufacture of
applications of ion implantation are in semiconduc- ICs and PV systems. The key application areas are
tor processing and we will review recent advances in shown Fig. 1.
process space, machine types, semiconductor appli- In addition to IC and PV uses, ion implan-
cations and process effects including shallow junc- tation is used in the fabrication of hardened met-
tion source/drain extension [SDE], junction leakage, als, polycarbonate foils, nuclear reactor containment
source/drain contact [SDC] and SDE strain, photore- structures, catalysts and micro-electro-mechanical
sist, photovoltaic [PV] doping, and semiconductor (MEMS) devices, discussed later in this article.
process issues. The other major area of commer-
cial application of ion processing is materials mod-
ification applications and processes; major sections 3. Implanter Machine Types
within that area include tool hardening, H-cut for The acceleration and distribution of ions over target
silicon-on-insulator [SOI] and PV, silicide stability, surfaces over the wide dose and energy ranges shown
and a collection of similar applications that can be in Fig. 1 has led to the development of many and
considered materials modification using an ion beam. diverse system designs for operation in specific areas
of the ion implantation “phase space.” The majority
of implantation machines operate in the ion energy
2. Dose and Energy Ranges
regime from a fraction of a keV to ≈200 keV, with
Ions are accelerated for implantation into integrated “medium current” tools spanning this energy range
circuit (IC) and photovoltaic (PV) devices over an with beam currents of a few mA or less and “high
energy range from ≈100 eV to nearly 10 MeV and current” tools operating at maximum beam currents

11
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12 L. A. Larson, J. M. Williams & M. I. Current

Fig. 1. Ion energy and dose for key applications in IC and Fig. 2. Yearly unit sales of ion implantation systems, mostly
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

PV device manufacturing. for IC device fabrication.

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of several 10 s of mA. The class of “high energy” tools the primary implanter vendors sell over US$1 billion
provide energetic ions in the range from ≈20 keV to in new machines in a year with active plant expan-
several MeV for doping of deep junctions for Flash sion. In addition, there is a well-developed group of
memories and CMOS-based optical sensors. Versions secondary vendors who provide spare parts, refur-
of high energy implanters have been developed to bishment and upgrade kits, implant services and the
provide mA beam currents of protons at energies up dopant and other materials to support continuous
to 4 MeV for use in splitting of ≈100 µm thick free- operations as well as a vigorous market for resale of
standing Si membranes. A recent addition to the ion older machines to developing markets.
implant tool set is a class of “high dose” tools which
either have a simplified beamline structure to provide 4. Doping Planar CMOS Transistors
an ion “shower” at high ion flux rates or forgo the
use of accelerating columns entirely and utilize wafer The principal doped regions of a transistor are shown
bias to draw ions out of nearby plasma in “plasma in Fig. 3, where the full CMOS device has approx-
immersion” ion implant (PIII) systems. This diver- imately equal numbers of n- and p-type channel
sity of machine types can be expected to increase regions (the area under the gate oxide between the
in the near future, with several “hybrid” designs in source and drain extension junctions) with opposite
development dedicated for high throughput doping doping in each type, hence the “C” (complemen-
of Si-based PV junctions. The design principles and tary) in CMOS. The most important junction in the
operational characteristics of these various types of
ion implantation systems are discussed in the follow-
ing section.
The industrial demand for ion implantation sys-
tems, almost entirely for doping of IC transistors, has
led to the development of a set of tool vendors with
many members active in this field since the 1970s.
The yearly unit sales of commercial implanters is
shown in Fig. 2. The yearly number of units sold aver-
ages around 300, with large fluctuations year to year,
usually with a six-year cycle, due to variations in
facility construction and expansion schedules, tran-
sitions to new wafer sizes and the opening of new
markets for IC devices. With a typical selling price
of US$4 million for a fully-featured production tool, Fig. 3. Principal doped regions of a planar CMOS transistor.
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

Ion Implantation for Semiconductor Doping and Materials Modification 13

transistor is the extension region under the spac- This deep peak suppresses “soft errors” arising from
ers because the location and doping levels in the local charge upsets from ionizing radiation from
extensions determine the threshold voltage and drive cosmic rays and other sources. In Flash memory
current. The extension junctions in advanced logic devices, some wells are themselves isolated by sur-
devices are “ultra-shallow,” approximately 10 nm, rounding deeper doped regions of an opposite type,
with desired doping levels above 1020 carriers/cm3. forming “triple well” structures so that opposite
The deeper contact junctions connected to the polarity biases can be sustained during cell program-
source/drain extensions often also contain additional ming which are independent of the background Si
elements to provide carrier mobility enhancing strain wafer ground reference. Even deeper well structures,
to the channel region; doped SiGe alloy epi in pMOS extending to several microns deep, are formed in
transistors (providing compressive channel strain) CMOS imager devices by implants of dopants at
and C, added by implant or selective epi (provid- energies above 5 MeV in some cases.
ing tensile strain) in the nMOS contacts. The con-
tact junctions are often capped by “raised” regions,
5. System on a Chip (SOC) Doping
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metal contacts to the source/drain junctions are suf- Complex control and logic circuits can require more
ficiently far away from the extension and channel to than 40 implant steps per finished device. The bal-
prevent metal shorts and reduce current flow crowd- ance of chip speed and power consumption is often
ing heating during transistor operations. The dop- accomplished by operating various regions of com-
ing in the region just under the metal contacts is plex “system on a chip” (SOC) devices with different
often enhanced by additional shallow implants to threshold voltages and drive current characteristics.
reduce contact resistance and thereby increase tran- This is achieved by forming transistors with locally
sistor drive currents. specific implant conditions and by adjustments in
The region below the source/drain contacts other factors such as the gate dimensions and gate
and extensions, the CMOS “well,” has carefully oxide thickness. The dose and energy distribution of
engineered doping in a series of opposite type a modern 28 nm SOC process is shown in Fig. 4,
implants compared to the source/drain junctions. where over 40 implant steps are used in the pro-
The source/drain extensions are bounded by an extra cess [1]. The implants near and above 100 keV are
well doping “halo,” usually formed by a set of angled the well doping, the lower dose implants between 10
implants before the gate spacer cladding is put in and 100 keV are mainly the various halo and shallow
place. The extra doping level in the halos is intended
to suppress the lateral encroachment of the source
depletion layer into the channel area and thereby
stabilize the transistor threshold voltage character-
istics and reduce off-state currents. As we will see
later, in the discussion of junction leakage currents,
halo doping can have deleterious effects by increasing
the reverse bias junction leakage through enhanced
band-to-band tunneling, and so the halo doping lev-
els are one of the many aspects of the transistor dop-
ing that must be balanced in process of “integration”
of the final IC design and production flow.
The doping profile of CMOS wells are often
formed with a series of multiple energy implants.
The location of shallow local doping peaks near
the channel sets the threshold voltage. There is
also a mid-well local peak to set the well punch
Fig. 4. Dose and energy distribution of ions used to fabri-
through characteristics and a deep well region peak cate 28 nm CMOS transistors. This comprises over 40 implant
to establish lateral isolation between adjacent wells. steps [1].
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14 L. A. Larson, J. M. Williams & M. I. Current

well doping and the low energy, high dose implants be supported by a single fin, so finFET transistors
are various depth S/D extensions and contacts and which need to supply high drive currents for high
the poly-Si gate doping. The non-dopant implants speed circuit operation are constructed with mul-
are primarily C profiles implanted as “cocktails” to tiple fin channels tied to source and drain contact
suppress deep diffusion of B and P doped shallow “bars.” The doping of the source and drain regions
junctions during annealing [2]. of finFET transistors presents several challenges not
present in planar CMOS designs. Most important
6. Doping of Non-Planar CMOS is the need to provide uniform doping throughout
Transistors the full exposed height of the fins at the source
and drain ends to ensure uniform threshold char-
Advanced logic and SRAM memory devices are acteristics in the undoped channel region under the
beginning to use non-planar CMOS transistors, gate. This requires that implanted ions impinge on
where the channel regions are formed from etched the sides of the fin in a controlled fashion. When
“fins” of Si with source/drain regions doped on either using beamline accelerators with high tilt angle end
side of fully depleted, undoped channels (Fig. 5). The
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stations, shadowing by adjacent fins limit the tilt

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principal advantage of “finFET”-type transistors is angles that can be used. An alternative is to employ
that the gate region surrounds the channel on three plasma immersion-type doping systems under condi-
sides (leading to the description of some types as “tri- tions that favor side wall “conformal” doping [4, 5].
gates”) so that the channel can be fully depleted by
the gate bias, leading to excellent off current levels.
A limitation of narrow fin-shaped channels is 7. PV Doping
the relatively low levels of drive currents that can Doping of junctions and contact regions in PV cells
is a relatively new and rapidly growing application of
ion implantation techniques [6]. The main advantage
of implant doping is that the doping levels in the
front surface junction and the contact regions under
the metal grid lines can be separately and accurately
set to provide optimal PV efficiency. Advanced PV
cell designs, with p- and n-type junctions on the
backside of the PV cell and a fully exposed (no
metal line) frontside, require the doping of densely
patterned interdigitated junctions of opposite dop-
ing types on cell backside, another situation where
doped junctions can be efficiently formed by implan-
tation techniques. This is discussed in detail in a later
section of the paper.

8. Ion Types
Although singly ionized, atomic ions, such as B+ ,
P+ , As+ , etc., are widely used for ion implantation
purposes, many other types of ions are used as well.
Higher charge states are often used to obtain higher
energy ions for deep implant profiles. With tandem
type accelerators (discussed in the next section), the
charge state is switched one or more times as the ions
pass through the accelerator to maximize the accel-
eration effect of the high voltage terminal, obtaining
Fig. 5. Sketch of a 3-fin non-planar transistor (top) and SEM
of a 6-fin, multi-gate inverter (bottom). Freely adapted from ions at 2 to 5 times higher kinetic energy than the
Intel images of 22 nm tri-gate CMOS transistors [3]. high voltage.
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Ion Implantation for Semiconductor Doping and Materials Modification 15

Using large molecules or clusters containing both directions. MeV ion implanters enable signifi-
many dopant atoms instead of mono-dopant ions, cantly higher energies than the typical commercial
such as B+ or BF+ 2 , can overcome two fundamen- ion implantation system. These “high energy” tools
tal limitations to providing sub-keV dopant beams provide energetic ions in the range from ≈20 keV
at commercially viable beam currents; (1) limita- to several MeV. Another group of high energy
tions on the extraction currents from the ion source implanters have been developed to provide mA beam
(Child–Langmiur law) and (2) beam transport limi- currents of protons at energies up to 4 MeV for use
tations due to ion repulsion which results in increases in splitting of ≈100 µm thick free-standing Si mem-
in the beam diameter as the ions are transported branes. A recent addition to the ion implant tool set
along a beamline (Coulomb repulsion effects). is a class of “high dose” tools which utilize wafer bias
In addition to improvements to the dopant flux to draw ions out of nearby plasma in plasma immer-
rates for shallow junction doping, the use of molec- sion ion implantation (PIII) systems operating with
ular ions increases the damage accumulation rate ion energies of a few keV or less and doses in the high
compared to single ion implants at the same equiv- 1015 to mid-1016 ions/cm2 range.
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

alent energy. Since higher damage accumulation Figure 6 illustrates the capabilities of these tool
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rates result in thicker amorphous layers, a higher sub-types in a figure with the same scaling of dose
fraction of the implanted dopant profile can be and energy as processes were overviewed in Fig. 1.
included within the amorphous layer for molecular A good overview of these concepts is reviewed by
ions, resulting in a higher fraction of dopants which Glawischnig et al. in Ref. 7.
are electrically active following recrystalization of Medium current implanters are characterized by
the Si region during the thermal anneal. Since more relatively low currents so that the power deposi-
of the implant damage is incorporated in creating tion is relatively low and single wafer processing can
the amorphous layer, which can be regrown to a be used. Standard energy ranges are 10 to 200 keV
high level of crystalline quality during the anneal, and the beam current ranges from nanoamps to a
molecular ion implants also result in lower levels of few hundred microamps. Recent tool improvements
residual lattice damage in the deep portion of the have extended the effective energy to nearly 1 MeV
profile, the “end-of-range” (EOR), resulting in lower and the current capability to a few milliamps. Sup-
defect levels in the junction depletion layer and sig- pliers marketing this type of tool have included
nificantly lower junction leakage currents. This will Axcelis Technologies Incorporated [8], Nissin Ion
be discussed in more detail in a later section of this Equipment Company [9], SEN Corporation [10],
article. Tokyo Electron Limited [11], ULVAC Technologies,
Inc. [12], and Varian Semiconductor Equipment
9. Ion Implantation Machines Associates [13].
Implanters have been classically separated into
medium and high current as the major sub-types
of machines. This designation is driven by the abil-
ity to handle the power in the beam differently for
each. Most implantation machines operate in the ion
energy regime from a fraction of a keV to ≈200 keV,
with “medium current” tools spanning this energy
range with beam currents of a few mA or less and
“high current” tools operating at maximum beam
currents of several 10 s of mA (at ≈80 keV) with a
focus on high ion flux rates, for high wafer through-
put, for low energy (<2 keV) and higher dose (5×1014
to 5×1015 ions/cm2 ) doping for “ultra-shallow” tran-
sistor junctions.
Fig. 6. Beam currents (in particle-µA) vs. energy (keV) for
More recently, advanced implant tools have been various ions in contemporary ion implantation systems. (Data
introduced which extend the useable energy scale in courtesy of Axcelis and the literature.)
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16 L. A. Larson, J. M. Williams & M. I. Current

High current implanters are characterized by rel-

atively high currents so that the power deposition is
high. Because of this, schemes must be developed to
reduce the duty cycle of the beam so that wafers
do not excessively heat the wafer and/or the pho-
toresist. Standard energy ranges are 10 to 80 or
160 keV with beam currents on the order of 10 mA.
Recent tool improvements have extended the lower
end of the energy below 500 eV and have produced
beam currents up to 30 mA. Suppliers marketing
this type of tool have included Advanced Ion Beam
Technology Inc. [14], Applied Materials [15], Axcelis
Technologies Incorporated [8], Nissin Ion Equipment
Company [9], SEN Corporation [10], Tokyo Electron
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Limited [11], ULVAC Technologies, Inc. [12], and

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Varian Semiconductor Equipment Associates [13]:

Plasma immersion ion implanters do not use a Fig. 7. Standard DC acceleration scheme. (A) source and
classic DC acceleration and instead the target is extraction, (B) magnetic ion separation, (C) post separation
beam tuning, (D) wafer target.
immersed in a plasma of the dopant and a high
energy pulse to the target pulls the dopant to it. technology is shown in Fig. 8 and early descriptions
Standard energy ranges are a few eV to a few were published by Conrad et al. [19] and Mizuno
tens of keV. Effective doses are relatively high. et al. [20]. This technology favors materials modifi-
This approach has found utility in the materials cation processes in that relatively high doses can be
modification market and low doping energy pro- easily implanted and the field lines direct the dopants
cesses for ICs. Suppliers marketing PIII and ion evenly to irregular shapes.
shower tools include Applied Materials [15], Ion MeV implanters have more complex accelera-
Beam Services [16], Nissin Ion Equipment Com- tion schemes. The major types are charge exchange
pany [9], SEN [10], and Varian Semiconductor Equip- and linear accelerator (linac). The charge exchange
ment Associates [13]. scheme is used by NEC and Varian. In this method,
MeV ion implanters are characterized by inno- a positive ion is extracted from an ion source and
vative accelerators that can accelerate beams to a converted by charge exchange to a negative ion by
few MeV. The amount of current available depends passing through a metal vapor, then accelerated as
strongly on the accelerator; however, even with low
beam currents, wafer handling for high power deposi-
tion needs to be used. Suppliers marketing this type
of tool include Axcelis Technologies Incorporated [8],
NEC Corporation [17], SEN Corporation [10], and
Varian Semiconductor Equipment Associates [13].
The standard DC acceleration scheme involves
an ion source, extraction electrodes, magnetic ion
separation, and some amount of post separation
focusing and deflection. A schematic illustration of
this scheme is shown in Fig. 7 and has been well
described in Ref. 18.
PIII has the simplest acceleration scheme. The
wafer/target is placed in the center of a plasma of
dopant ions. When the target is pulsed to a negative
potential, the positive dopant ions are accelerated
directly to the target. A schematic illustration of this Fig. 8. Plasma immersion ion implantation scheme.
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Ion Implantation for Semiconductor Doping and Materials Modification 17

a negative ion to the center of a high potential node controllable angle with respect to the beam. Many
where a second charge exchange cell is located. Two medium current designs produce a flat beam path
or more electrons are removed by collisions in this through scanning in one direction while the platform
charge exchange cell and the resulting positive ion with the wafer at the appropriate angles would trans-
is further accelerated on its return from the high late in an approximately perpendicular direction.
voltage node to ground [7]. Both beam currents
and energies are dependent on the specific accel-
erator, however they are on the order of hundreds 10. Advanced Semiconductor Processes
of microamps at a few MeV. The linac acceleration
scheme is used by Axcelis. In this scheme the beam- 10.1. Shallow junction SDE
line is a series of klystron accelerators where each Producing shallow junction depths is one of the more
individual node is tuned in both phase and frequency important development goals for the further shrink-
to accelerate a bunch of the desired ions into the ing of CMOS technology. In the International Tech-
klystron node and further accelerate that bunch as nology Roadmap for Semiconductors [22] junctions
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

it exits the node. Beam currents and energies are have the goal of 12 nm in 2010 shrinking to 7.5 nm
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even more dependent on the tool and recipe; how- in 2015. The roadmap text gave the doping related
ever, effective currents near to a milliamp at a few difficult challenge: “In the near term, while maintain-
MeV may be achieved [7]. ing the bulk planar architecture, the difficult chal-
As described above, several orders of magnitude lenge for doping of CMOS transistors is achieving
of beam current and power deposition are possi- doping profiles in the source/drain extension regions
ble through the different tool types. This has gen- to attain progressively shallower junction depths
erated several approaches to beam scanning and (∼10 nm), while concomitantly optimizing the sheet
wafer motion to most effectively expose the wafers resistance (∼500 ohms/sq), doping abruptness at
to a uniform dose at a minimum time while keeping the extension-channel junction, and extension-gate
the power deposition within limits. Early medium overlap.”
current machines had relatively low power deposi- The formation of these shallow S/D regions is
tion and could therefore continuously expose the one of the most important techniques for reduc-
wafer to the beam. Electrostatic scanning at non- ing MOSFET characteristics called “short-channel
commensurate X and Y frequencies produced uni- effects.” Several of these are threshold voltage (Vt )
form deposition in about 10 s [21]. Higher current reduction, high subthreshold leakage current, hot
machines reduced the duty cycle of the beam on electron effects and source-to-drain punch-through
wafer by mounting several wafers on a heat-sinking breakdown. These effects cause increased leakage of
disk. The beam is held stationary and the disk is the devices as the length of the device becomes
rotated and translated so that the dose is uniform small. As MOSFET devices are scaled below 100 nm
across the wafers. Nominal implant times would be in channel length and power supply voltages are
one to five minutes, however up to 25 wafers could reduced to below 2.5 V, short channel effects like
receive a relatively high dose in this time. threshold voltage lowering and bulk source-to-drain
Early processes had an average beam incidence punch-through are more critical ULSI scaling limits
angle of 7◦ which was chosen to minimize channel- than hot electron effects [1, 2]. Suppression of these
ing effects and non-uniformities due to angular dif- short channel effects in scaled-down devices requires
ferences. Later processes determined that the angle close attention to doping profiles. These device char-
of the beam to the wafer was a process variable acteristics and the effect which junction technologies
that could be used to optimize device performance. can have in engineering them are discussed more
Tools were then developed so that both tilt and twist fully by Jones and Ishida [23] and also by Chason
angles could be controlled to the best effect. For disk et al. [24].
implanters, this took the form of capability to mod- A useful figure of merit for evaluating the effec-
ify the angle of the disk in reference to the beam. tiveness of shallow junction development activities
For medium current implanters, the approach used has been the junction depth vs. sheet resistance plot
was to mount the wafer on a platform that had a shown in Fig. 9. In this plot, junction depth is one of
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18 L. A. Larson, J. M. Williams & M. I. Current

beam energy was limited by transient enhanced dif-

fusion (TED) [7]. This effect was discovered to result
from the annealing of implant damage to 110 defect
clusters, which then would slowly release the trapped
silicon interstitials resulting in enhanced diffusion for
extended times [7].
Higher effective doses and throughput may be
achieved by implanting molecules or clusters. Using
large molecules or clusters containing many dopant
atoms instead of mono-dopant ions, such as B+ ,
can overcome two fundamental limitations to pro-
viding sub-keV dopant beams at commercially viable
beam currents; (1) limitations on the extraction cur-
Fig. 9. A junction depth (Xj ) vs. sheet resistance plot for rents from the ion source (Child–Langmiur law) and
Boron implantations in silicon. Data represent three different
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(2) beam transport limitations due to ion repulsion

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advanced anneal techniques.

which results in increases in the beam diameter as
the ions are transported along a beamline (Coulomb
the axes, making evaluation of reduction of junction repulsion effects). The Child–Langmuir limit to the
depth by itself trivial. However, the other parame- ion current that can be extracted from an ideal,
ter of interest is how well the layer is activated. To a planar plasma boundary with an extraction voltage
first approximation, simple reduction on the resistiv- of V , is
ity axis indicates improvement. A useful comparator 2
Jion (A/cm ) = (4ε/9)(Ze/M )1/2 (1/d2 )(V )2/3 (1)
is to calculate and plot the hyperbolic for the resis-
tance of a layer of constant resistivity [the solid sol- where: Ze is the ion charge, M is the ion mass, d is
ubility for that dopant at a nominal temperature] on the sheath distance and ε is the permittivity of free
the same plot. space. The sharp decrease in the extractable ion cur-
Early development efforts centered on reducing rent as the extraction voltage, V , is reduced is a
implant acceleration energy [24, 25] and annealing serious limit to the use of beamline implanters in
times at increased temperature [7, 21]. The result of “drift” mode. This limitation for beamline systems
these trends was the development of implant tools at low energies has favored the development of PIII
that would have higher throughput at relatively low systems, where the plasma-to-target transport dis-
energies [21] and the development of Rapid Thermal tance is the plasma sheath distance, of the order of
Annealing tools [RTAs] that had increasing capabil- cm or less, with correspondingly high delivered ion
ity to anneal for consistent short times at higher tem- current density per pulse.
peratures [19, 26]. The annealing tool development If multi-atom ions are used instead of single-
has continued to the development of Laser Anneal- atom ions, the Child–Langmiur limitations can
ers [26, 27] and to Flash Thermal Annealers [28, 29] be relaxed by allowing extraction and drift mode
which represent the state of the art of this technology operation at energies that are multiples of the atom
at this time. number per ion higher than the single ion case. This
The throughput of implant tools is directly concept has been used for many years through the
related to the acceleration energy that is used to use of BF2 ions to allow use of extraction voltages
extract the beam and propagate that through the that are 49/11 (the ion mass ratio) times higher
beamline since it is more difficult to transport high than the extraction needed for single boron ions at
current ion beams as the energy is reduced. The the same impact velocity. The use of molecular ions,
trend to lower energies is then counter to the need for such as B10 H14 , B10 C2 H12 and B18 H22 , allows for
higher throughput. The balance of these two effects extraction at energies that are up to 20 times larger
seems to saturate on the order of 500 eV [30–32]. In than the single-ion case (Fig. 10), with correspond-
addition to the pure productivity issue, it was found ing increases in the available ion current. The use of
that the junction depth reduction as a function of massive clusters, with up to ∼104 atoms/ion, can
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Ion Implantation for Semiconductor Doping and Materials Modification 19

The development of the advanced annealing

techniques mentioned above is one effort to move the
temperature profile past the region where defect clus-
ter formation is preferred. Another research direction
is to implant mixtures of ions where additional ele-
ments suppress defect enhanced diffusion. Table 1
shows a summary of research on novel directions in
shallow junction research over the last decade.
Early work looked at simple modifications that
could be made to annealing so that the effect of
“transient enhanced diffuson” (TED) could be min-
imized. A similar approach is called “defect engi-
neering” where an attempt is carried out to make
Fig. 10. The ratio of atomic (“Boron equivalent”) and ion
energies for various Boron-containing atomic, molecular and a mix of implants such that the placement of inter-
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“massive” gas-cluster ions. The larger (100 and above) Boron stitials and vacancies is engineered such that the
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clusters are formed by adiabatic expansion cooling of gas mix- resulting defect distribution minimizes the subse-
tures of dopants and other elements, such as Ar.
quent diffusion. Another similar approach, perhaps
more effective, is to co-implant carbon or fluorine.
facilitate the use of extracted dopant fluxes that The effect of these species is to embed strain fields
are correspondingly many times higher before Child– which capture or delay the defects that cause the
Langmiur limits become relevant. various varieties of defect enhanced diffusion. Fol-
In addition to improvements to the available lowing the directions described in the discussion of
dopant flux rates for shallow junction doping, the principles of molecular and cluster ion implantation,
use of high-atom count molecular ions increases the there have been a number of works aimed at describ-
damage accumulation rate compared to single ion ing those systems. Among the molecules are octade-
implants at the same equivalent energy, which is of caborane, decaborane, carborane, and molecular ions
benefit to USJ formation. As more of the implant such as borides. Commercial approaches have been
damage is incorporated in creating the amorphous developed for octadecaborane, decaborane [51] and
layer, which can be regrown to a high level of crys- cluster implantation [52].
talline quality during anneal, molecular ion implants
also result in lower levels of residual lattice damage 10.2. Junction leakage
in the deep portion of the profile, resulting in higher Junction leakage current is a critical factor to be
quality, lower leakage junctions. limited as much as possible for high-speed server

Table 1. A summary of research on shallow junction technologies.

Shallow junction technology Additional processing Depth/Improvement comment Reference

B — 2-step anneal 33
B B atoms, such as SiB, SiB2 GeB, and Bn molecular ions 34
B — Diffused from SiGe 35
B recoil implantation recoil implantation 34
B defects Defect Engineering 34, 36
B He Defect Engineering 37, 38
B Boride enhanced Diffusion Defect Engineering 39
B C/F and Spike Anneal 40, 41, 42
B — from SOD diffusion and RTP 43
B2 H 6 — Plasma Doping, Spike RTA 4
Decaborane — — 44, 45
Octodecaborane — — 46, 47
Cluster Ion Implantation — — 48, 49
B C cluster co-implant — 50
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20 L. A. Larson, J. M. Williams & M. I. Current

circuits (where device cooling is a strong environmen-

tal and cost issue) and portable electronics (where
long battery lifetime is a premium). Design of low-
leakage CMOS processes involves nearly every facet
of transistor structure, including gate oxide thickness
and composition, implant and anneal conditions,
local strain and control of metal contamination.
Regarding transistor doping, the key factors are
the junction carrier activation, background or halo
profile doping levels and the density and position
of any residual implant defects present after com-
pletion of the thermal annealing process. The key
mechanisms for junction leakage are (1) band-to-
band tunneling, active under reverse bias, (2) carrier Fig. 12. Sketch of damage effects during implantation and
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

generation and recombination and (3) trap-assisted annealing. For a high dose implant, an amorphous layer is
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tunneling, where the last two mechanisms being formed from the surface to below the depth of the implant
profile peak, which can be recrystallized during annealing.
active for both bias directions (Fig. 11). Defects that Implant damage deeper than the amorphous layer often results
are located within the junction depletion layer are in “end of range” defects present after annealing.
particularly problematic because they can greatly
magnify leakage effects from carrier recombination they interact with local defects (by recombination or
and generation and trap-assisted tunneling. The generation).
thickness of the junction depletion layer, which is The general characteristics of residual damage
determined by the bias amplitude and the rela- formation for high-dose implants are sketched in
tive doping levels near the metallurgical junction Fig. 12. Each energetic ion that strikes a crystalline
depth location, is another prime factor. For high target, such as Si, creates a large number of point
sub-junction doping, such as a halo profile surround- and cluster defects, vacancies and interstitial target
ing a shallow source/drain extension, the depletion atoms, as it slows down and stops in the target. Most
layer thickness can be a few 10 s of nanometers, of the vacancies and interstitials rapidly recombine
greatly increasing the effects of carrier tunneling within a few milliseconds of the ion impact. How-
and decreasing the diffusion path of carriers before ever, if enough ions are implanted and other factors
apply, the target lattice is converted to an amor-
phous structure in the region around the peak of the
implant profile. The depth of the amorphous region
depends not only on the ion mass and energy and
the implanted dose but also such factors as the ion
beam current density, beam scanning rates and the
target temperature during implant. The ion type, a
single atom or a multi-atom molecule, also greatly
influences the amount and location of damage that
accumulates during the implant.
During thermal annealing, the amorphous layer
can be recrystallized to a high degree of perfection
and the near-surface dopants are electrically acti-
vated. However the implant damage below the amor-
phous/crystalline interface is often not effectively
removed, leaving “end of range” (EOR) defects.
When EOR defects are located within the junction
Fig. 11. The three key junction leakage mechanisms for a
p/n-junction under reverse bias, with residual implant damage depletion layer formed during transistor operation,
defects in the depletion layer, in a lighter doped n-substrate. high levels of leakage can occur.
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

Ion Implantation for Semiconductor Doping and Materials Modification 21

Fig. 14. Leakage current levels for a variety of implanted

Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

Fig. 13. Leakage current density vs. sub-junction doping con- junctions where the EOR damage is deeper than the junction
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centration and junction bias for an implanted junction, with a (on the left) and where the junction is deeper than the dam-
peak damage density of 1017 defects/cm3 located 20 nm below age layer (on the right), resulting in much lower leakage [54].
the junction, and an epi-doped junction, with traps located at The anneal in this study was a limited-diffusion “solid-phase
the epi/substrate interface. The dotted lines show the effects epitaxy” process at temperatures between 560◦ C and 650◦ C.
of carrier generation and trap-assisted tunneling alone, with- Three junctions were also annealed by “rapid thermal anneal-
out the contributions from band-to-band tunneling [53]. ing” (RTA) at 900◦ C for 30 s, diffusing the dopant junction
deeper and strongly reducing the observed leakage levels.

The combined impact of damage and subjunc-

tion doping on leakage current is shown in Fig. 13. importance for control of defect-driven leakage cur-
For the implanted junction, with a layer of EOR rents. In the leakage current data shown in Fig. 14,
damage located 20 nm below the junction depth, by adjusting the relative location of the EOR dam-
leakage currents increase strongly for all bias con- age layer and the dopant junction, which can be done
ditions as the depletion layer thickness is reduced for by adjusting the ion energies used for boron doping
sub-junction doping levels above 1017 dopants/cm3 . and Ge ion “preamorphization” implants, the leak-
While an epi-doped junction, with no sub-junction age current levels can be varied over a range of five
damage but a set of traps at the epi/substrate orders of magnitude [54]. If the junctions are diffused
interface shows much lower leakage levels. However, deeper with a second anneal, a similar shift in leakage
for substrate doping levels above 1018 dopants/cm3 , currents can be obtained.
band-to-band tunneling (under reverse bias) presents Although diffusing dopant junctions deeper that
strong leakage effects for both junctions. implant damage layers was a routine process choice
“Damage engineering” involves adjusting tran- through the production of 65 nm CMOS [55], later
sistor doping levels and the implant and annealing dimension shrinks relied on “diffusion-less” anneal
conditions so that the desired junctions are formed steps using short thermal pulses from flash lamps or
while damage in the depletion region is reduced or scanned laser beams. Under these thermal cycle con-
eliminated. For instance, high halo profile doping ditions, where dopant diffusion is minimized, anneal-
levels can be beneficial for controlling subthreshold ing of implant damage is also strongly curtailed
leakage, threshold voltage rolloff and other “short so the details of the implant conditions and the
channel” effects. However, the strong junction leak- net damage accumulation process become critical
age current effects, shown in Fig. 13, force tradeoffs choices. As discussed earlier (see Fig. 12) a key factor
in the process design that limit the practical halo is the thickness of the amorphous layers created by
doping levels. high dose implants. If the damage accumulation rate
The relative location and density of any regions for a particular implant is increased so that more of
containing residual defects remaining from the the implanted dopant profile is contained within the
implant damage and the position of the junction amorphous layer, a higher level of dopant activation
and the surrounding depletion layer are of primary is often achieved during the re-crystallization process
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

22 L. A. Larson, J. M. Williams & M. I. Current

during annealing. If the methods used to increase

the main peak of the damage accumulation do not
also increase the damage levels in the EOR region,
then fewer defects remain to contribute to leakage
currents.
For the same ion mass, energy and dose, the
damage accumulation during implantation can be
increased by (1) increasing the ion flux rate with
higher beam current densities and slower beam scan-
ning rates, (2) decreasing the rate of recombination
of point defects during implantation by lowering the
target temperature and (3) increasing the immedi-
ate damage rate by using ions which contain mul-
Fig. 15. Amorphous layers formed with 3 keV equivalent ions
tiple atoms, such as molecules or clusters. Present using atomic and molecular ions at implant temperatures
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

day process development programs are exploring all between 25◦ C to −30◦ C, showing the strong effect of mul-
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of these methods, with the construction of produc- tiatom impacts on damage accumulation [61].
tion implantation systems fitted with abilities to cool
wafers to temperatures of −30◦ C to −100◦C at the vigorously explored by all advanced CMOS devel-
start of the implant cycle [56, 57]. Slow ion beam opment groups.
scan rates have been combined with wafer cooling to
−80◦ C, also achieving thicker amorphous layers [58].
In addition to the machine controlled factors 10.3. Mobility enhancing strain
(beam current, scan rates and temperature), the For many decades the key to increasing CMOS tran-
form of the ions used for implantation has a major sistor speeds, drive currents and power requirements
impact on damage accumulation effects. When multi- was to shrink the lateral and vertical dimensions
ple atoms hit a target surface during the picosecond- of the transistor structure in proportion [62]. By
timeframe of ion collisions and stopping, the net 2000, with the introduction of 90 nm features, several
damage creation rate increases strongly as the physical limitations had halted this “scaling” pro-
number of atoms in the ion increases [59]. Source cess. The principal problem was that leakage currents
materials and implantation systems have been devel- through SiO2 and SiONx gate were too high to allow
oped for the use of multi-atom molecular ions, such the use of oxide thinner than about 1.2 nm. Without
as B36 Hx , where 98% of the implanted dopant is the ability to scale the gate dielectric, shrinking the
contained within the amorphous layer for a 300 eV gate length alone did not result in a net performance
implant (at room temperature) and activated [60]. gain. In order to obtain strong increases in transis-
A comparison of the effects of reduced target temper- tor performance with only modest shrinks in gate
ature and the use of molecular ions for 3 kV implants size, Intel, soon followed by others, introduced a set
is shown in Fig. 15 [61]. When atomic C ions are of intentional stressors in order to increase CMOS
used, a 10 nm thick amorphous layer is formed for drive current by increasing carrier mobility [63].
a dose of 1015 C/cm2 at an implant temperature Carrier mobility in Si depends not only on local
of −30◦C, more than twice as thick as the amor- stress levels but also on the crystalline orienta-
phous layer formed by C ions at 25◦ C. However, tion of the channel conduction (Fig. 16). In pMOS
when molecular carbon ions are used, C7 H7 and transistors, where holes are the channel carriers,
C16 H16 , a ≈10 nm amorphous layer is formed at a compressive stress is favored. In nMOS transistors,
10× lower C dose even at room temperature, indicat- where electrons are the channel carriers, tensile stress
ing that the use of molecular ions is intrinsically more is desired. An additional mobility benefit can be
efficient than cryo-conditions for enhancing damage gained by orienting pMOS channels along a (110)
accumulation rates. The “payoff” demonstration of direction and nMOS channels along (100), although
the use of enhanced damage accumulation techniques this greatly complicates circuit layout for complex
for reduction of device leakage currents is being devices and is not widely used.
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

Ion Implantation for Semiconductor Doping and Materials Modification 23

Ge fractions of ≈17%, which is now increased to

≈40% for 32 nm processes. In addition, compressive
strain is impressed on the Si regions at the bound-
aries of shallow trench isolation (STI), and stressed
nitride cladding layers can be formed over the gate
stack with compressive properties for pMOS and ten-
sile effects for nMOS (locally adjusted by nitride
deposition conditions and implants). Highly doped
junctions contain additional strains arising from the
lattice mismatch of dopant and Si atoms, leading to
modification of carrier mobility within the junction,
among other effects.
For nMOS transistors, intentional stacking fault
defects formed in the S/D contact and extension
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

regions can be used to provide tensile strain in the

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channel. The process involves forming an amorphous

layer, with a Ge implant, in the region of the S/D
contact junction (Fig. 18). During the anneal pro-
cess, an angled stacking fault defect is formed at
the intersection of the lateral and vertical regrowth
fronts, providing a source for tensile strain on the
nMOS channel region [64, 65]. The doped S/D con-
tact is placed so that the stacking fault is entirely
contained within the heavily doped junction and does
not result in a leakage current path through the junc-
Fig. 16. Hole (top) and electron (bottom) mobilities in (110) tion. Additional tensile strain can be obtained by
and (110) Si directions as a function of uniaxial stress [63]. repeating this process with increasingly thick spacer
linings [66].
In the decade since the initial use of strain
sources in CMOS, an extensive suite of stress enhanc-
ing processes have been developed (Fig. 17). The
earliest implementation of pMOS strain was the use
of Six Ge1−x selective epi to form compressive stress
sources in S/D contact regions. 90 nm pMOS used

Fig. 17. Sketch of the main stressor sources in planar pMOS Fig. 18. Sketch of tensile strain effect in nMOS transistors of
(left) and nMOS (right) CMOS transistors. The principal dop- stacking fault formation along the intersection of the re-growth
ing elements in the SD and well regions are shown in paren- regrowth fronts of a deep amorphous layer formed by Ge
thesis. The stress directions are shown as red arrows. implantation.
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

24 L. A. Larson, J. M. Williams & M. I. Current

Higher levels of tensile strain can be obtained by fraction of C are present, resulting in strong tensile
forming C-rich regions in the S/D contact and exten- strain effects, as seen in the XRD spectra. When
sion junctions. Optimal strain is provided by an ≈2% a heavier molecular ion, C14 H+ 14 , is used, a thicker
population of substitutional C embedded within a amorphous layer is formed containing a larger frac-
Phosphorus-doped nMOS S/D. Efforts to adapt the tion of the implanted C, resulting in higher strain
SiGe selective epi deposition process used in pMOS after millisecond anneal.
transistors are limited by the slow and difficult epi
process needed to grow Si:C epi with high substitu- 10.4. Photoresist “freezing” for
tional concentrations of C. A direct implant process lithography
uses a Ge amorphization implant coupled with a C+ Ion implantation has long been used to pre-condition
ion implant into the MOS S/D contact region fol- photoresist (PR) patterns for various processes, such
lowed by annealing [67]. as adding a deep cross-linked and C-rich skin to PR
A more efficient process uses molecular ions, such for enhanced durability during exposure to reactive
as C7 H+7 , to simultaneously add the required C con- ion etch plasmas and to reduce the amount of PR
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

centration profile and directly form a deep, dense outgassing for sensitive dopant implants in order to
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amorphous layer, without the need for the separate avoid dose errors.
Ge implant [68]. As ions are stopped in organic PR masks, many
A comparison of damage layers created by local bonds are broken by the ion and secondary
6.6 keV C+ and 49.5 keV C7 H+ 7 ions (Fig. 19) shows recoil atom impacts. This forms a C-rich, heav-
+
that atomic C ions do not form a continuous amor- ily cross-linked “crust,” is formed with a thickness
phous layer [69]. After anneal, only a small fraction roughly equal to the full extent of the implanted ion
of the implanted C is substitutional and the result is profile [70, 71]. As the C-rich crust is formed, the
a low level of strain. Molecular ions form a thick and PR line shrinks in both the vertical and lateral direc-
dense amorphous layer containing a large fraction of tions. This effect as a process issue will be discussed
the implanted C. After anneal, ≈2% substitutional later in this article.

Fig. 19. TEM images (top) of atomic C+ (left) and molecular C7 H+ 7 (right) ion implants in Si, forming a mixed damage-
amorphous region with C+ and a thick, uniform amorphous layers with C+ 7 . After laser annealing, XRD (bottom) shows high
strain for C7 implanted layers and a higher level of strain following the use of a larger molecular ions, C14 H+
14 [69].
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

Ion Implantation for Semiconductor Doping and Materials Modification 25

Fig. 20. Sketch of PR lines for a dual-exposure process

utilizing ion implant line shrinks. (a) (b)
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With the extended use of subwavelength opti-

cal patterning, ion implant conditioning and the
resulting PR line shrinks have become a routine pro-
cess factor. With the elaboration of litho pattern-
ing to include dual and quad exposures, the effects
of ion implant conditioning have been extended
to include enhancement of the adhesion of multi-
ple litho patterns of PR to the underlying wafer
coatings and reduction of line edge and line width
Fig. 21. PR lines implanted with 2 keV (left (a)) and 5 keV
roughness [72].
(right (b)) Ar+ ions and shrinkage of PR line width, CD, and
PR line shrinkage with ion implantation is illus- reduction of line width roughness, LWR, with 2 and 8 keV Ar+
trated in Fig. 20 for a dual-exposure process. The ion implants into PR [74].
usual ion for PR conditioning is Ar+ , mainly for
its ease of use and relative lack of process com-
11. Photovoltaics Doping
plications. A challenge for dual-exposure litho pro-
cess is that the first level PR layer needs to stay in Makers of photovoltaic cells have historically avoided
place throughout the spin coat, exposure, develop the more complex and expensive semiconductor
and curing of the second layer. If the first level manufacturing techniques as the solar industry has
PR adhesion to the wafer is not sufficient, the sol- been driven mainly by cost. The surface junctions in
vents in the develop cycle of the second layer can solar devices are optimized by balancing their depth
delaminate the PR lines. Here again, the details of and that of the intrinsically doped silicon to the pen-
the implant conditions can vary the PR adhesion etration depth of the light. This characteristic depth
strength [72]. is a few microns, so the surface junction optimizes at
As the C-rich crust forms on the surface of the a depth which is large in comparison with the shallow
PR line, the dimensional integrity of the printed line junctions used in CMOS devices.
increases as the surface “stiffens” and solvent absorp- Similarly, the doping level is optimized high
tion decreases. These effects improve both the line enough to give good resistivity and field penetra-
edge and line width roughness of fine lines, especially tion, but at the cost of a reduction in the lifetime
if the implant included exposures with a high beam of the carriers being collected in the front junc-
tilt angle so that the sides as well as the tops of tion. Standard production thus favors the use of
the PR line are encrusted [73]. The effects of both polycrystalline silicon and deposited doped layers.
adhesion and line roughness improvements with ion However, advanced development favors implanted
implantation are shown in Fig. 21. doped layers where control in placement and doping
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

26 L. A. Larson, J. M. Williams & M. I. Current

level is desired for higher photoconversion effi- Implantation may be enabling for more novel
ciency. The main advantage of implant doping is technologies. The surface morphology is an area
that the doping levels in the front surface junc- where increased absorption of incoming photons can
tion and the contact regions under the metal grid be produced by appropriate scale surface roughening.
lines can be separately and accurately set to pro- Tesfamichael, Will, and Bell have implemented this
vide optimal PV efficiency. In addition, by using in titania films used in dye-sensitized solar cells [80].
a shadow mask during the implant, both the front Doping of more complex PV systems is a topic of
side junction and the extra doping desired for good greater interest. Metal plasma ion implantation of
contact resistance with metal grid lines can be Ru ions has been used to improve conversion effi-
implanted in a single step, without the need for on- ciency of dye-sensitized solar cells [81]. Phosphorus
cell patterning, a significant process time and cost implantation of C60 for PV applications has been
reduction [6]. investigated [82]. The effects of Cl ion implantation
Advanced PV cell designs, with p- and n-type on the properties of CuInSe2 epitaxial thin films have
junctions on the backside of the PV cell and a fully been reported [83]. Polycrystalline CdTe layers were
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

exposed (no metal line) frontside, require the dop- implanted with Phosphorus in order to obtain an
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ing of densely patterned interdigitated junctions of enhanced p-type doping close to the back contact of
opposite doping types on the cell backside, another CdTe solar cells [84].
situation where doped junctions can be efficiently As standard implantation tools are considered
formed by implantation techniques. This is discussed expensive and the layers needed are in an ineffi-
in detail in a theory and simulation paper by Aleman cient part of their process space, plasma implant and
et al. [75]. This paper discusses interdigitated back ion shower tools and techniques have been investi-
contacted cells (IBC) as an option for the achieve- gated as a more appropriate technology. Torregrossa
ment of high-efficiency on silicon material. Imple- et al. used PIII to implant BF3 to form boron junc-
mentation of an electrical field on the front side, also tions and illustrate the use of Plasma Immersion Ion
called the Front Surface Field (FSF), is included in Implantation [85]. Moon et al. investigated amor-
this analysis and is considered beneficial. The back phous silicon p-i-n solar cells using the ion shower
surface field was modeled and experimentally tested doping technique [86].
resulting in an analysis of recombination parameters
by Bordin et al. [76].
12. Semiconductor Process Issues
Doping can be used to modify the solar cell mate-
rials to improve the solar efficiency of the mate- Ion implantation tools, which continue to be the most
rials. Impurity traps (IPV effect) were tested by complex combination of technologies operating in an
both simulation and experiment for boron in sili- IC fabrication line, also need to be the cleanest and
con by Kasai and Matsumura of KAIST [77]. They most controlled in order to function as expected and
assert that impurity-traps could possibly act as step- needed. For example, the balance of doping levels
ping stones in two-step excitation of electrons from and the precise location of junction location in both
the valence band to the conduction band, and thus, vertical and lateral dimensions required for high per-
sunlight of longer wavelength than that equivalent formance CMOS transistors translates into a need
to the band gap could be utilized to improve cell for ion dose control often to better than 1% over a
efficiency. dose range scanning six orders of magnitude. Also
Hydrogen implantation to form shallow donor the energy and angle of incidence of the ion beam
levels has been tested to make deep n–p junctions is specified to within a few percent (for energy) and
in p-type silicon by hydrogen ion implantation [78]. fractions of a degree (for angle of incidence). The
To use less silicon (a cost improvement), H-cut meth- angular control requires not only a tight control on
ods have been used to make thin silicon layers at an mechanical tolerances for wafer positioning but also
encouraging efficiency level — Microsystems enabled the need to minimize beam divergence effects arising
photovoltaics: 14.9% efficient 14 micron thick crys- from electrostatic repulsion of the ions in the beam.
talline silicon solar cell [79]. (This is also discussed Methods to reduce the effects of beam divergence
in the H-cut section). include the introduction of dense local plasmas at
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

Ion Implantation for Semiconductor Doping and Materials Modification 27

critical points in the beam path to the wafer and under-doped and the junction depth will in most
the use of high-mass molecular ions for low energy cases be locally shallower, leading to increased risk of
beams [87]. junction breakdown events and changes to transistor
Once the ion beam and wafers are arranged so functional properties. Even quite small particles and
that the desired ion type, with the correct energy, absorbed thin films result in junction contamination
incident angle and dose is delivered across the from recoil implantation driven by the passing of the
wafer with sufficient uniformity, a significant num- beam ions through these small particles and films.
ber of additional process issues must be controlled Since particles and absorbed films are largely made
by proper system design and operational procedures. up of sputtered and vaporized materials from beam-
line apertures, beam stops and wafer holding fix-
12.1. Particles tures as well as outgassed and sputtered debris from
previously implanted wafers, the recoil implanted
Since the ion energies used for implantation are usu-
atoms can be a complex mix of dopants, metals,
ally quite modest, a fraction to a few tens of keV,
graphitic compounds and hydrocarbons. In addition,
particles and thin films on the wafer can result in
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

any particles which are not removed by the post-

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unwanted blocking of the incoming ions. In addition,

implant resist stripping cleans and remain on the
quite small particles that do not completely block
wafer during the subsequent anneal cycles are dan-
the ion flux can result in distortions of the junction
gerous sources of diffused contaminants and present
edge location and small particles and thin films that
further problems for the metal contact formation
are penetrated by the ion beam contribute surface
step.
contamination by recoil implantation of atoms from
Particles that are trapped in the positive beam
the particles and films. A schematic of these effects
potential of the ion beam and are transported to
is shown in Fig. 22.
the wafer can cause an additional problem through
The larger particle on the left in Fig. 22 results
kinetic impact with rapidly moving wafers being
in a locally undoped junction that will provide a
scanned in front of the beam. For wafers mounted
direct short to the substrate when a metal contact
on spinning wheels and moving at scan velocities of
is formed on the implanted region. For shallow junc-
up to 90 m/s, the impact of a relatively slow moving
tions, aimed to be 10 nm and less in depth, the pres-
beam-transported particle with thin gate structures
ence of small particles and absorbed thin films and
in devices in the rapidly moving wafers is sufficient to
native oxides as thin as a few nanometers can block
shatter stacks of nearby poly-silicon gates for CMOS
a large fraction of the incoming low energy ion beam.
scales of 0.25 µm and less [88]. This problem has
The mid-sized particle, small enough to be pen-
led to the nearly complete abandonment of spinning
etrated by the ion beam, will still cause prob-
wheel scanning designs for advanced CMOS man-
lems because the region under the particle will be
ufacturing and the use of much slower mechanical
scanning of single wafers.

12.2. Charging
Since ion implantation operates with charged ions,
the balance of charge flows between the ion beam
and the wafer must be carefully controlled to min-
imize the net flow of charge through fragile device
structures, buildup of dangerous local potentials and
distortions of ion beam characteristics. In early ion
implantation systems charge balance on the wafer
was attempted, with varying degrees of success, by
Fig. 22. Schematic of particle effects for a particle larger than
direct electron beams aimed at the intersection of the
the ion range (left), a particle that blocks a portion of the ion
flux (middle) and a combination of a small particle and a thin ion beam and wafer, by mixes of primary and sec-
film (right). ondary electrons emitted by an electron-bombarded
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28 L. A. Larson, J. M. Williams & M. I. Current

metal target placed near the implanted wafer and an

increasing variety of plasma flows designed to mix
with incoming ion beam plasma and flow to the wafer
surface.
The modern understanding of beam-wafer inter-
actions includes control of the stability of the ion
beam plasma, consisting of a central column of
rapidly moving positive ions and an approximately
equal charge of slow moving electrons trapped in
the ion potential. Maintaining space-charged neutral
conditions throughout most of the ion beam path
from the ion source to the wafer is usually essential to
avoid significant loss in beam transmission through
beam size expansion driven by Coulomb repulsion of
Fig. 23. Charge flows with an ion beam and local plasma in
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

the energetic ions, particularly for low-energy, high- contact with an implanted wafer.
by HENRICH-HEINE-UNIVERSITAET on 10/06/13. For personal use only.

current beams.
In the region near the implanted wafer surface,
beam and local plasma at a wafer surface is shown
additional methods are used to ensure a quasi-
in Fig. 23.
neutral wafer surface and to minimize the net current
The net current flow in Fig. 23 is a sum of the
flow to the wafer. Early efforts to maintain a neutral
incoming positive ion beam and accompanying beam
wafer surface during ion implantation used beams
plasma electrons and the ion and electrons from the
of 300 eV electrons directed toward the intersection
local plasma, mixed with the secondary electrons and
of the ion beam with the wafer surface. However, if
ions generated on the wafer surface by the energetic
the beam alignments were not accurate and the var-
ion beam impact.
ious ion and electron currents not well controlled,
The actual current components at the wafer sur-
the high-energy electron beam could cause as much
face are somewhat more complex than those shown
disruption to device structures as the un-neutralized
in Fig. 23. For example, gas atoms in the ion beam
ion beam. An improved scheme directed the ener-
path are ionized by collisions with the energetic ions,
getic electron beam towards a grounded metallic sur-
increasing the local plasma density and generating a
face placed near the wafer location, expecting that
population of “slow ions” that are repelled by the
low-energy secondary electrons would be a gentler
beam potential to the sides of the ion beam path
means of neutralizing the ion beam on the wafer
(Fig. 24). Measurements of the energy of the slow
surface. However this method also failed in practice
ions emerging from the ion beam region can be used
since organic material outgassed from photoresist on
to probe the beam potential characteristics of various
wafers quickly coated the metallic target surface. As
ion beams [89].
a result, no secondary electrons were emitted and the
A reasonably accurate and compact description
energetic primary electron beam was reflected by the
of the net current flow on the wafer surface can
charged organic film back towards the wafer surface,
be developed for the case where the local plasma
causing similar damage as the older direct electron
is space-charge neutral, i.e. the total electron den-
beam systems.
sity is balanced by the beam and plasma ions, ne =
A better way to control ion beam charging was
nib + nip . For a thermal equilibrium local plasma,
to add more ions and electrons to the wafer vicinity
the electron population can be described by ne =
in the form of neutral, low-energy plasmas. When
neo e([Vsurf −Φp ]/Te ) , where Vsurf is the wafer surface
the plasma ion density, and corresponding electron
potential, Φp is the beam ion potential and Te is the
population, is much higher than the incoming ion
temperature of the thermalized plasma electrons.
beam density, the charge and current flows on the
The net ion current, where γ is the secondary
wafer surface is dominated by the characteristics
charge generation coefficient, is:
of the added plasma, not the implanted ion beam.
A sketch of the basic charge flows with an ion Jnet = jib (1 + γ) + jip − je . (2)
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

Ion Implantation for Semiconductor Doping and Materials Modification 29

Fig. 25. Positive and negative current flows for an Ar+ ion
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

beam with a current density of 2 mA/cm2 and a beam poten-

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tial of 15 V.

Fig. 24. Sketch of the charges generated near and at the

wafer surface by the energetic (“fast”) ion beam, including plasma also greatly increases the net negative current
ionization of Ar gas atoms in the beam path, secondary elec- flow from the local plasma, primarily from outside of
trons from conductive regions on the wafer and outgassing of
the ion beam area. This can lead to additional IC
charged ions, such as H− , from the photoresist mask areas.
Also shown are Ar+ ions and electrons from the local plasma device yield problems in sensitive device thin films
source. and structures.
In Fig. 25, the local plasma density is 10 times
For a local plasma made up of ions of mass, Ap , the higher than the ion beam density with an electron
net current density is: temperature of 4 eV. The average wafer surface sec-
Jnet = jib (1 + γ) + jip ∗ [1 − (1 + nib /nip ) ondary coefficient is 10. The positive current flows
show the effects of using various ions for the local
∗ 34.2 ∗ A1/2
p ∗e
([Vsurf −Φp ]/Te )]
. (3) plasma and the negative current flows are calculated
This compact description of the net current matches for an Ar plasma with electron temperatures higher
well with detailed measurements of surface potentials than 4 eV.
and positive and negative current flows obtained by
on-wafer sensing structures connected to EEPROM-
12.3. Photoresists
like data storage transistors [90, 91]. Two aspects
of the local plasma characteristics are illustrated in The ability of ion implantation to use the patterning
Fig. 25, the effect of ion mass and electron tempera- photoresist as a blocking mask at temperature close
ture in the local plasma. For an Ar+ ion beam with a to room temperature has long been a major factor
current density of 2 mA/cm2 and a plasma electron in the economic superiority of implant to thermal-
temperature of 4 eV, the net positive current flow driven CVD methods for doping. However the dam-
into the wafer (+V ) as well as the maximum surface age and degradation of organic photoresist films as
potential decreases substantially when a heavier ion the energetic ions are stopped in the mask layer leads
is used in the local plasma. This accounts for the to a number of process effects (Fig. 26).
choice of Xe as the local charge control plasma ion The principal effect is that, as ions are stopped
in many commercial ion implanters. The net neg- in the resist, bonds in the organic material are broken
ative current flows (−V ) are mainly controlled by by ion-target collisions and large amounts of volatile
the plasma electron temperature. If the local plasma materials, mostly H2 , H, N2 and O2 , are released
source is biased relative to the wafer and ion beam, during the initial stages of the implant. The high
the current flow from the source into the region of flux of outgassed atoms raises the pressure in the
the beam and wafer can be greatly increased, how- region of the wafer and leads to dose and energy
ever the higher electron temperature of the biased errors in certain beamline and dosimetry designs
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

30 L. A. Larson, J. M. Williams & M. I. Current

Fig. 27. Dopant atom ranges and C-rich crust thickness

for As and BF2 ions implanted into PMMA photoresist for
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

doses of >5 × 1015 ions/cm2 . The crust thickness data is

by HENRICH-HEINE-UNIVERSITAET on 10/06/13. For personal use only.

from [70].

Fig. 26. Sketch of process effects occurring in organic pho-

toresists during ion implantation, including outgassing of high-dose implants, the C-rich crust thickness closely
volatile atoms released from the implanted mask layer, for- follows the sum of the mean ion range plus three
mation of a top-surface C-rich crust layer and formation of
gas-filled blisters if the resist film is heated too much by a times the range straggling.
high-power ion beam with insufficient wafer cooling.

13. Materials Modification Applications

through neutralization and other charge exchanges and Process Effects
during collisions with the incoming ion beam. Ion implantation has been used for its capability
As the dose accumulates in the resist film, the to beneficially modify the chemical and mechani-
implanted layer becomes depleted of many volatile cal surface properties of materials since the early
components of the organic material and becomes a 1970s. This is well described by Nastasi, Mayer and
dense, C-rich “crust” [71]. If the ion beam heating of Hiroven [18]. An early paper describing the technique
the wafer raises the temperature in the resist film of plasma immersion ion implantation by Conrad
higher than the boiling point of some of the un- et al. also has a discussion of the many applications
crosslinked short-chain resist components, internal of these techniques [19]. Similarly, Ueda, Berni and
gas-filled blisters are formed. If the heating contin- Castro published “Application of Plasma Immer-
ues, these blisters grow and can burst through the sion Ion Implantation for improved performance of
upper crust layer, causing breakdown of the mask tools and industrial components” which specifically
integrity. To avoid blister formation, ion implanters focuses on materials modification for surface and
are designed with sufficient heat sinking and coolant mechanical property improvement [92].
flows under the wafer such that the wafer tempera- Advantages of ion implantation in comparison
ture is kept below ≈120◦C for high-current and high- to other surface treatments include the following: the
energy implants. solid solubility limit can be exceeded, that the prepa-
At the conclusion of the implant cycle, the resist ration is independent of diffusion, and that the depth
layer is removed to clear the way for subsequent pro- distribution is controllable. At the same time there is
cessing and patterning steps. The C-rich crust layer no sacrifice of the bulk material properties, no signif-
usually requires plasma exposure in an “asher,” fol- icant dimensional changes and adhesion is expected
lowed by a wet-chemical clean to remove the residual as there is no clear interface.
lower resist layers [70]. The thickness of the C-rich A limitation of beam-line implantation is that it
crust, which determines the power settings and pro- is a line-of-sight process. Samples having complicated
cess time in the plasma asher tool, depends on the re-entrant surfaces cannot be treated effectively.
range of the implant ions in the resist (Fig. 27). For However, one of the benefits of PIII is that the ions
December 13, 2011 11:50 WSPC/253-RAST : SPI-J100 S1793626811000616

Ion Implantation for Semiconductor Doping and Materials Modification 31

follow the field lines, which trace the surface geom- manner [98]. Most PIII tools and applications use
etry of the sample. This provides a much more even relatively low energies; however, Rossi et al. [99]
treatment of the material. A paper that describes have developed a high energy immersion approach
the theoretical background to this statement is “PIII using short repetitive pulses for aerospace materi-
Implantation Inside a Small Bore” [93]. als. An associated technology is IBAD (ion beam
Tools for materials modification are described assisted deposition). Nastasi et al. [18] and Kaufman
in Chapter 15 of the book by Nastasi, Mayer and and Robinson [100] discussed source technology and
Hiroven [18]. Directed ion beam implanters have fol- system for this tool family.
lowed closely the same evolution and features as Table 2 summarizes the results of an active area
described earlier for tools developed for semiconduc- of the literature, where researchers have published a
tor technology. Ion sources capable of larger cur- large number of results on the effect of several ions on
rents have been developed for their use in these metallurgical systems. Two areas in particular have
applications. These include CHORDIS (cold and hot found multiple applications. The first three rows of
reflex discharge ion source) [94] and MEVVA (metal Table 2 show variants of Ti-Al alloys. These materi-
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

vapor vacuum arc) [95, 96]. PIII tools were devel- als are favored for medical implants, such as knee
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oped in the 1990s [97] and found quick application joints and hip replacement. Reviewing the effects
due to the field-line implantation attribute and the of the treatments show that nitrogen and several
promise of high doses in a simple, fast, cost-effective other elements can increase the hardness, decrease

Table 2. A summary of the literature materials treatment on metal, ion and a short comment on the results
are listed.

Substrate Ion Improvements observed Reference ID

Titanium Alloys
Ti-6Al–4V N Hardness, coefficient of 101, 102, 103, 104, 99
friction, wear and
adhesion
Ti-Al-Si-N C Frictional coefficient; 105
wear
Ti-Al-Zr Ta, N Anodic current density; 106
corrosion potentials
Chromium Alloys
CrCoMo, CrNiMo N, H Hardness improvement 92
Aluminum Alloys
A17475, A15052 N Corrosion reduction, 99
hardness improvement
Steels
5160, SKD11, SKS3, M2, N, H, Cr, Ar, Si Hardness, wear rate, 19, 107, 102, 103, 92, 108,
SI, E-52 corrosion potential 109, 110, 111, 112
H13, 304, 420, 430, 304 N, Cr, N and Cr 113, 114, 115, 116
Polyethylene
Polyethylene N Hardness; elastic 117, 99, 92
(UHMWPE) modulus; coefficient
of wear
Nanoparticles
Silicon with silicon Ni, Fe, Si Created nanoparticles 118, 119, 120
dioxide layer with controllable size
and density
Silica microbeads, Ar and C ions, + and − Tested threshold charging 121
soda-lime glass beads voltage and particle
Photo
Silicon, H-implanted Si H+
2 , Acetylene and Ar Photoluminescence, 122
roughness, isolation
Rutile TiO2 Cu and Ag Photocatalytic efficiency 123
PbTe Tin Thermopower and 124
electrical conductivity
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32 L. A. Larson, J. M. Williams & M. I. Current

the wear coefficient and reduce the potential for cor- the H range in Si, increasing with energy. If the
rosion. Similarly, much work has been done on steels; H-implanted Si wafer is bonded to an oxidized “han-
the majority of the references address this topic. For dle” wafer before thermal processing, the chemical
multiple alloys, results indicate that nitrogen implan- etching of Si by the accumulated H atoms results in
tation along with several other elements can increase the formation of thin “platelet” voids aligned along
the hardness and decrease the wear rate. Notably, the wafer surface plane in Si(100) at the depth of
several specific applications are quoted as the target the H implant peak. If this bonded pair of wafers
of this research with a beneficial effect. is heated to ≈450◦C or subjected to appropriate
Increasing the hardness of metal alloys is not mechanical force, a planar “cleave plane” will form
the only application of these surface treatments, but along the platelets in the H-rich region and the wafers
may be the largest. Several publications detailed can be separated. After removal of the H-rich dam-
work on plastics, where the irradiation created sur- aged layer, the handle wafer, oxide, and transferred
face layers that increased their wear resistance. Kap- layer become an SOI wafer ready for CMOS and pho-
ton was found to create a metal oxide layer that tonic device processing.
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

increases its lifetime in the space atmosphere of If a higher energy proton beam is used to implant
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atomic oxygen [125]. Similarly, Shi, Li and Dong H at a deep enough location, the overlying Si is stiff
of Birmingham found that PIII of nitrogen would enough to drive the formation of planar platelets
improve the hardness, elastic modulus, and coef- rather than surface blisters, without the need for the
ficient of wear reduction of ultra-high molecular bonded handle wafer. Free-standing Si membranes as
weight polyethylene [117]. Tin implantation has been thin as 20 µm, using an ≈1.2 MeV proton beam, have
studied to improve the activity of PbTe as a thermo- been reported [129].
electric material [124]. Several materials segregate to Monte Carlo calculations [130] of H and Si recoil
form particles when present in sufficient amounts. profiles for high-dose, low and high-energy proton
It has been found that these segregations naturally profiles are shown in Fig. 29. The residual damage
form into nanoparticles. Silicon particles have been associated with the Si recoils during the ion stopping
formed in SiO2 [120] and nanotubes have been grown is important for H implants because H diffuses eas-
from both nickel [118] and iron [119] implantations. ily in Si and migrates away from the initial stopped
In the area of catalysis, metal ions have been profile unless it is trapped by local Si defects. The
used to improve the catalytic properties of rutile
TiO2 [123] and a machine process paper has
described how the implantation may scatter catalytic
particles [121]. The use of PIII techniques for for-
mation of bioactive materials and devices has been
reviewed by Chu [126].

13.1. H-cut wafer splitting

Hydrogen implantation at high enough doses (≈5 ×
1016 H/cm2 ) to induce planar lateral splitting in
crystalline Si, Ge and GaAs, etc., under proper con-
ditions has been used for the last decade to manufac-
ture silicon-on-insulator (SOI) wafers as well as for
lamination of diverse types of photonic and photo-
voltaic materials and structures [127–129].
The effects of high-dose H implant into Si Fig. 28. Schematic for high dose (≈5×1016 H/cm2 ) implants
are sketched in Fig. 28. For relatively shallow H into Si after thermal treatment for (left) a shallow H profile
implants, a few hundred nm, into an exposed Si with an open Si wafer surface, resulting in surface blisters,
(middle) a shallow H profile with an oxide covered Si handle
wafer, H2 -filled surface blisters form during the
wafer bonded to the implanted wafer before thermal treat-
implant and during subsequent thermal process- ment, resulting in Si layer splitting, and (right) a deep H pro-
ing. The thickness of the blister skin is equal to file into a Si wafer, also resulting in Si layer splitting.
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Ion Implantation for Semiconductor Doping and Materials Modification 33

a range from 1 to 4 MeV for fabrication of thin Si

membranes for use in high efficiency PV cell man-
ufacturing [135]. Multichannel linac designs are also
in use to provide multi-mA-level proton currents for
Si membrane separation [136]. In addition to provid-
ing low weight solar modules, H-cut methods also
are highly efficient in their utilization of Si material
with minimal waste of Si in the cutting and removal
of the heavily damaged cleave plane region. This is
in strong contrast to wire-saw methods which con-
sume 30–50% of the Si block in the cutting and saw
damage etching process for thin Si sections.
H-cut techniques are envisioned to play a cen-
Fig. 29. Monte Carlo calculations of initial H and Si pri- tral role in formation of 3D ICs [137]. In the meth-
Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com

mary recoil distributions for high dose 40 keV and 2 MeV ods proposed by MonolithIC 3D, a completed CMOS
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protons [130].
circuit, stopping at the S/D contact formation, is
implanted with H at a depth sufficient to separate
resulting H distribution follows the damage profile, the device level from the fabrication wafer. Then
peaking near the H range but slightly shallower than a temporary bond is made to a transparent handle
the initial H depth profile. For a 40 keV H profile, wafer and the CMOS device layer is separated from
typical of SOI wafer and photonic materials fabrica- the wafer, aligned with a fully interconnected sec-
tion, the H depth and transferred layer thickness is ond CMOS device layer and bonded to it. The 3D
≈0.4 µm. For a 2 MeV proton beam, used for split- structure is completed with the fabrication of shal-
ting of free-standing Si membranes for low mass PV low vias and interconnects linking the two device
cells, the range and thickness is ≈50 µm. layers. Many similar 3D integration methods have
H-cut splitting can be accomplished in a num- been explored, including bonding of CMOS device
ber of ways, such as thermal splitting at ≈450◦C layers formed on SOI wafers thinned by removal of
for ≈30 min [127], mechanical separation at room the handle wafer material by grind and etching meth-
temperature [131], by exposure to microwave radi- ods using the buried oxide layer as an etch stop [138].
ation for short periods of time [132] and thermal It is estimated that proton acceleration to less than
stress from high power laser scans [133]. The heav- 50 keV would be sufficient to implement the process
ily damaged and H-rich layer that surrounds the shown in Fig. 30, with a cleave plane depth of less
cleave plane can be removed by chemical mechani- than 500 nm and the use of a temporary bonded car-
cal polishing (CMP) [127], exposure to H2 at tem- rier wafer.
peratures above ≈1100◦C [134], or by specialized
etching procedures, leaving relatively undamaged 13.2. Phase stabilization implants
crystalline material in the transferred layer. Measure- for NiSi contacts
ments of carrier recombination rates in free-standing The effect of source/drain junction contact resistance
Si membranes, an important consideration for PV on the transistor total series resistance increases as
cell materials, indicate that a high quality Si mate- the contact pitch and contact area decrease with
rial survives the passage of high dose MeV proton more strongly scaled devices. Ni silicide has been
beams [129]. widely adopted for a junction contact metal, with
The accelerators used for implantation of H for very good results (low Schottky barrier height (SBH)
creation of free-standing Si membranes of several and low contact resistivity for contact to p-type junc-
to 150 µm thick require proton beams of sufficient tions). However the NiSi form of Ni silicide has a high
beam current to be economically viable for doses of SBH and high contact resistivity on n-type junctions
≈5 × 1016 H/cm2 per membrane at energies up to due to the contribution of the Si band gap.
4 MeV. Single-ended 4MV Van de Graaff-type accel- Implants of rare-earth ions (Dy, Pr, La) into
erators provide a useful high-current proton flux over the surface regions of n-type contacts prior to Ni
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34 L. A. Larson, J. M. Williams & M. I. Current

Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com
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Fig. 30. Schematic of the use of H-cut techniques to split

away a completed CMOS front end device (top) and laminate
it to a fully metalized 2nd CMOS layer, to be connected by
vias and final metal layers (bottom) [137].

deposition and silicide formation have shown lower

SBH. However the contact resistance to heavily
n-type doped junctions is still limited by the forma-
tion of local and discontinuous NiSi grains (Fig. 31).
The implantation of N at doses of ≈3 × 1015 N/cm2
results in a stable phase of NiSi for anneal temper-
atures of 300◦ C–400◦C with lower SBH values, sim-
ilar to NiSi2 but without the need for high anneal
temperatures (>750◦ C for formation of NiSi2 phases)
and at a lower metal layer resistivity than NiSi2 . The Fig. 31. SEM cross-sections and sketches (top) and sheet
phase-stabilized N-implanted NiSi also has a more resistance distributions for 150 nm thick Ni-silicide layers (bot-
uniform grain distribution, allowing the use of thin- tom) showing the positive effect of N+ 2 ion implantation into
NiSi layers on n-type junctions [1].
ner silicide contact layers, and a much narrower and
lower value distribution of sheet resistance (Fig. 31).
The use of N-implants into NiSi contacts reduces the The enhanced damage rates produced by the
total series resistance in a modern nMOS transistor molecular ions of B18 and C16 also seem to increase
by 22% (Fig. 32). the stability of NiSi films during post-deposition
Additional studies have shown that C doping of anneals (Fig. 33). The C in combination here with B
NiSi films and substrates, combined with dopants, dopants results in shallower junctions after anneal.
also contributes to the phase stability of NiSi con-
tacts. When combined with dopants that diffuse
13.3. Optical constant modification
by interstitial mechanisms, mainly B or P, the C
implants can serve the dual functions of reduc- A well known property of ion implanted materials
ing dopant diffusion (the “cocktail” implant effect) is that the fluence of ions causes damage in the
and allowing the NiSi contact film to withstand material exposed to the beam. This damage often
higher anneal temperatures without agglomerating changes the optical properties of the material. An
into local islands. active application of ion implantation is to exploit
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Ion Implantation for Semiconductor Doping and Materials Modification 35

Rev. Accl. Sci. Tech. 2011.04:11-40. Downloaded from www.worldscientific.com
by HENRICH-HEINE-UNIVERSITAET on 10/06/13. For personal use only.

Fig. 32. Reduction of SBH for NiSi on n-type junctions by

high dose N+ implant (top) and reduction of total series resis-
tance in an nMOS transistor (bottom) [139].
Fig. 33. NiSi sheet resistance for 15 nm films with additional
B18 and C16 molecular ion implants (top) and B diffusion
profiles (bottom) [140].
this effect by modifying the optical properties of opti-
cal materials using implantation. In particular, ion
implantation is a powerful and promising technique
to use to fabricate optical waveguides [141]. Accu- focuses on changes in n and associated optical con-
rate control of both the depth and lateral concen- stants, there are several other effects that have been
trations of the dopant at low temperature make the explored.
implantation process an extremely attractive tech- Implantation has been used to modify lumines-
nique for this purpose. In the waveguides formed by cent properties of a laser crystal [154] and of sili-
light-ion implantation, such as He or H, ion doses con [122]. The silicon work is of particular interest
of the order of 1016 ions/cm2 or higher are needed, as this is a link coupling optical materials for possi-
and an optical barrier is built up at the end of track ble use with silicon microelectronics. Another effect
due to the damage induced by nuclear energy loss revealed is the formation of copper nano-particles
[142, 143]. in polymer substrates [157] and in ZnO [158]. Zinc
This damage in the optical material primar- oxide was chosen, because of its utility for photonic
ily causes changes in the index of refraction, n. applications, as a semiconductor with high radiation
Several other physical and optical properties may resistance [158]. In the polymers, the copper nano-
also be affected. Table 3 surveys the literature on particles are the agent that affects the optical prop-
this area and although the majority of the work erties of the material [157].
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36 L. A. Larson, J. M. Williams & M. I. Current

Table 3. Survey of the literature regarding implantation on optical material systems.

Substrate Ion Modification Reference

Chalcogenide glasses Ar, N Waveguides, step-like n distribution 144

α-SiO2 F, Cl Waveguides, step-like n distribution 145
LiNbO3 O n enhancement in the waveguide layer 118
PMMA, PVC, PI, PC Li, N Waveguides fabricated with n 146
PMMA, Polystyrene H, H2 , N, B up to 30% change in index of refraction (n) 147
PMMA Protons refractive index depth profile 148
Polycarbonate O n, loss factor, hardness 149
Polycarbonate C optical, chemical and thermal properties 150
polycarbonate Cu, Ni structural degredation characterized 151
Sapphire, a-Al2 O3 Au optical absorption shifts 152
Cd2 SnO4 Ag optical and electrical properties 153
Nd:MgO:LiNbO3 C fluorescence modifications 154
polycarbonate O structural degredation characterized 155
Sapphire, a-Al2 O3 Co structural and optical changes 156
Si H, by PIII Photoluminescence 122
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HDPE, PS, PO Cu Cu nanoparticle formation 157

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ZnO Cu Cu nanoparticle formation 158

14. Summary [2] S. B. Felch et al., J. Vac. Sci. Technol. B 26, 281
(2008).
Ion implantation in its many forms continues to pro- [3] http://download.intel.com/newsroom/kits/22nm/
vide the principal method for delivering dopants and pdfs/22nm-Announcement Presentation.pdf
other ions for the manufacture of IC devices. In [4] Y. Sasaki et al., Conformal doping for finFETs
addition, new applications for doping of PV mate- and precise controllable shallow doping for pla-
rials, materials modification of metals, plastics, and nar FET manufacturing by a novel B2 H6 /helium
self-regulatory plasma doping process, in Proc.
other forms, and bioactive surfaces and devices, con- Int. Conf. Electron Devices Meeting IEDM (2008),
tinue to develop. The diversity of implant machine pp. 917–920.
types continues to grow, in many cases still nurtured [5] J. Mody et al., J. Vac. Sci. Technol. B 28, C1H5–
by the deep roots of accelerator physics developed C1H13 (2010).
through the 1930s to 60s. The high expectations for [6] A. Rohatgi and D. Meier, Photovolt. Int. 10, 87
(2010).
the ion implantation processes for doping accuracy
[7] N. Cheung et al., Ion Implantation Science and
in amount and placement as well as in elemen- Technology, ed. J. F. Ziegler (Ion Implanta-
tal purity mean a wide variety of process control tion Technology Corp., Yorktown, New York,
issues that must be resolved on a daily basis by 1996).
machine builders, engineers, maintenance workers, [8] http://www.axcelis.com
and operators throughout the world. A sample of [9] http://www.nissin-ion.co.jp
[10] http://www.senova.co.jp/english/index.html
these implantation tools, applications and issues [11] http://www.tel.com/eng/about/index.htm
have been reviewed in this paper. [12] http://www.ulvac.com
[13] http://www.vsea.com
Acknowledgments [14] http://www.aibt-inc.com
[15] http://www.appliedmaterials.com
The authors would like to thank Dr. Harold Stern [16] http://www.ion-beam-services.com
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Lawrence A. Larson is a Senior Lecturer and Michael I. Current’s Research interests range over
by HENRICH-HEINE-UNIVERSITAET on 10/06/13. For personal use only.

Research Professor in the Ingram School of Engi- three decades of the applications and process controls
neering at Texas State University at San Marcos. of ion beam processing of Si and related materials
At Texas State, he has taught classes on the ITRS for fabrication of advanced IC and photonic devices.
in addition to core engineering classes. Previously, He has worked at Current Scientific, Frontier Semi-
he was Associate Director of the FEP Division of conductor, Silicon Genesis, Applied Materials, Xerox
SEMATECH. This program targeted the develop- Palo Alto Research Center, Trilogy Systems, Signet-
ment of processes and materials needed to manu- ics/Philips, and Kyoto and Cornell Universities. He
facture the most advanced semiconductor devices. earned his Ph.D. in Physics and worked at Rensse-
He established the project and funding for the laer Polytechnic Institute. He has written over 200
SEMATECH/SRC Front End Processes Research papers and book chapters and co-chaired 6 interna-
Center, and worked on programs in installed base tional conferences, was a co-founder of the Silicon
implant, ultrashallow junction development, rapid Valley Implant Users Group, and is an active mem-
thermal processing, implant contamination, and the ber of the MRS and AVS.
conversion of SEMATECH’s fab to 200 mm. Larson
received a B.A. in Physics from Whitman College
and a Ph.D. in Solid-State Physics from Washing-
ton State University. He is the author of over 130
publications.
Justin M. Williams attended the University of
Hawai’i at Manoa for his freshman year, after grad-
uating from James E. Taylor High School in Katy,
Texas. He is currently studying electrical engineering
with a specification toward networks and telecommu-
nications systems at Texas State University at San
Marcos, and expects to graduate in December 2012
summa cum laude.