Chapter 1 Logic 1

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LOGIC DESIGN 1

• The aim of this course is :


– to learn how the student can realize a logic function
with different numbers of inputs and outputs.
– To optimize the function realization
– To realize logic modules and memory ROM
– To ensure right transfer & comparison of data.
– To build up asynchronous and synchronous memory
element.
– To design registers and shift registers.
– To design and realize counters .
– To design and realize a RAM with certain capacity.
Student Assessment Method

1. Midterm : 20 points , 8th week.


2. PRACTICAL 20 points
3. Quizzes, assignments and projects: 20 points.
4. final: 40 points.
Internal organization of computers
DIRECT HANDLING CPU

INPUT
ALU

CPU OUTPUT
ENCODED DIGITAL INF.

*INSTRUCTIONS MEMORY CONTROL


*DATA

Control bus
LOGIC DESIGN 1
CONTENTS
CHAP I. COMBINATIONAL LOGIC CIRCUITS
I.1. Introduction.
I.2. Basic definitions.
I.3. Boolean algebra.
I.4. Logic function presentation & realization.
I.5. States maps (Karnauph maps)
I.6. Minimization of logic functions.
I.7. Realization of logic functions using AND gates ONLY
I.8. Realization of logic functions using NOR gates ONLY.
I.9. Undefined states.
CONTENTS cont.
• CHAP II COMBINATIONAL MODULES AND
SUBSYSTEMS.
• II.1 Half Adder
• II.2 Full Adder
• II.3 Decoder.
• II.4. Encoder.
• II.5 ROM.
• II.6. MUX & DEMUX
• II.7. Parity Checker.
• II.8. Comparator
CONTENTS cont.
• CHAP III SEQUENTIAL CIRCUITS.
• III.1 DEFINITIONS
• III.2 SR flip flop.
• III.3 JK flip flop.
• III.4. D flip flop.
• III.5 T flip flop.
• III.6. conversion from one type to another
• III.7. Asynchronous & Synchronous flip fops.
CONTENTS cont.
CHAP IV REGISTERS & MEMORY ELEMENTS.

• IV.1 Example of 4 bit registers


• IV.2 Shift Registers.
• IV.3. Counters.
• IV.4. RAM.
CHAP I.
COMBINATIONAL LOGIC CIRCUITS
• I.1. INTRODUCTION:
• The aim of this course is :
– to learn how the student can realize a logic function with
different numbers of inputs and outputs.
– To optimize the function realization
– To realize logic modules and memory ROM
– To ensure right transfer & comparison of data.
– To build up asynchronous and synchronous memory element.
– To design registers and shift registers.
– To design and realize counters .
– To design and realize a RAM with certain capacity.
I.2. Basic definitions.
1. Logic Variable if A=0 ; Á=1
if A=1 ; Á=0
the corresponding gate is NOT gate.

A y=A’
2. Logic Product y=A. B

A y=A . B AND gate


B
2 1
A B Y
0 0 0

8421 0 1 0
1 0 0
0011 1 1 1

2519
3. Logic Sum y=A+ B

A y=A + B OR gate
B
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
3Inp AND, OR
STATES A B C AND OR

S0 0 0 0 0 0

S1 0 0 1 0 1

S2 0 1 0 0 1

S3 0 1 1 0 1

S4 1 0 0 0 1

S5 1 0 1 0 1

S6 1 1 0 0 1

S7 1 1 1 1 1
STATES A B C D AND OR
S0 0 0 0 0 0 0
S1 0 0 0 1 0 1
S2 0 0 1 0 0 1
S3 0 0 1 1 0 1
4
S4 0 1 0 0 0 1
INPUTS
AND S5 0 1 0 1 0 1
and S6 0 1 1 0 0 1
OR S7 0 1 1 1 0 1
S8 1 0 0 0 0 1
S9 1 0 0 1 0 1
S10 1 0 1 0 0 1
S11 1 0 1 1 0 1
S12 1 1 0 0 0 1
S13 1 1 0 1 0 1
S14 1 1 1 0 0 1
S15 1 1 1 1 1 1
I.3. Boolean Algebra
1. Repetition: A

A.A=A A+A=A A

2. Association
 A.B =B.A A+B= B+A
3. Distribution:
 A(B+C) =AB +AC A+BC=(A+B)(A+C)
4. Complement
 A. A=0 A+ A=1
STATES A B C AND OR

S0 0 0 0 0 0

S1 0 0 1 0 1

S2 0 1 0 0 1

S3 0 1 1 0 1

S4 1 0 0 0 1

S5 1 0 1 0 1

S6 1 1 0 0 1

S7 1 1 1 1 1
Boolean Algebra (cont.)
5. ONES: A+1=1 ; A.1 =A
6. ZEROS: A+0=A ; A.0 =0
7. From 5&6 0 is Id number of OR
1 is Id number of AND
8. De Morgan theorem
(A+B )’ = A’ B’ ; ( AB)’ =A’+B’ ;
(ABCD)’=A’ + B’+ C’ + D’
(AB+CD)’=(AB)’ (CD)’= (A’+B’) (C’+D’)
I.4.LOGIC FUNCTION
• INPUTS: n ; OUTPUTS: m

• X0 Y0
• X1 Y1

• Xn-1 Ym-1

• Yi=F(X0,X1,………..Xn-1)
States X Y0 Y1 Y2 Y3

Example1 Y=F(X) S0 0 0 1 0 1
S1 1 0 0 1 1

• Y1=X • Y2=X
LSB MSB

Example2 Y=F(X0, X1)


X0 X1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 T13 Y14 Y15

0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

NOR ExOR NAND AND ExNOR OR

Y8=X0.X1; Y14=X0+X1;

Y7= X0.X1 ; Y1=X0+X1;

Y6=X0 X1; Y9= X0 X1


Ex. Realize the logic Function
y=F(X0,X1,X2)=∑(0,2,5,7)
state X0 X1 X2 Y

0 0 0 0 1
Truth Table
1 0 0 1 0

2 0 1 0 1

3 0 1 1 0

4 1 0 0 0

5 1 0 1 1

6 1 1 0 0

7 1 1 1 1
Ex realize the logic Function
y=F(X0,X1,X2)=∑(0,2,5,7)
State X0 X1 X2 Y

0 0 0 0 1 • X0.X1.X2
1 0 0 1 0

2 0 1 0 1
• X0.X1.X2
3 0 1 1 0

4 1 0 0 0

5 1 0 1 1
• X0.X1.X2
6 1 1 0 0

7 1 1 1 1 • X0.X1.X2
y=∑(0,2,5,7)
= X0.X1.X2 + X0.X1.X2+X0.X1.X2 + X0.X1.X2 SOP
0 1 0 1 0 1 0
X0 X1 X2 X0 X1 X2
0 0
y=∏(1,3,4,6)=(X0+X1+X2)(X0+X1+X2)(X0
+
X
+
X
+X1+X2)(X0+X1+X2) 1
+ POS
1
+
X X
2 2
State X0 X1 X2 Y

0 0 0 0 1

1 0 0 1 0 • X0+X1+X2
2 0 1 0 1

3 0 1 1 0
• X0+X1+X2
4 1 0 0 0 • X0+X1+X2
5 1 0 1 1

6 1 1 0 0
• X0+X1+X2
7 1 1 1 1
y=∏(1,3,4,6)
=(X0+X1+X2)(X0+X1+X2)(X0+X1+X2)(X0+X1+X2)
X0 X1 X2 X0 X1 X2

0 1 0 1 0 1 POS
X0’+X1’+X2

X0’+X1+X2

X0+X1’+X2’

X0+X1+X2’
TASKS
• Realize the logic Function
y=F(X0,X1,X2)=∑(2,5,7) Using POS, SOP
which is better?
• Realize the logic Function
y=F(X0,X1,X2)=∑(0,1,2,5,7) Using POS, SOP
which is better?
• Draw a truth table for the possible designs of
the logic Function y=F(X0,X1,X2)
y=∑(2,5,7)
= X0’.X1.X2’+X0.X1’.X2 + X0.X1.X2 SOP
0 1 0 1 0 1 0
X0 X1 X2 X0 X1 X2
I.5 PRESENTATION OF LOGIC FUNCTIONS
USING STATES MAP (KARNAUPH MAP)
STATES X Y
S0 0 1
S1 1 0

S0 S1

1 0
Example1 Y=F(X) =∑(0) X
STATES MAP (cont)
Y= F (A,B)
NO OF STATES=4
TRUTH TABLE STATES MAP
S0 S1
States A B Y
S0 0 0 1 1 0
S1 0 1 0 S2 S3
S2 1 0 1
S3 1 1 1 A 1 1
B
Y=F(A,B,C)=∑(0,1,4,7)
8 STATES
TRUTH TABLE STATES MAP
STATES A B C Y C

S0 0 0 0 1 S0 S1 S3 S2
S1 0 0 1 1
1 1 0 0
S2 0 1 0 0
S3 0 1 1 S4 S5 S7 S6
0
A
S4 1 0 0 1 1 0 1 0
X5 1 0 1 0 B

S6 1 1 0 0
S7 1 1 1 1
Y=F(A,B,C,D)=∑(0,1,4,7,8,9,10,15) 16 STATES
TRUTH TABLE STATES MAP
STATES A B C D Y
S13 =1101
S0 0 0 0 0 1
S1 0 0 0 1 1
S2 0 0 1 0 0 D

S3 0 0 1 1 0
S0 S1 S3 S2
S4 0 1 0 0 1
S5 0 1 0 1 0 1 1 0 0
S6 0 1 1 0 0
S7 0 1 1 1 1 S4 S5 S7 S6
B
S8
S9
1
1
0
0
0
0
0
1
1
1
1 0 1 0
S10 1 0 1 0 1 S12 S13 S15 S14
S11
S12
1
1
0
1
1
0
1
0
0
0
0 0 1 0
S8 S9 S11 S10
S13 1 1 0 1 0 A
S14
S15
1
1
1
1
1
1
0
1
0
1
1 1 0 C
1
I.6. Minimization of logic function
• This could be done by many methods:
1. make use the lowest number of zeros(POS) or ones (SOP).
2. Sum up two, four , eight, or multiple adjacent states if they
are ones or zeros.
from the last example , if we sum up S0+S1, we get:
A’ B’ C’ D’+ A’ B’ C’ D= A’ B’ C’
also if we sum up S8+S9 , we get:
A B’ C’ D’ +A B’ C’ D = A B’ C’
So iwe sum both, i.e. S0+S1+S8+S9, we get: (B’C’)
Therefore after summing up the remaining ones , we get:
Y= BC+ A B D + A B D.
You may see that the last two terms could be minimized to:
I.6. Minimization of logic function (cont)
Y= BC+ A’ B D’ + A B’ D’ = BC + D’(A’B +AB’)=BC +D’ (A B)
ABCD D
Y=F(A,B,C,D)=∑(0,1,4,7,8,9,10,15) 16 STATES
TRUTH TABLE STATES MAP
STAT A B C D Y
ES
S0 0 0 0 0 1
S1 0 0 0 1 1 D
S2 0 0 1 0 0
S3 0 0 1 1 0 S0 S1 S3 S2
S4
S5
0
0
1
1
0
0
0
1
1
0
1 1 0 0
S6 0 1 1 0 0
S4 S5 S7 S6
S7 0 1 1 1 1 B
S8 1 0 0 0 1 1 0 1 0
S9 1 0 0 1 1
S12 S13 S15 S14
S10 1 0 1 0 1
S11 1 0 1 1 0 0 0 1 0
S12 1 1 0 0 0 S8 S9 S11 S10
A
S13 1 1 0 1 0
S14 1 1 1 0 0 1 1 0 C
1
S15 1 1 1 1 1
Y=F(A,B,C,D)=∑(0,1,4,7,8,9,10,15) 16 STATES
TRUTH TABLE STATES MAP
STAT A B C D Y
ES
S0 0 0 0 0 1 A’B’C’D’+A’B’C’D= A’B’C’(D’+D) = A’B’C’
S1 0 0 0 1 1 D
S2 0 0 1 0 0
S3 0 0 1 1 0 S0 S1 S3 S2
S4
S5
0
0
1
1
0
0
0
1
1
0
1 1 0 0
S6 0 1 1 0 0
S4 S5 S7 S6
S7 0 1 1 1 1 B
S8 1 0 0 0 1 1 0 1 0
S9 1 0 0 1 1
S12 S13 S15 S14
S10 1 0 1 0 1
S11 1 0 1 1 0 0 0 1 0
S12 1 1 0 0 0 S8 S9 S11 S10
A
S13 1 1 0 1 0
S14 1 1 1 0 0 1 1 0 C
1
S15 1 1 1 1 1
Y=F(A,B,C,D)=∑(0,1,4,7,8,9,10,15) 16 STATES
TRUTH TABLE STATES MAP
STAT A B C D Y
ES
S0 0 0 0 0 1 A’B’C’D’+A’B’C’D=A’B’C’(D’+D)=A’B’C’
S1 0 0 0 1 1 D
S2 0 0 1 0 0
S3 0 0 1 1 0 S0 S1 S3 S2
S4
S5
0
0
1
1
0
0
0
1
1
0
1 1 0 0
S6 0 1 1 0 0
S4 S5 S7 S6
S7 0 1 1 1 1 B
S8 1 0 0 0 1 1 0 1 0
S9 1 0 0 1 1
S12 S13 S15 S14
S10 1 0 1 0 1
S11 1 0 1 1 0 AB’C’ 0 0 1 0
S12 1 1 0 0 0 S8 S9 S11 S10
A
S13 1 1 0 1 0
S14 1 1 1 0 0 1 1 0 C
1
S15 1 1 1 1 1
Y=F(A,B,C,D)=∑(0,1,4,7,8,9,10,15) 16 STATES
TRUTH TABLE STATES MAP
STAT A B C D Y A’B’C’+AB’C’=B’C’(A+A’)=B’C’
ES
S0 0 0 0 0 1 A’B’C’D’+A’B’C’D=A’B’C’(D’+D)=A’B’C’

S1 0 0 0 1 1 D
S2 0 0 1 0 0
S3 0 0 1 1 0 S0 S1 S3 S2
S4
S5
0
0
1
1
0
0
0
1
1
0
1 1 0 0
S6 0 1 1 0 0 B’C’ S4 S5 S7 S6
S7 0 1 1 1 1 B
S8 1 0 0 0 1 1 0 1 0
S9 1 0 0 1 1
S12 S13 S15 S14
S10 1 0 1 0 1
S11 1 0 1 1 0
AB’C’
0 0 1 0
S12 1 1 0 0 0 S8 S9 S11 S10
A
S13 1 1 0 1 0
S14 1 1 1 0 0 1 1 0 C
1
S15 1 1 1 1 1
Y=F(A,B,C,D)=∑(0,1,4,7,8,9,10,15) 16 STATES
TRUTH TABLE STATES MAP
STAT A B C D Y
ES
A’B’C’+AB’C’=B’C’(A+A’)=B’C’
S0 0 0 0 0 1
S1 0 0 0 1 1 D
S2 0 0 1 0 0
S3 0 0 1 1 0 S0 S1 S3 S2
S4
S5
0
0
1
1
0
0
0
1
1
0
1 1 0 0
S6 0 1 1 0 0 B’C’ S4 S5 S7 S6
S7 0 1 1 1 1 B
S8 1 0 0 0 1 1 0 1 0
S9 1 0 0 1 1
S12 S13 S15 S14
S10 1 0 1 0 1
S11 1 0 1 1 0 0 0 1 0
S12 1 1 0 0 0 S8 S9 S11 S10
A
S13 1 1 0 1 0
S14 1 1 1 0 0 1 1 0 C
1
S15 1 1 1 1 1
Y=F(A,B,C,D)=∑(0,1,4,7,8,9,10,15) 16 STATES
TRUTH TABLE STATES MAP
STAT A B C D Y
ES B’C’
S0 0 0 0 0 1
S1 0 0 0 1 1 D
S2 0 0 1 0 0
S3 0 0 1 1 0 S0 S1 S3 S2
S4
S5
0
0
1
1
0
0
0
1
1
0
1 1 0 0
S6 0 1 1 0 0
S4 S5 S7 S6
S7 0 1 1 1 1 B
S8 1 0 0 0 1 1 0 1 0
S9 1 0 0 1 1
S12 S13 S15 S14
S10 1 0 1 0 1
S11 1 0 1 1 0 AB’C’ 0 0 1 0
S12 1 1 0 0 0 S8 S9 S11 S10
A
S13 1 1 0 1 0
S14 1 1 1 0 0 1 1 0 C
1
S15 1 1 1 1 1 AB’D’
Y=F(A,B,C,D)=∑(0,1,4,7,8,9,10,15) 16 STATES
TRUTH TABLE STATES MAP
STAT A B C D Y A’B’C’+AB’C’=B’C’(A+A’)=B’C’
ES
S0 0 0 0 0 1 A’B’C’D’+A’B’C’D=A’B’C’(D’+D)=A’B’C’

S1 0 0 0 1 1 D
S2 0 0 1 0 0
S3 0 0 1 1 0 S0 S1 S3 S2
S4
S5
0
0
1
1
0
0
0
1
1
0
1 1 0 0
S6 0 1 1 0 0 B’C’ S4 S5 S7 S6
S7 0 1 1 1 1 B
S8 1 0 0 0 1 1 0 1 0
S9 1 0 0 1 1
S12 S13 S15 S14
S10 1 0 1 0 1
S11 1 0 1 1 0
AB’C’
0 0 1 0
S12 1 1 0 0 0 S8 S9 S11 S10
A
S13 1 1 0 1 0
S14 1 1 1 0 0 1 1 0 C
1
S15 1 1 1 1 1
Y=F(A,B,C,D)=∑(0,1,4,7,8,9,10,15) 16 STATES
TRUTH TABLE STATES MAP
STAT A B C D Y A’B’C’+AB’C’=B’C’(A+A’)=B’C’
ES A’B’C’D’+A’B’C’D=A’B’C’(D’+D)=A’B’C’
S0 0 0 0 0 1
S1 0 0 0 1 1 D
S2 0 0 1 0 0
BCD
S3 0 0 1 1 0 S0 S1 S3 S2
A’C’D’
S4
S5
0
0
1
1
0
0
0
1
1
0
1 1 0 0
S6 0 1 1 0 0
S4 S5 S7 S6
S7 0 1 1 1 1 B
S8 1 0 0 0 1 B’C’ 1 0 1 0
S9 1 0 0 1 1
S12 S13 S15 S14
S10 1 0 1 0 1
S11 1 0 1 1 0 0 0 1 0
S12 1 1 0 0 0 S8 S9 S11 S10
A
S13 1 1 0 1 0
S14 1 1 1 0 0 AB’D’ 1 1 0 C
1
S15 1 1 1 1 1
Y=B’ C’ + A’C’D’ + BCD +AB’D’

ABCD A’B’C’D’
Example1: Realize
y=∑(0,2,5,7,8,10,13,15)
D

S0 S1 S3 S2

1 0 0 1
S4 S5 S7 S6
B
0 1 1 0
S12 S13 S15 S14

0 1 1 0
S8 S9 S11 S10
A
1 0 0 1
C
Example1: Realize
y=∑(0,2,5,7,8,10,13,15)
D
B’ D’
S0 S1 S3 S2

y= B’ D’ + B D 1 0
1 0 1
0
BD
S4 S5 S7 S6
B
0
1 1
0 1 0
S12 S13 S15 S14

0 1
0 1 0
S8 S9 S11 S10
A

1 0
1 0 C
1
Y=B D + B’D’

ABCD A’B’C’D’
Example1: Realize
y=∑(0,2,5,7,8,10,13,15)=BD + B’ D’
W=B’D+BD’; W’=BD+B’ D’
D
B’ D’
S0 S1 S3 S2

1 0
1 0 1
0
BD
S4 S5 S7 S6
B
0
1 1
0 1 0
S12 S13 S15 S14

0 1
0 1 0
S8 S9 S11 S10
A

1 0
1 0 C
1
I.7. By NAND gates ONLY
• Consider the expression
Y= BC+ A B D + A B D.
Applying De Morgan two times we can get NAND expressions as:

Y= (BC)( A B D )( A B D )

Y= (BC) (ABD) (ABD ) = UV W

And the resulting electronic circuit will be as shown.


Y= BC+ A’ B D’ + A B’ D’.
Y= { (BC)’ ( A’ B D’ )’ ( A B’ D’ )’ }’
• ABCD A B D
I.7. By NOR gates ONLY
Y= (BC)( A B D )( A B D )

Y= (B’+C’) + ( A +B’+ D ) + ( A’+ B+ D )

Y’ = (B’+C’) + ( A +B’+ D ) + ( A’+ B+ D )


I.7. By NOR gates ONLY
Y= (BC)( A B D )( A B D )

Y= (B’+C’) + ( A +B’+ D ) + ( A’+ B+ D )

Y’’ = (B’+C’) + ( A +B’+ D ) + ( A’+ B+ D )


Example1: Realize
y=∑(0,2,5,7,8,10,13,15)=BD + B’ D’
by NAND gates ONLY
Y’= (BD + B’ D’)’
=(BD)’ (B’ D’)’
y= [(BD)’ (B’D’)’ ]’
by NOR gates ONLY
Y= [(B’+D’) (B + D)]’
Y’= [ (B’+D’)’ + (B + D)’ ]’
Y= {[ (B’+D’)’ + (B + D)’ ]’ }’
• BD B’ D’

Y
I.8. By NOR gates ONLY
• Consider the expression
Y= BC+ A B D + A B D.
Applying De Morgan two times we can get NAND expressions as:

Y= (BC)( A B D )( A B D).
Applying De Morgan two times we can get NOR expressions as:

Y=(B + C )+ (A +B + D) + (A + B + D )
And the resulting electronic circuit will be as shown.
• ABCD A B C
I .7. Undefined states
• The undefined state is that could arbitrarly be 0 or 1 without
any effect on the logic function.
• Consider the following example

• Y=∑ (0,1,4,7,8,9,10,15) + Φ ( 7,11, 14)


• Adding undefined states helps in simplifying the logic function
and its realization.
• Y=( A + B + C) ( B +C + D ) (A + B + C )
Y=F(A,B,C,D) 16 STATES
STATES MAP
Y = B’C’ + BC + AB’ +A’ C’ D’ Y=∑ (0,1,4,6,8,9,10,15) + Φ ( 7,11, 14)

B’C’
D

S0 S1 S3 S2

A’C’D’ 1 1 0 0 BC

S4 S5 S7 S6
B
1 0 Φ 1
S12 S13 S15 S14
AB’
0 0 1 Φ
S8 S9 S11 S10
A

1 1 Φ 1 C
Y=F(A,B,C,D) 16 STATES
STATES MAP
Y=∑ (0,1,4,6,8,9,10,15) + Φ ( 7,11, 14)

A + B + C’
D

Y=( A+B+C’)(B’+C+D’)(A’+B’+C) S0 S1 S3 S2

It is better to use Zeros 1 1 0 0


S4 S5 S7 S6
B
B’ +C + D’ 1 0 Φ 1
S12 S13 S15 S14

A’ + B’ + C 0 0 1 Φ
S8 S9 S11 S10
A

1 1 Φ 1 C
Y=F(A,B,C,D) 16 STATES
STATES MAP
Y=∑ (0,1,4,6,8,9,10,15) + Φ ( 7,11, 14)
D

B’C’
S0 S1 S3 S2

A’B D’ 1 1 0 0
S4 S5 S7 S6
B
1 0 Φ 1
S12 S13 S15 S14 AC

0 0 1 Φ
S8 S9 S11 S10
A

1 1 Φ 1 C

Y = B’C’ + AC +A’ B D’
Y=F(A,B,C,D) 16 STATES
STATES MAP
Y = B’C’ + BC + AB’ +A’ C’ D’ Y=∑ (0,1,4,6,8,9,10,15) + Φ ( 7,11, 14)

B’C’
A + B + C’
D

Y=( A+B+C’)(B’+C+D’)(A’+B’+C) S0 S1 S3 S2

It is better to use Zeros A’C’D’ 1 1 0 0 BC

S4 S5 S7 S6
B
B’ +C + D’ 1 0 Φ 1
S12 S13 S15 S14

A’ + B’ + C 0 0 1 Φ
S8 S9 S11 S10
AB’ A

1 1 Φ 1 C
Y=( A + B + C’) ( B’ +C + D’ ) (A’ + B’ + C )

A B C D A’ B’ C’ D’

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