LTC1149

LTC1149-3.3/LTC1149-5
High Efficiency Synchronous
Step-Down Switching Regulators
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FEATURES DESCRIPTIO
■ Operation to 48V Input Voltage The LTC ®1149 series is a family of synchronous step-
■ Ultrahigh Efficiency: Up to 95% down switching regulator controllers featuring automatic
■ Current Mode Operation for Excellent Line and Burst ModeTM operation to maintain high efficiencies at
Load Transient Response low output currents. These devices drive external comple-
■ High Efficiency Maintained over Wide Current Range mentary power MOSFETs at switching frequencies up
■ Logic-Controlled Micropower Shutdown to 250kHz using a constant off-time current-mode archi-
■ Short-Circuit Protection tecture.
■ Very Low Dropout Operation: 100% Duty Cycle Special onboard regulation and level-shift circuitry allow
■ Synchronous FET Switching for High Efficiency operation at input voltages from dropout to 48V (60V
■ Adaptive Nonoverlap Gate Drives absolute max). The constant off-time architecture main-
■ Available in 16-Pin Narrow SO Package tains constant ripple current in the inductor, easing the
UO design of wide input range converters. Current mode
APPLICATI S operation provides excellent line and load transient
■ Notebook and Palmtop Computers response. The operating current level is user-program-
■ Portable Instruments mable via an external current sense resistor.
■ Battery-Operated Digital Devices The LTC1149 series incorporates automatic power saving
■ Industrial Power Distribution Burst Mode operation when load currents drop below the
■ Avionics Systems level required for continuous operation. Standby power is
■ Telecom Power Supplies reduced to only about 8mW at VIN = 12V. In shutdown,
, LTC and LT are registered trademarks of Linear Technology Corporation. both MOSFETs are turned off.
Burst Mode is a trademark of Linear Technology Corporation.

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TYPICAL APPLICATI
VIN

LTC1149-5 Efficiency
1N4148
+ CIN
VIN 1N4148 100µF 100
CAP P-CHANNEL 100V FIGURE 1 CIRCUIT
PGATE VIN = 12V
0.068µF IRFR9024

+ VCC 0.047µF
90
3.3µF PDRIVE D1
VCC L* RSENSE**
EFFICIENCY (%)

1N5819 62µH 0.05Ω

LTC1149-5 VOUT VIN = 24V
5V/2A 80
0V = NORMAL SHDN1 SENSE +
>2V = SHUTDOWN SHDN2 1000pF
SENSE –
ITH + 70
3300µF N-CHANNEL COUT
CT NGATE
IRFR024 220µF
CT SGND P, RGNDS
1k 470pF
60
*COILTRONICS CTX62-2-MP 0.02 0.2 2
**KRL SL-1-C1-0R050J 1149 F01
LOAD CURRENT (A)
1149 TA01

Figure 1. High Efficiency Step-Down Regulator

1
LTC1149
LTC1149-3.3/LTC1149-5
W W W U U W U
ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
Input Supply Voltage (Pin 2)...................... – 15V to 60V TOP VIEW
ORDER PART
VCC Output Current (Pin 3) .................................. 50mA
PGATE 1 16 CAP NUMBER
VCC Input Voltage (Pin 5)........................................ 16V 2 15 SHDN2
VIN
Continuous Output Current (Pins 4, 13) .............. 50mA
Sense Voltages (Pins 8, 9)
VCC 3 14 RGND
LTC1149CN
4 13 NGATE
PDRIVE
LTC1149CN-3.3
VIN ≥ 12.7V .......................................... 13V to – 0.3V VCC 5 12 PGND
LTC1149CN-5
VIN < 12.7V ............................. (VCC + 0.3V) to – 0.3V CT 6 11 SGND
VFB / LTC1149CS
Shutdown Voltages (Pins 10, 15) ............................. 7V ITH 7 10 SHDN1*
LTC1149CS-3.3
Operating Temperature Range .................... 0°C to 70°C SENSE – 8 9 SENSE +
LTC1149CS-5
Extended Commercial N PACKAGE S PACKAGE
Temperature Range ............................... – 40°C to 85°C 16-LEAD PDIP 16-LEAD PLASTIC SO
*FIXED OUTPUT VERSIONS
Junction Temperature (Note 1) ............................ 125°C TJMAX = 125°C, θJA = 70°C/ W (N)
Storage Temperature Range ................ – 65°C to 150°C TJMAX = 125°C, θJA = 110°C/ W (S)

Lead Temperature (Soldering, 10 sec)................. 300°C

Consult factory for Industrial and Military grade parts.

ELECTRICAL CHARACTERISTICS TA = 25°C, VIN = 12V, V10 = 0V (Note 2), unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V10 Feedback Voltage (LTC1149 Only) VIN = 9V ● 1.21 1.25 1.29 V
I10 Feedback Current (LTC1149 Only) ● 0.2 1 µA
VOUT Regulated Output Voltage VIN = 9V
LTC1149-3.3 ILOAD = 700mA ● 3.23 3.33 3.43 V
LTC1149-5 ILOAD = 700mA ● 4.9 5.05 5.2 V
∆VOUT Output Voltage Line Regulation VIN = 9V to 48V, ILOAD = 50mA – 40 0 40 mV
Output Voltage Load Regulation
LTC1149-3.3 5mA < ILOAD < 2A ● 40 65 mV
LTC1149-5 5mA < ILOAD < 2A ● 60 100 mV
Burst Mode Output Ripple ILOAD = 0A 50 mVP-P
I2 Input DC Supply Current (Note 3)
Normal Mode VIN = 12V 2.0 2.8 mA
VIN = 48V 2.2 3.0 mA
Burst Mode VIN = 12V 0.6 0.9 mA
VIN = 48V 0.8 1.1 mA
Shutdown VIN = 12V, V15 = 2V 135 170 µA
VIN = 48V, V15 = 2V 300 390 µA
VCC Internal Regulator Voltage VIN = 12V to 48V ● 9.75 10.25 11 V
(Sets MOSFET Gate Drive Levels) I3 = 20mA
V2 – V3 VCC Dropout Voltage VIN = 5V, I3 = 10mA 200 250 mV
VIN – V1 P-Gate to Source Voltage (Off) VIN = 12V ● – 0.2 0 V
VIN = 48V ● – 0.2 0 V

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 LTC1149
LTC1149-3.3/LTC1149-5
ELECTRICAL CHARACTERISTICS TA = 25°C, VIN = 12V, V10 = 0V (Note 2), unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V 9 – V8 Current Sense Threshold Voltage
LTC1149 V8 = 5V, V10 = 1.32V (Forced) 25 mV
V8 = VOUT – 100mV ● 130 150 170 mV
LTC1149-3.3 V8 = 3.5V (Forced) 25 mV
V8 = VOUT – 100mV ● 130 150 170 mV
LTC1149-5 V8 = 5.3V (Forced) 25 mV
V8 = VOUT – 100mV ● 130 150 170 mV
V10 Shutdown 1 Threshold
LTC1149-3.3, LTC1149-5 0.5 0.8 2 V
V15 Shutdown 2 Threshold 0.8 1.4 2 V
I15 Shutdown 2 Input Current V15 = 5V 18 25 µA
I6 CT Pin Discharge Current VOUT In Regulation, VSENSE– = VOUT 50 70 90 µA
VOUT = 0V 2 10 µA
tOFF Off-Time (Note 4) CT = 390pF, ILOAD = 700mA 4 5 6 µs
tr, tf Driver Output Transition Times CL = 3000pF (Pins 4, 13), VIN = 6V 100 200 ns

– 40°C ≤ TA ≤ 85°C (Note 5), unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V10 Feedback Voltage LTC1149 Only 1.2 1.25 1.3 V
VOUT Regulated Output Voltage VIN = 9V
LTC1149-3.3 ILOAD = 700mA 3.17 3.33 3.43 V
LTC1149-5 ILOAD = 700mA 4.85 5.05 5.2 V
I2 Input DC Supply Current (Note 3)
Normal Mode VIN = 12V 2.0 3.2 mA
VIN = 48V 2.2 3.5 mA
Burst Mode VIN = 12V 0.6 1.05 mA
VIN = 48V 0.8 1.30 mA
Shutdown VIN = 12V, V15 = 2V 135 230 µA
VIN = 48V, V15 = 2V 300 520 µA
VCC Internal Regulator Voltage VIN = 12V to 48V 9.75 10.25 11 V
(Sets MOSFET Gate Drive Levels) I3 = 20mA
V9 – V 8 Current Sense Threshold Voltage Low Threshold (Forced) 25 mV
High Threshold (Forced) 125 150 175 mV
V15 Shutdown 2 Threshold 0.8 1.4 2 V
tOFF Off-Time (Note 4) CT = 390pF, ILOAD = 700mA, VIN = 10V 3.8 5 6 µs
The ● denotes specifications which apply over the full operating Note 3: Dynamic supply current is higher due to the gate charge being
temperature range. delivered at the switching frequency. The allowable operating frequency
Note 1: TJ is calculated from the ambient temperature TA and power may be limited by power dissipation at high input voltages. See Typical
dissipation PD according to the following formulas: Performance Characteristics and Applications Information.
LTC1149CN, LTC1149CN-3.3, LTC1149CN-5: TJ = TA + (PD )(70°C/W) Note 4: In applications where RSENSE is placed at ground potential, the off-
LTC1149CS, LTC1149CS-3.3, LTC1149CS-5: TJ = TA + (PD)(110°C/W) time increases approximately 40%.
Note 2: Pin 10 is a shutdown pin on the LTC1149-3.3 and LTC1149-5 Note 5: The LTC1149, LTC1149-3.3, and LTC1149-5 are not tested and
fixed output voltage versions and must be at ground potential for testing. not quality assurance sampled at – 40°C and 85°C. These specifications
are guaranteed by design and/or correlation.

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LTC1149
LTC1149-3.3/LTC1149-5
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Input Voltage Line Regulation Load Regulation
100 60 20
FIGURE 1 CIRCUIT FIGURE 1 CIRCUIT FIGURE 1 CIRCUIT
ILOAD = 1A ILOAD = 1A VIN = 24V
40 0
95
20 –20
EFFICIENCY (%)

∆VOUT (mV)
∆VOUT (mV)
90 0 –40

–20 –60
85
–40 –80

80 –60 –100
0 10 20 30 40 50 0 10 20 30 40 50 0 0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V) INPUT VOLTAGE (V) LOAD CURRENT (A)
1149 G01 1149 G02 1149 G03

Operating Frequency
DC Supply Current Supply Current in Shutdown vs (VIN – VOUT)
3.0 400 2.0
VSD2 = 2V VOUT = 5V
2.5 T = 0°C

NORMALIZED FREQUENCY
300 1.5
SUPPLY CURRENT (mA)

SUPPLY CURRENT (µA)

ACTIVE MODE
2.0 T = 25°C
T = 70°C
1.5 200 1.0

1.0
SLEEP MODE
100 0.5
0.5

0 0 0
0 10 20 30 40 50 0 10 20 30 40 50 0 5 10 15 20 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V) (VIN – VOUT) VOLTAGE (V)
1149 G04 1149 G05 1149 G06

Gate Charge Supply Current Off-Time vs VOUT Current Sense Threshold Voltage
30 80 160

70 140 MAXIMUM
25
GATE CHARGE CURRENT (mA)

THRESHOLD
60 120
SENSE VOLTAGE (mV)

20
OFF-TIME (µs)

QP + QN = 100nC 50 100

15 40 80

30 60
10
QP + QN = 50nC 20 40 MINIMUM
5 THRESHOLD
10 LTC1149-5 20
LTC1149-3.3
0 0 0
50 100 150 200 250 0 1 2 3 4 5 0 20 40 60 80 100
OPERATING FREQUENCY (kHz) OUTPUT VOLTAGE (V) TEMPERATURE (°C)
1149 G07 1149 G08 1149 G09

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 LTC1149
LTC1149-3.3/LTC1149-5
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PI FU CTIO S
PGATE (Pin 1): Level-Shifted Gate Drive Signal for Top SHDN1/VFB (Pin 10): In fixed output voltage versions, Pin
P-Channel MOSFET. The voltage swing at Pin 1 is from VIN 10 serves as a shutdown pin for the control circuitry only
to VIN – VCC. (VCC is not affected). Taking Pin 10 of the LTC1149-3.3 or
VIN (Pin 2): Main Supply Input Pin. LTC1149-5 high holds both MOSFETs off. Must be at
ground potential for normal operation.
VCC (Pin 3): Output Pin of Low Dropout 10V Regulator. Pin
3 is not protected against DC short circuits. For the LTC1149 adjustable version, Pin 10 serves as the
feedback pin from an external resistive divider used to set
PDRIVE (Pin 4): High Current Gate Drive for Top the output voltage.
P-Channel MOSFET. The voltage swing at Pin 4 is from VCC
to ground. SGND (Pin 11): Small-Signal Ground. Must be routed
separately from other grounds to the (–) terminal of COUT.
VCC (Pin 5): Regulated 10V Input for Driver and Control
Supplies. Must be closely decoupled to power ground. PGND (Pin 12): Driver Power Ground. Connects to source
of N-channel MOSFET and the (–) terminal of CIN.
CT (Pin 6): External capacitor CT from Pin 6 to ground sets
the operating frequency. (The frequency is also dependent NGATE (Pin 13): High Current Drive for Bottom
on the ratio VOUT/VIN.) N-channel MOSFET. The voltage swing at Pin 13 is from
ground to VCC.
ITH (Pin 7): Gain Amplifier Decoupling Point. The current
comparator threshold increases with the Pin 7 voltage. RGND (Pin 14): Low Dropout Regulator Ground. Con-
nects to power ground.
SENSE – (Pin 8): Connects to internal resistive divider
which sets the output voltage in LTC1149-3.3 and SHDN2 (Pin 15): Master Shutdown Pin. Taking Pin 15
LTC1149-5 versions. Pin 8 is also the (–) input for the high shuts down VCC and all control circuitry; requires a
current comparator. logic signal with tr, tf < 1µs.
SENSE+ (Pin 9): The (+) Input for the Current Comparator. CAP (Pin 16): Charge Compensation Pin. A capacitor from
A built-in offset between Pins 8 and 9 in conjunction with Pin 16 to VCC provides the charge required by the P-drive
RSENSE sets the current trip threshold. level-shift capacitor during supply transitions. The Pin 16
capacitor must be larger than the Pin 4 capacitor.

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OPERATIO (Refer to Functional Diagram)

The LTC1149 series uses a current mode, constant off- A low dropout 10V regulator provides the operating volt-
time architecture to synchronously switch an external pair age VCC for the MOSFET drivers and control circuitry. The
of complementary power MOSFETs. Operating frequency driver outputs at Pins 4 and 13 are referenced to ground,
is set by an external capacitor at the timing capacitor, which fulfills the N-channel MOSFET gate drive require-
Pin 6. ment. The P-channel gate drive at Pin 1 must be refer-
The output voltage is sensed either by an internal voltage enced to the main supply input VIN, which is accomplished
divider connected to SENSE–, Pin 8 (LTC1149-3.3 and by level-shifting the Pin 4 signal via an internal 500k
LTC1149-5) or an external divider returned to VFB Pin 10 resistor and external capacitor.
(LTC1149). A voltage comparator V, and a gain block G, During the switch “ON” cycle in continuous mode, current
compare the divided output voltage with a reference comparator C monitors the voltage between Pins 8 and 9
voltage of 1.25V. To optimize efficiency, the LTC1149 connected across an external shunt in series with the
series automatically switches between two modes of inductor. When the voltage across the shunt reaches its
operation, burst and continuous. The voltage comparator threshold value, the PGATE output is switched to VIN,
is the primary control element for Burst Mode operation, turning off the P-channel MOSFET. The timing capacitor
while the gain block controls the output voltage in continu- connected to Pin 6 is now allowed to discharge at a rate
ous mode. determined by the off-time controller. The discharge

5
LTC1149
LTC1149-3.3/LTC1149-5
U
OPERATIO (Refer to Functional Diagram)
current is made proportional to the output voltage (mea- The circuit now enters sleep mode with both power
sured by Pin 8) to model the inductor current, which MOSFETs turned off. In sleep mode, much of the circuitry
decays at a rate which is also proportional to the output is turned off, dropping the supply current from several
voltage. While the timing capacitor is discharging, the milliamperes (with the MOSFETs switching) to 600µA.
NGATE output is high, turning on the N-channel MOSFET. When the output capacitor has discharged by the amount
When the voltage on the timing capacitor has discharged of hysteresis in comparator V, the P-channel MOSFET is
past VTH1, comparator T trips, setting the flip-flop. This again turned on and this process repeats. To avoid the
causes the NGATE output to go low (turning off the operation of the current loop interfering with Burst Mode
N-channel MOSFET) and the PGATE output to also go low operation, a built-in offset is incorporated in the gain
(turning the P-channel MOSFET back on). The cycle then stage. This prevents the current comparator threshold
repeats. from increasing until the output voltage has dropped
below a minimum threshold.
As the load current increases, the output voltage
decreases slightly. This causes the output of the gain To prevent both the external MOSFETs from ever being
stage to increase the current comparator threshold, thus turned on at the same time, feedback is incorporated to
tracking the load current. sense the state of the driver output pins. Before the N-gate
output can go high, the P-drive output must also be high.
The sequence of events for Burst Mode operation is very Likewise, the P-drive output is prevented from going low
similar to continuous operation with the cycle interrupted when the N-gate output is high.
by the voltage comparator. When the output voltage is at
or above the desired regulated value, the P-channel MOSFET Using constant off-time architecture, the operating fre-
is held off by comparator V and the timing capacitor quency is a function of the input voltage. To minimize the
continues to discharge below VTH1. When the timing frequency variation as dropout is approached, the off-
capacitor discharges past VTH2, voltage comparator S time controller increases the discharge current as VIN
trips, causing the internal SLEEP line to go low and the drops below VOUT + 1.5V. In dropout the P-channel
MOSFET is turned on continuously.
N-channel MOSFET to turn off.
U U W
FU CTIO AL DIAGRA Pin 10 connection shown for LTC1149-3.3 and LTC1149-5; changes create LTC1149.
VIN
2
1 PGATE
CAP 5 VCC
500k
16
SHDN2 LOW VCC 4 PDRIVE
500k
DROPOUT
15 3
10V
REGULATOR 13 NGATE
14 RGND 12 PGND 9 SENSE + 8 SENSE –
–

V
+
R
Q –
SLEEP S
C
+ 25mV TO 150mV
– VOS
VTH1
–
T 13k
+ G
+ 100k
+
S
– VTH2 1.25V
VIN
OFF-TIME
6
CONTROL SENSE – 7 11 REFERENCE 10
CT ITH SGND SHDN1
(VFB) 1149 FD

6
 LTC1149
LTC1149-3.3/LTC1149-5
TEST CIRCUIT

+ +
IRF9Z34 220µF
0.1µF VIN 0.068µF 100V
MBR380

1 16
PGATE CAP + IRFZ34
V15
2 15
VIN SHDN2
0.047µF
3 14
VCC RGND

+ 4 13
PDRIVE NGATE
1µF 50µH
5 LTC1149 12
VCC PGND
6 11
CT SGND +
7 VFB / 10 V10
ITH 25k
SHDN1
390pF 3300pF 8 9
SENSE – SENSE +
+ + 220µF
1k V8 75k
+ 0.05Ω
V9 – V8
1000pF
VOUT
1149 TC

U U W U
APPLICATIO S I FOR ATIO
Typical Application Circuit Since efficiency generally increases with ripple current,
The basic LTC1149 series application circuit is shown in the maximum allowable ripple current is assumed, i.e.,
Figure 1. External component selection is driven by the IRIPPLE(P-P) = 25mV/RSENSE (see CT and L Selection for
input voltage and output load requirement, and begins Operating Frequency). Solving for RSENSE and allowing a
with the selection of RSENSE. Once RSENSE is known, CT margin for variations in the LTC1149 series and external
and L can be chosen. Next, the power MOSFETs and D1 component values yields:
are selected. Finally, CIN and COUT are selected and the
loop is compensated. The circuit shown in Figure 1 can be RSENSE = 100mV
IMAX
configured for operation up to an input voltage of 48V. If
the application does not require greater than 15V opera- A graph for selecting RSENSE versus maximum output
tion, then the LTC1148 should be used. current is given in Figure 2. The LTC1149 series works well
with values of RSENSE from 0.02Ω to 0.2Ω.
RSENSE Selection for Output Current
The load current below which Burst Mode operation
RSENSE is chosen based on the required output current. commences, IBURST, and the peak short-circuit current,
The LTC1149 series current comparator has a threshold ISC(PK), both track IMAX. Once RSENSE has been chosen,
range which extends from a minimum of 25mV/RSENSE to IBURST and ISC(PK) can be predicted from the following
a maximum of 150mV/RSENSE. The current comparator equations:
threshold sets the peak of the inductor ripple current,
yielding a maximum output current IMAX equal to the peak IBURST ≈ 15mV
value less half the peak-to-peak ripple current. For proper RSENSE
Burst Mode operation, IRIPPLE(P-P) must be less than or
equal to the minimum current comparator threshold. ISC(PK) = 150mV
RSENSE

7
LTC1149
LTC1149-3.3/LTC1149-5
U U W U
APPLICATIO S I FOR ATIO
The LTC1149 series automatically extends tOFF during a
short circuit to allow sufficient time for the inductor
current to decay between switch cycles. The resulting
f= 1
tOFF )1–
VOUT
VIN )
ripple current causes the average short-circuit current where:

) )
ISC(AVG) to be reduced to approximately IMAX.
VREG
tOFF = (1.3)(104)(CT)
0.20 VOUT
0.18
0.16 VREG is the desired output voltage (i.e., 5V, 3.3V), while
0.14 VOUT is the actual output voltage. Thus VREG/VOUT = 1
when in regulation.
RSENSE (Ω)

0.12
0.10
Note that as VIN decreases, the frequency decreases.
0.08
When the input to output voltage differential drops below
0.06
1.5V, the LTC1149 series reduces tOFF by increasing the
0.04
0.02
discharge current in CT. This prevents audible operation
0
prior to dropout.
0 1 2 3 4 5
MAXIMUM OUTPUT CURRENT (A) Once the frequency has been set by CT, the inductor L must
1149 F02 be chosen to provide no more than 25mV/RSENSE of peak-
Figure 2. RSENSE vs Maximum Output Current to-peak inductor ripple current. This results in a minimum
required inductor value of:
L and CT Selection for Operating Frequency LMIN =( 5.1)(105)(RSENSE)(CT)(VREG)
The LTC1149 series uses a constant off-time architecture As the inductor value is increased from the minimum
with tOFF determined by an external timing capacitor CT. value, the ESR requirements for the output capacitor are
Each time the P-channel MOSFET switch turns on, the eased at the expense of efficiency. If too small an inductor
voltage on CT is reset to approximately 3.3V. During the is used, the inductor current will decrease past zero and
off-time, CT is discharged by a current which is propor- change polarity. A consequence of this is that the LTC1149
tional to VOUT. The voltage on CT is analogous to the series may not enter Burst Mode operation and efficiency
current in inductor L, which likewise decays at a rate will be severely degraded at low currents.
proportional to VOUT. Thus the inductor value must track
1400
the timing capacitor value. VOUT = 5V
1200
The value of CT is calculated from the desired continuous
mode operating frequency, f:
CT CAPACITANCE (pF)

1000

) )
800
–5 V
CT = (7.8)(10 ) 1 – OUT VIN = 48V
f VIN 600

400 VIN = 24V

A graph for selecting CT versus frequency including the
effects of input voltage is given in Figure 3. 200
VIN = 12V
0
As the operating frequency is increased the gate charge 0 50 100 150 200 250
losses will be higher, reducing efficiency (see Efficiency FREQUENCY (kHz)

Considerations). The complete expression for operating 1149 F03

frequency is given by: Figure 3. Timing Capacitor Selection

8
 LTC1149
LTC1149-3.3/LTC1149-5
U U W U
APPLICATIO S I FOR ATIO
Inductor Core Selection Selection criteria for the P-channel MOSFET include the
Once the minimum value for L is known, the type of on-resistance RDS(ON), reverse transfer capacitance CRSS,
inductor must be selected. High efficiency converters input voltage and maximum output current. When the
generally cannot afford the core loss found in low cost LTC1149 is operating in continuous mode, the duty cycle
powdered iron cores, forcing the use of more expensive for the P-channel MOSFET is given by:
ferrite, molypermalloy, or Kool Mµ® cores. Actual core V
loss is independent of core size for a fixed inductor value, P-Ch Duty Cycle = OUT
VIN
but it is very dependent on inductance selected. As induc-
tance increases, core losses go down. Unfortunately, The P-channel MOSFET dissipation at maximum output
increased inductance requires more turns of wire and current is given by:
therefore copper losses increase.
V
P-Ch PD = OUT (IMAX)2(1 + ∂P) RDS(ON)
Ferrite designs have very low core loss, so design goals VIN
can concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that + K(VIN)2(IMAX)(CRSS)(f)
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in where ∂ is the temperature dependency of RDS(ON) and K
inductor ripple current and consequent output voltage is a constant related to the gate drive current. Note the two
ripple which can cause Burst Mode operation to be falsely distinct terms in the equation. The first gives the I2R
triggered in the LTC1149 series. Do not allow the core to losses, which are highest at low input voltages, while the
saturate! second gives the transition losses, which are highest at
high input voltages. For VIN < 24V, the high current
Molypermalloy (from Magnetics, Inc.) is a very good, low efficiency generally improves with larger MOSFETs
loss core material for toroids, but it is more expensive than (although gate charge losses begin eating into the gains.
ferrite. A reasonable compromise from the same manu- See Efficiency Considerations). For VIN > 24V, the transi-
facturer is Kool Mµ. Toroids are very space efficient, tion losses rapidly increase to the point that the use of a
especially when you can use several layers of wire. higher RDS(ON) device with lower CRSS actually provides
Because they generally lack a bobbin, mounting is more higher efficiency. This is illustrated in the Design Example
difficult. However, new surface mount designs available section.
from Coiltronics do not increase the height significantly.
The term (1 + ∂) is generally given for a MOSFET in the
P-Channel MOSFET Selection form of a normalized RDS(ON) vs temperature curve, but
∂ = 0.007/°C can be used as an approximation for low
Two external power MOSFETs must be selected for use
voltage MOSFETs. CRSS is usually specified in the MOSFET
with the LTC1149 series: a P-channel MOSFET for the
electrical characteristics. The constant K is much harder to
main switch, and an N-channel MOSFET for the synchro-
pin down, but K = 5 can be used for the LTC1149 series to
nous switch.
estimate the relative contributions of the two terms in the
The minimum input voltage determines whether standard P-channel dissipation equation.
threshold or logic-level threshold MOSFETs must be used.
For VIN > 8V, standard threshold MOSFETs (VGS(TH) < 4V) N-Channel MOSFET and D1 Selection
may be used. If VIN is expected to drop below 8V, logic- The same input voltage constraints apply to the N-channel
level threshold MOSFETs (VGS(TH) < 2.5V) are strongly MOSFET as to the P-channel with regard to when logic-
recommended. When logic-level MOSFETs are used, the level devices are required. However, the dissipation calcu-
absolute maximum VGS rating for the MOSFETs must be lation is quite different. The duty cycle and dissipation for
greater than the LTC1149 series internal regulator
voltage VCC. Kool Mµ is a registered trademark of Magnetics, Inc.

9
LTC1149
LTC1149-3.3/LTC1149-5
U U W U
APPLICATIO S I FOR ATIO
the N-channel MOSFET operating in continuous mode are ripple current ratings are often based on only 2000 hours
given by: of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
V –V temperature than required. Several capacitors may be
N-Ch Duty Cycle = IN OUT
VIN paralleled to meet size or height requirements in the
design. An additional 0.1µF ceramic capacitor may also be
V –V
N-Ch PD = IN OUT (IMAX)2 (1 + ∂N)RDS(ON) required on VIN for high frequency decoupling.
VIN
The selection of COUT is driven by the required effective
where ∂ is the temperature dependency of RDS(ON). Note series resistance (ESR). The ESR of COUT must be less
that there is no transition loss term in the N-channel than twice the value of RSENSE for proper operation of the
dissipation equation because the drain-to-source voltage LTC1149 series:
is always low when the N-channel MOSFET is turning on
COUT Required ESR < 2RSENSE
or off. The remaining I2R losses are the greatest at high
input voltage or during a short circuit, when the N-channel Optimum efficiency is obtained by making the ESR equal
duty cycle is nearly 100%. Fortunately, low RDS(ON) to RSENSE. As the ESR is increased up to 2RSENSE, the
N-channel MOSFETs are readily available which reduce efficiency degrades by less than 1%. If the ESR is greater
losses to the point that heat sinking is not required, even than 2RSENSE, the voltage ripple on the output capacitor
during continuous short-circuit operation. will prematurely trigger Burst Mode operation, resulting in
The Schottky diode D1 shown in Figure 1 only conducts disruption of continuous mode and an efficiency hit which
during the dead-time between the conduction of the two can be several percent.
power MOSFETs. D1’s sole purpose in life is to prevent the Manufacturers such as Nichicon, Chemicon and Sprague
body diode of the N-channel MOSFET from turning on and should be considered for high performance capacitors.
storing charge during the dead-time, which could cost as The OS-CON semiconductor dielectric capacitor available
much as 1% in efficiency (although there are no other from Sanyo has the lowest ESR for its size, at a somewhat
harmful effects if D1 is omitted). Therefore, D1 should be higher price. Once the ESR requirement for COUT has been
selected for a forward voltage of less than 0.7V when met, the RMS current rating generally far exceeds the
conducting IMAX. IRIPPLE(P-P) requirement.
Finally, both MOSFETs and D1 must be selected for In surface mount applications multiple capacitors may
breakdown voltages higher than the maximum VIN. have to be paralleled to meet the capacitance, ESR, or RMS
current handling requirements of the application. Alumi-
CIN and COUT Selection num electrolytic and dry tantalum capacitors are both
In continuous mode, the source current of the P-channel available in surface mount configurations. In the case of
MOSFET is a square wave of duty cycle VOUT/VIN. To tantalum, it is critical that the capacitors are surge tested
prevent large voltage transients, a low ESR input capacitor for use in switching power supplies. An excellent choice is
sized for the maximum RMS current must be used. The the AVX TPS series of surface mount tantalums, available
maximum RMS capacitor current is given by: in case heights ranging from 2mm to 4mm. For example,
if 200µF/10V is called for in an application requiring 3mm
IMAX [VOUT (VIN – VOUT)]1/2 height, two AVX 100µF/10V (P/N TPSD 107K010) could be
CIN Required IRMS ≈
VIN used. Consult the manufacturer for other specific recom-
mendations.
This formula has a maximum at VIN = 2VOUT, where
IRMS = IMAX/2. This simple worst-case condition is com- At low supply voltages, a minimum value of COUT is
monly used for design because even significant deviations suggested to prevent an abnormal low frequency operat-
do not offer much relief. Note that capacitor manufacturer’s ing mode (see Figure 4). When COUT is too small, the

10
 LTC1149
LTC1149-3.3/LTC1149-5
U U W U
APPLICATIO S I FOR ATIO
output ripple at low frequencies will be large enough to trip regulator loop adapts to the current change and returns
the voltage comparator. This causes the Burst Mode VOUT to its steady state value. During this recovery time
operation to be activated when the LTC1149 series would VOUT can be monitored for overshoot or ringing which
normally be in continuous operation. The effect is most would indicate a stability problem. The Pin 7 external
pronounced with low values of RSENSE and can be components shown in the Figure 1 circuit will prove
improved by operating at higher frequencies with lower adequate compensation for most applications.
values of L. The output remains in regulation at all times.
A second, more severe transient is caused by switching in
Checking Transient Response loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
Switching regulators take several cycles to respond to a
with COUT, causing a rapid drop in VOUT. No regulator can
step in DC (resistive) load current. When a load step deliver enough current to prevent this problem if the load
occurs, VOUT shifts by an amount equal to (∆ILOAD)(ESR), switch resistance is low and it is driven quickly. The only
where ESR is the effective series resistance of COUT. solution is to limit the rise time of the switch drive so that
∆ILOAD also begins to charge or discharge COUT until the the load rise time is limited to approximately (25)(CLOAD).
1000 Thus a 10µF capacitor would require a 250µs rise time,
L = 50µH
RSENSE = 0.02Ω
limiting the charging current to about 200mA.
800
LTC1149 Adjustable Applications
600 L = 25µH
When an output voltage other than 3.3V or 5V is required,
COUT (µF)

RSENSE = 0.02Ω
the LTC1149 adjustable version is used with an external
400
resistive divider from VOUT to VFB Pin 10. The regulated
L = 50µH
RSENSE = 0.05Ω voltage is determined:
200

0
0 1 2 3 4 5
)
VOUT = 1.25 1 + R2
R1 )
(VIN – VOUT) VOLTAGE (V)
1149 F04 In applications where VOUT is greater than the LTC1149
Figure 4. Minimum Suggested COUT internally regulated VCC voltage, RSENSE must be moved to

VIN

1N4148
+ 150µF
VIN 1N4148
50V
CAP PGATE IRF9Z34
0.068µF 100µH
+ VCC 0.047µF
1µF PDRIVE
VCC
1N5819 R2
NGATE IRFZ34 215k
LTC1149 1% + 150µF
16V VOUT LOAD
0V = NORMAL
SHDN2 VFB OS-CON
>2V = SHUTDOWN R1
100pF
25k
1%
SENSE +
ITH 1000pF
RSENSE
3300pF CT SENSE –
0.05Ω OUTPUT

( )
GNDS GROUND
CT
1k VOUT = 1.25 1 + R2 CONNECTION
200pF R1
1149 F05
VALUES SHOWN FOR VOUT = 12V

Figure 5. High Efficiency Step-Down Regulator with VOUT > VCC

11
LTC1149
LTC1149-3.3/LTC1149-5
U U W U
APPLICATIO S I FOR ATIO
the ground side of the output to prevent the absolute mode, IGATECHG = f (QN + QP). The typical gate charge
maximum voltage ratings of the sense pins from being for a 0.1Ω N-channel power MOSFET is 25nC, and for
exceeded. This is shown in Figure 5. When the current a P-channel about twice that value. This results in
sense comparator is operating at 0V common mode, the IGATECHG = 7.5mA in 100kHz continuous operation, for
off-time increases approximately 40%, requiring the use a 5% to 10% typical mid-current loss with VIN = 24V.
of a smaller timing capacitor CT. Note that the gate charge loss increases directly with
both input voltage and operating frequency. This is the
Efficiency Considerations
principal reason why the highest efficiency circuits
The percent efficiency of a switching regulator is equal to operate at moderate frequencies. Furthermore, it
the output power divided by the input power times 100%. argues against using larger MOSFETs than necessary
It is often useful to analyze individual losses to determine to control I2R losses, since overkill can cost efficiency
what is limiting the efficiency and which change would as well as money!
produce the most improvement. Percent efficiency can be
expressed as: 3. I2R losses are easily predicted from the DC resistances
of the MOSFET, inductor and current shunt. In continu-
%Efficiency = 100 – (L1 + L2 + L3 + ...) ous mode all of the output current flows through L and
where L1, L2, etc., are the individual losses as a percent- RSENSE, but is “chopped” between the P-channel and
age of input power. (For high efficiency circuits only small N-channel MOSFETs. If the two MOSFETs have
errors are incurred by expressing losses as a percentage approximately the same RDS(ON), then the resistance of
of output power.) one MOSFET can simply be summed with the resis-
tances of L and RSENSE to obtain I2R losses. For
Although all dissipative elements in the circuit produce example, if each RDS(ON) = 0.1Ω, RL = 0.15Ω and
losses, four main sources usually account for most of the RSENSE = 0.05Ω, then the total resistance is 0.3Ω. This
losses in LTC1149 series circuits: 1) LTC1149 DC supply results in losses ranging from 3% to 12% as the output
current, 2) MOSFET gate charge current, 3) I2R losses and current increases from 0.5A to 2A. I2R losses cause the
4) P-channel transition losses. efficiency to roll-off at high output currents.
1. The DC supply current is the current which flows into 4. Transition losses apply only to the P-channel MOSFET,
VIN Pin 2 less the gate charge current. For VIN = 12V the and only when operating at high input voltages (typi-
LTC1149 DC supply current is 0.6mA for no load, and cally 24V or greater). Transition losses can be esti-
increases proportionally with load up to 2mA after the mated from:
LTC1149 series has entered continuous mode.
Because the DC supply current is drawn from VIN, the Transition Loss ≈ 5(VIN)2 (IMAX)(CRSS)(f)
resulting loss increases with input voltage. For For example, if VIN = 48V, IMAX = 2A, CRSS = 300pF (a very
VIN = 24V, the DC bias losses are generally less than 3% large MOSFET) and f = 100kHz, the transition loss is 0.7W.
for load currents over 300mA. However, at very low A loss of this magnitude would not only kill efficiency but
load currents the DC bias current accounts for nearly all would probably require additional heat sinking for the
of the loss. MOSFET! See Design Example for further guidelines on
2. MOSFET gate charge current results from switching the how to select the P-channel MOSFET.
gate capacitance of the power MOSFETs. Each time a Other losses including CIN and COUT ESR dissipative
MOSFET gate is switched from low to high to low again, losses, Schottky conduction losses during dead-time, and
a packet of charge dQ moves from VIN to ground. The inductor core losses, generally account for less than 2%
resulting dQ/dt is a current out of VIN which is typically total additional loss.
much larger than the DC supply current. In continuous

12
 LTC1149
LTC1149-3.3/LTC1149-5
U U W U
APPLICATIO S I FOR ATIO
LTC1149 Package Dissipation The same calculations were repeated for a smaller device,
High input voltage applications in which large MOSFETs the Motorola MTD2955 (RDS(ON) = 0.3Ω) and a larger one,
are being driven at high frequencies may cause the maxi- the Harris RFP30P05 (RDS(ON) = 0.065Ω). The results are
mum junction temperature rating for the LTC1149 series summarized in the table.
to be exceeded. The LTC1149 supply current is dominated CONDITIONS P-CHANNEL MOSFET
by the gate charge supply current, which is given as a VIN = 24V, VOUT = 5V
function of operating frequency in the Typical Perfor- F = 100kHz, IOUT = 2.5A MTD2955 IRF9Z34 RFP30P05
mance Characteristics. The LTC1149 series junction tem- Est. I2R Loss (100°C) 550mW 270mW 120mW
perature can be estimated by using the equations given in Est. Transition Loss 110mW 145mW 290mW
Note 1 of the Electrical Characteristics. For example, the Est. Gate Charge Loss 60mW 85mW 240mW
LT1149CS is limited to less than 11mA from a 48V supply: Est. Total Loss 720mW 500mW 650mW

TJ = 70°C + (11mA)(48V)(110°C/W) For this set of conditions, the midsized P-channel MOSFET
= 128°C exceeds absolute maximum actually produces the lowest total losses at IMAX. The
To prevent the maximum junction temperature from being resulting efficiency differences will be even more pro-
exceeded, the Pin 2 supply current must be checked in nounced at lower output currents. Note that only the I2R
continuous mode when operating at the maximum VIN. and transition losses are dissipated in the MOSFET; the
gate charge supply current loss is dissipated by the
Design Example LTC1149 series.
As a design example, assume VIN = 24V, VOUT = 5V, Selection of the N-channel MOSFET is somewhat easier; it
IMAX = 2.5A and f = 100kHz. RSENSE, CT and L can need only be sized for the anticipated I2R losses at 100%
immediately be calculated: duty cycle (worst-case assumption for short circuit.) The
Siliconix Si9410, for example, has RDS(ON) = 0.03Ω Max
RSENSE = 100mV = 0.039Ω and QN = 30nC. This will produce an I2R loss of 250mW at
2.5

) )
100°C and a gate charge supply current loss of 75mW. As
(7.8)(10 –5) 5V with the P-channel device, the use of a larger MOSFET may
CT = 1– = 620pF
100kHz 24V actually result in lower midcurrent efficiency.
LMIN = (5.1)(105)(0.039Ω)(620pF)(5V) = 62µH CIN will require an RMS current rating of at least 1.25A at
temperature, and COUT will require an ESR of 0.04Ω for
Selection of the P-channel MOSFET involves doing calcu- optimum efficiency. The output capacitor ESR require-
lations for different sized MOSFETs to determine the ment can be fulfilled by a single OS-CON or by two or more
relative loss contributions. Taking an International Recti- surface mount tantalums in parallel.
fier IRF9Z34 for example, R DS(ON) = 0.14Ω Max,
QP = 35nC and CRSS = 200pF (VDS = VIN/2). These values Auxiliary Windings – Suppressing Burst Mode
can be used to estimate the I2R losses, transition losses Operation
and gate charge supply current losses: The LTC1149 synchronous switch removes the normal
Est. I2R Loss (TJ = 100°C) = limitation that power must be drawn from the inductor
(5V/24V)(2.5)2 (1 + 0.5)0.14Ω = 270mW primary winding in order to extract power from auxiliary
windings. With synchronous switching, auxiliary outputs
Est. Transition Loss = may be loaded without regard to the primary output load,
5(24V)2 (2.5A)(200pF)(100kHz) = 145mW providing that the loop remains in continuous mode
Est. Gate Charge Loss = operation.
(100kHz)(35nC)(24V) = 85mW Burst Mode operation can be suppressed at low output
currents with a simple external network which cancels the

13
LTC1149
LTC1149-3.3/LTC1149-5
U U W U
APPLICATIO S I FOR ATIO
25mV minimum current comparator threshold. This tech- circuitry. Turning on the N-channel MOSFET when this
nique is also useful for eliminating audible noise from fault is detected will then force the system fuse to blow.
certain types of inductors in high current (IOUT > 5A) The N-channel MOSFET needs to be sized so it will safely
applications when they are lightly loaded. handle this overcurrent condition. The typical delay from
An external offset is put in series with the SENSE – pin to pulling the CT Pin 6 high to when the NGATE Pin 13 goes
subtract from the built-in 25mV offset. An example of this high is 250ns. Under shutdown conditions, the N-channel
technique is shown in Figure 6. Two 100Ω resistors are is held off and pulling Pin 6 high will not cause the output
inserted in series with the leads from the sense resistor. to be crowbarred.
With the addition of R3, a current is generated through R1 A small N-channel FET can be used as an interface between
causing an offset of: the overvoltage detect circuitry and the LTC1149 as shown

) )
in Figure 7.
R1
VOFFSET = VOUT
R1 + R3
5
VCC
If VOFFSET > 25mV, the minimum threshold will be cancelled
CROWBAR VN2222LL LTC1149
and Burst Mode operation is prevented from occurring. 6
Since VOFFSET is constant, the maximum load current is CT

also decreased by the same offset. Thus, to get back to the ACTIVE WHEN CROWBAR = VIN
OFF WHEN CROWBAR = GROUND
same IMAX, the value of the sense resistor must be lower: 1149 F07

RSENSE ≈ 75mV Figure 7. Output Crowbar Interface

IMAX
To prevent noise spikes from erroneously tripping the Board Layout Checklist
current comparator, a 1000pF capacitor is needed across
When laying out the printed circuit board, the following
Pins 8 and 9.
checklist should be used to ensure proper operation of the
LTC1149 series. These items are also illustrated graphi-
RSENSE
L
cally in the layout diagram of Figure 8. Check the following
LTC1149
R2
+ in your layout:
COUT
9 100Ω
SENSE + 1. Are the signal and power grounds segregated? The
R1
8
1000pF
100Ω
LTC1149 signal ground Pin 11 must connect separately
SENSE – 1149 F06
to the (–) plate of COUT. The other ground Pins 12 and
R3 14 should return to the source of the N-channel MOSFET,
anode of the Schottky diode and (–) plate of CIN, which
Figure 6. Suppressing Burst Mode Operation should have as short lead lengths as possible.
2. Does the LTC1149 SENSE – Pin 8 connect to a point
Output Crowbar close to RSENSE and the (+) plate of COUT? In adjustable
An added feature to using an N-channel MOSFET as the applications, the resistive divider R1, R2 must be
synchronous switch is the ability to crowbar the output connected between the (+) plate of COUT and signal
with the same MOSFET. Pulling the timing capacitor Pin 6 ground.
above 1.5V when the output voltage is greater than the 3. Are the SENSE – and SENSE + leads routed together with
desired regulated value, will turn on the N-channel MOSFET. minimum PC trace spacing? The differential decou-
A fault condition which causes the output voltage to go pling capacitor between Pins 8 and 9 should be as close
above a maximum value can be detected by external as possible to the LTC1149. Up to 100Ω may be placed

14
 LTC1149
LTC1149-3.3/LTC1149-5
U U W U
APPLICATIO S I FOR ATIO
BOLD LINES INDICATE HIGH CURRENT PATHS
+

CIN
1N4148 1N4148

+
P-CHANNEL
VIN
0.068µF D1

1µF
+ N-CHANNEL
–
1 16
PGATE CAP
2 15
VIN SD2 SHUTDOWN
3 14
0.047µF VCC RGND
L
4 13
PDRIVE NGATE
5 12
VCC PGND
6 11
CT SGND –
7 10 100pF
VFB/ R1
ITH
SHDN1 COUT
CT 3300pF 8 9
+ VOUT
SENSE – SENSE +
1k R2 RSENSE
1000pF +
OUTPUT DIVIDER REQUIRED WITH
1149 F08
ADJUSTABLE VERSION ONLY

Figure 8. LTC1149 Series Layout Diagram (see Layout Checklist)

in series with each sense lead to help decouple Pins 8 correctly in both continuous and Burst Mode operation.
and 9. However, when these resistors are used, the The waveform to monitor is the voltage on the timing
capacitor should be no larger than 1000pF. capacitor Pin 6.
4. Does the (+) plate of CIN connect to the source of the In continuous mode (ILOAD > IBURST) the voltage on Pin 6
P-channel MOSFET as closely as possible? An addi- should be a sawtooth with a 0.9VP-P swing. This voltage
tional 0.1µF ceramic capacitor between VIN and power should never dip below 2V as shown in Figure 9a.
ground may be required in some applications. When load currents are low (ILOAD < IBURST) Burst Mode
5. Is the VCC decoupling capacitor connected closely operation should occur with the CT pin waveform periodi-
between Pin 5 of the LTC1149 and power ground? This cally falling to ground as shown in Figure 9b.
capacitor carries the MOSFET driver peak currents. If Pin 6 is observed falling to ground at high output
6. Is the SHDN1 Pin 10 (fixed output versions only) currents, it indicates poor decoupling or improper ground-
actively pulled to ground during normal operation? The ing. Refer to the Board Layout Checklist.
SHDN1 pin is high impedance and must not be allowed 3.3V
to float. In adjustable versions, Pin 10 is the feedback
pin and is very sensitive to pickup from the switch node. 0V
Care must be taken to isolate VFB from possible capaci- (a) CONTINUOUS MODE OPERATION

tive coupling of the inductor switch signal. 3.3V

Troubleshooting Hints 0V
(b) Burst Mode OPERATION
Since efficiency is critical to LTC1149 series applications, 1149 F09

it is very important to verify that the circuit is functioning Figure 9. CT Pin 6 Waveforms

15
LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S
VIN
8V TO 20V

1N4148 1N4148
+ 100µF
35V
IRFR9024

L* RSENSE**
1 16 68µH 0.1Ω
PGATE CAP VOUT
3.3V/1A
0.068µF 2 15
VIN SHDN2
0.047µF
3 14
VCC R-GND + 220µF
6.3V
4 13
P-DRIVE NGATE IRFR024 1N5818 AVX
5 LTC1149-3.3 12
VCC PGND
6 11
CT SGND
7 10 0V = NORMAL
+ ITH SHDN1
>2V = SHUTDOWN
1µF 390pF 3300pF 8 9
SENSE – SENSE +
1k 1000pF
1149 F10

*COILTRONICS CTX02-11932
**DALE WSC-1/2-0.1

Figure 10. High Efficiency 8V to 20V Input 3.3V/1A Output Regulator

VIN
8V TO 20V

1N4148 1N4148
+ 220µF
35V
IRF9Z34

L* RSENSE**
1 16 33µH 0.033Ω
PGATE CAP VOUT
3.3V/3A
0.068µF 2 15
VIN SHDN2
0.047µF
3 14
VCC RGND + 220µF
6.3V × 2
4 13
PDRIVE NGATE IRFZ34 1N5818 AVX
LTC1149-3.3
5 12
VCC PGND
6 11
CT SGND
7 10
+ ITH SHDN1 SHUTDOWN
3.3µF 470pF 3300pF 8 9 100Ω
– +
SENSE SENSE
1k 1000pF 100Ω
1149 F11

*COILTRONICS CTX33-4-KM
**KRL SL-1-C1-0R033J

Figure 11. High Efficiency 8V to 20V Input 3.3V/3A Output Regulator

16
 LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S
VIN
5.5V TO 25V

1N4148 1N4148
+ 220µF
35V
Si9435DY

L* RSENSE**
1 16 33µH 0.05Ω
PGATE CAP VOUT
5V/2A
0.068µF 2 15
VIN SHDN2
0.047µF
3 14
VCC RGND + 220µF
10V × 2
4 13
PDRIVE NGATE Si9410DY 1N5818 AVX
5 LTC1149-5 12
VCC PGND
6 11
CT S-GND
7 10
+ ITH SHDN1 SHUTDOWN
1µF 220pF 3300pF 8 9
– +
SENSE SENSE
1k 1000pF
1149 F12

*COILTRONICS CTX33-4 Kool Mµ

**KRL SL-1-C1-0R050J

Figure 12. Ultra Wide Input Range (5.5V to 25V) High Efficiency 5V Regulator

VIN
8V TO 16V

1N4148 1N4148
+ 100µF
25V
Si9430DY

L* RSENSE**
1 16 22µH 0.05Ω
PGATE CAP VOUT
5V/2A
0.068µF 2 15
VIN SHDN2
0.047µF
3 14
VCC RGND + 220µF
4 10V
13
PDRIVE NGATE Si9410DY 1N5818 AVX
5 LTC1149-5 12
VCC PGND
6 11
CT SGND
7 10
+ ITH SHDN1 SHUTDOWN
1µF 180pF 3300pF 8 9
SENSE – SENSE +
1k 1000pF
1149 F13

*DALE LPE-6562-220MB
**KRL SL-1-C1-0R050J

Figure 13. 250kHz High Efficiency 12V Input 5V/2A Output Regulator

17
LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S

VIN
48V
1N4148 1N4148
+ 100µF
0.1µF
100V
MTD2955

L* RSENSE**
1 16 68µH 0.04Ω
PGATE CAP VOUT
5V/2.5A
0.068µF 2 15
VIN SHDN2
0.047µF
3 14
VCC RGND + 220µF
10V
4 13
PDRIVE NGATE IRFZ34 MBR380 OS-CON
5 LTC1149-5 12
VCC PGND
6 11
CT SGND
7 10
+ ITH SHDN1 SHUTDOWN
3.3µF 620pF 3300pF 8 9 100Ω
SENSE – SENSE +
1k 1000pF 100Ω
1149 F14

*HURRICANE LAB HL-KI168M

**IRC LR2512-01-R040-G

Figure 14. High Efficiency 48V Input 5V/2.5A Output Regulator

VIN
8V TO 20V

1N4148 1N4148
+ 100µF
35V
RFD15P05SM

L* RSENSE**
1 16 50µH 0.05Ω VOUT
PGATE CAP 3.3V/2A
0.068µF 2 15 OR 5V/2A
VIN SHDN2 SHUTDOWN
0.047µF
3 14
+ 220µF
VCC RGND 10V × 2
AVX
4 13
PDRIVE NGATE RFD14N05SM 1N5818
5 LTC1149 12
VCC PGND 0V: VOUT = 3.3V
VN2222LL
6 11 5V: VOUT = 5V
CT SGND
100pF R1A R1B R2
7 10 33k 43k 56k
+ ITH VFB
1% 1% 1%
1µF 390pF 3300pF 8 9
SENSE – SENSE +
1k 1000pF
1149 F15

*COILTRONICS CTX50-2-MP
**IRC LR2010-01-R050-G

Figure 15. Logic Selectable 5V/2A or 3.3V/2A High Efficiency Regulator

18
 LTC1149
LTC1149-3.3/LTC1149-5
U
TYPICAL APPLICATIO S
VIN
12V TO 36V
1N4148

+ 1000µF
10k 220Ω
63V
2N3906

0.1µF
470Ω
VN2222LL
2N2222
1 16
PGATE CAP
MTP30N06EL L* RSENSE**
2 15 50µH
VIN SHDM2 MUR110 0.02Ω
VOUT
3 14 5V/5A
0.1µF VCC RGND
4 13 + 220µF
PDRIVE NGATE IRFZ44 MBR380 10V × 2
5 LTC1149-5 12 OS-CON
VCC PGND
6 11 0V = NORMAL
CT SGND
>2V = SHUTDOWN
7 10
+ ITH SHDN1
3.3µF 820pF 3300pF 8 9 100Ω
SENSE – SENSE +
1k 1000pF 100Ω
1149 F16

*COILTRONICS CTX50-5-52 SEE APPLICATIONS INFORMATION TO SUPPRESS

**DALE LVR-3-0.02 Burst ModeTM OPERATION AT LOW CURRENTS

Figure 16. 25W High Efficiency Regulator Using N-Channel MOSFET Switches

U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.

N Package
16-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)

0.770*
(19.558)
0.300 – 0.325 0.130 ± 0.005 0.045 – 0.065 MAX
(7.620 – 8.255) (3.302 ± 0.127) (1.143 – 1.651)
16 15 14 13 12 11 10 9

0.020
(0.508) 0.255 ± 0.015*
MIN 0.065 (6.477 ± 0.381)
0.009 – 0.015
(1.651)
(0.229 – 0.381) TYP
+0.035 1 2 3 4 5 6 7 8
0.325 –0.015

( )
0.125 0.100 ± 0.010 0.018 ± 0.003
+0.889 (3.175) (2.540 ± 0.254) (0.457 ± 0.076)
8.255 N16 1197
–0.381 MIN
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

19
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1149
LTC1149-3.3/LTC1149-5
U
PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted.

S Package
16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 – 0.394*
(9.804 – 10.008)
0.010 – 0.020 16 15 14 13 12 11 10 9
× 45° 0.053 – 0.069 0.004 – 0.010
(0.254 – 0.508)
(1.346 – 1.752) (0.101 – 0.254)
0.008 – 0.010
(0.203 – 0.254) 0° – 8° TYP

0.228 – 0.244 0.150 – 0.157**

(5.791 – 6.197) (3.810 – 3.988)
0.014 – 0.019 0.050
0.016 – 0.050
(0.355 – 0.483) (1.270)
0.406 – 1.270 TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
S16 0695
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD 1 2 3 4 5 6 7 8
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

U
TYPICAL APPLICATION VIN
20V TO 30V

1N4148 1N4148
+ 220µF
50V
MTP23P06

L*
1 16 100µH
PGATE CAP VOUT
12V/3A
0.068µF 2 15
VIN SHDN2 SHUTDOWN
0.047µF
3 14 R2 + 150µF
VCC RGND 172k 16V × 2
4 13 1% OS-CON
PDRIVE NGATE MTP36N06E MBR160
5 LTC1149 12
VCC PGND
6 11
CT SGND R1
100pF 20k RSENSE**
7 10 0.033Ω
+ ITH VFB 1%
3.3µF 300pF 3300pF 8 9 100Ω
SENSE – SENSE +
OUTPUT
1k 1000pF GROUND
100Ω
CONNECTION
1149 F17
*HURRICANE LAB HL-EK210M
**KRL SL-1-C1-0R033J

Figure 17. High Efficiency 24V Input 12V/3A Output Regulator

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1148HV High Efficiency, Synchronous Step-Down Switching Regulator 4V < VIN < 20V
LTC1159 High Efficiency, Synchronous Step-Down Switching Regulator 4V < VIN < 40V, ISHUTDOWN = 20µA
LTC1435A High Efficiency, Low Noise, Synchronous Switching Regulator 3.5V < VIN < 36V, N-Channel Driver
LTC1438 Dual, Low Noise, Synchronous Switching Regulator 3.5V < VIN < 36V, N-Channel Driver

1149fa LT/TP 0898 REV A 2K • PRINTED IN USA

Linear Technology Corporation
20 1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com  LINEAR TECHNOLOGY CORPORATION 1993