LT1765EFE#PBF LT1765EFE-5#PBF LT1765ES8#PBF LT1765EFE-3.

3#PBF
 LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
Monolithic 3A, 1.25MHz
Step-Down Switching Regulator

FEATURES DESCRIPTION
n 3A Switch in a Thermally Enhanced 16-Lead The LT®1765 is a 1.25MHz monolithic buck switching
TSSOP or 8-Lead SO Package regulator. A high efficiency 3A, 0.09Ω switch is included
n Constant 1.25MHz Switching Frequency on the die together with all the control circuitry required
n Wide Operating Voltage Range: 3V to 25V to construct a high frequency, current mode switching
n High Efficiency 0.09Ω Switch regulator. Current mode control provides fast transient
n 1.2V Feedback Reference Voltage response and excellent loop stability.
n Uses Low Profile Surface Mount Components
n
New design techniques achieve high efficiency at high
Low Shutdown Current: 15μA
n
switching frequencies over a wide operating voltage
Synchronizable to 2MHz
n
range. A low dropout internal regulator maintains con-
Current Mode Loop Control
n
sistent performance over a wide range of inputs from
Constant Maximum Switch Current Rating at
24V systems to Li-Ion batteries. An operating supply
All Duty Cycles*
n
current of 1mA improves efficiency, especially at lower
Available in 8-Lead SO and 16-Lead Thermally
output currents. Shutdown reduces quiescent current to
Enhanced TSSOP Packages
15μA. Maximum switch current remains constant at all
duty cycles. Synchronization allows an external logic level
APPLICATIONS signal to increase the internal oscillator into the range of
1.6MHz to 2MHz.
n DSL Modems
n Portable Computers Full cycle-by-cycle current control and thermal shutdown
n Regulated Wall Adapters are provided. High frequency operation allows the reduc-
n Battery-Powered Systems tion of input and output filtering components and permits
n Distributed Power the use of chip inductors.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
*Patent Pending

TYPICAL APPLICATION
5V to 3.3V Step-Down Converter Efficiency vs Load Current
CMDSH-3 90
VIN = 10V
VOUT = 5V
0.18μF
85
INPUT BOOST 1.5μH OUTPUT
EFFICIENCY (%)

5V VIN VSW 3.3V

2.2μF 2.5A
LT1765-3.3 80
CERAMIC
OFF ON SHDN FB
SYNC GND VC
4.7μF
2.2nF UPS120 CERAMIC 75

1765 TA01
70
0 0.5 1.0 1.5 2.0
SWITCH CURRENT (A)
1765 • TAO1a

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LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
ABSOLUTE MAXIMUM RATINGS (Note 1)

Input Voltage ........................................................... 25V SYNC Pin Current ................................................... 1mA

BOOST Pin Above SW ............................................. 20V Operating Junction Temperature Range
Max BOOST Pin Voltage ............................................35V (Note 2)................................................. –40°C to 125°C
SHDN Pin ................................................................. 25V Storage Temperature Range ................. –65°C to 150°C
FB Pin Current......................................................... 1mA Lead Temperature (Soldering, 10 sec) ................ 300°C

PIN CONFIGURATION
TOP VIEW

GND 1 16 GND
TOP VIEW
BOOST 2 15 NC
VIN 3 14 SYNC BOOST 1 8 SYNC
VIN 4 13 VC VIN 2 7 VC
17
SW 5 12 FB SW 3 6 FB
SW 6 11 SHDN GND 4 5 SHDN
NC 7 10 NC
S8 PACKAGE
GND 8 9 GND 8-LEAD PLASTIC SO
TJMAX = 125°C, θJA = 90°C/W, θJC(PIN 4) = 30°C/W
FE PACKAGE
GROUND PIN CONNECTED TO LARGE COPPER AREA
16-LEAD PLASTIC TSSOP
θJA = 45°C/W, θJC(PAD) = 10°C/W
EXPOSED PAD (PIN 17) SOLDERED TO LARGE COPPER PLANE

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1765EFE#PBF LT1765EFE#TRPBF 1765EFE 16-Lead Plastic TSSOP –40°C to 125°C
LT1765EFE-1.8#PBF LT1765EFE-1.8#TRPBF 1765EFE-1.8 16-Lead Plastic TSSOP –40°C to 125°C
LT1765EFE-2.5#PBF LT1765EFE-2.5#TRPBF 1765EFE-2.5 16-Lead Plastic TSSOP –40°C to 125°C
LT1765EFE-3.3#PBF LT1765EFE-3.3#TRPBF 1765EFE-3.3 16-Lead Plastic TSSOP –40°C to 125°C
LT1765EFE-5#PBF LT1765EFE-5#TRPBF 1765EFE-5 16-Lead Plastic TSSOP –40°C to 125°C
LT1765ES8#PBF LT1765ES8#TRPBF 1765 8-Lead Plastic SO –40°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LT1765EFE LT1765EFE#TR 1765EFE 16-Lead Plastic TSSOP –40°C to 125°C
LT1765EFE-1.8 LT1765EFE-1.8#TR 1765EFE-1.8 16-Lead Plastic TSSOP –40°C to 125°C
LT1765EFE-2.5 LT1765EFE-2.5#TR 1765EFE-2.5 16-Lead Plastic TSSOP –40°C to 125°C
LT1765EFE-3.3 LT1765EFE-3.3#TR 1765EFE-3.3 16-Lead Plastic TSSOP –40°C to 125°C
LT1765EFE-5 LT1765EFE-5#TR 1765EFE-5 16-Lead Plastic TSSOP –40°C to 125°C
LT1765ES8 LT1765ES8#TR 1765 8-Lead Plastic SO –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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 LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VIN = 15V, VC = 0.8V, Boost = VIN + 5V, SHDN, SYNC and switch open unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Maximum Switch Current Limit 3 4 6 A
Oscillator Frequency 3.3V < VIN < 25V l 1.1 1.25 1.6 MHz
Switch On Voltage Drop I = 3A l 270 430 mV
VIN Undervoltage Lockout (Note 3) l 2.47 2.6 2.73 V
VIN Supply Current l 1 1.3 mA
Shutdown Supply Current VSHDN = 0V, VIN = 25V, VSW = 0V 15 35 μA
l 55 μA
Feedback Voltage 3V < VIN < 25V, 0.4V < VC < 0.9V LT1765 (Adj) 1.182 1.2 1.218 V
(Note 3) l 1.176 1.224 V
LT1765-1.8 l 1.764 1.8 1.836 V
LT1765-2.5 l 2.45 2.5 2.55 V
LT1765-3.3 l 3.234 3.3 3.366 V
LT1765-5 l 4.9 5 5.1 V
FB Input Current LT1765 (Adj) l –0.25 –0.5 μA
FB Input Resistance LT1765-1.8 l 10.5 15 21 kΩ
LT1765-2.5 l 14.7 21 30 kΩ
LT1765-3.3 l 19 27.5 39 kΩ
LT1765-5 l 29 42 60 kΩ
FB Error Amp Voltage Gain 0.4V < VC < 0.9V 150 350
FB Error Amp Transconductance ΔIVC = ±10μA l 500 850 1300 μMho
VC Pin Source Current VFB = VNOM – 17% l 80 120 160 μA
VC Pin Sink Current VFB = VNOM + 17% l 70 110 180 μA
VC Pin to Switch Current Transconductance 5 A/V
VC Pin Minimum Switching Threshold Duty Cycle = 0% 0.4 V
VC Pin 3A ISW Threshold 0.9 V
Maximum Switch Duty Cycle VC = 1.2V, ISW = 800mA, VIN = 6V 85 90 %
l 80 %
Minimum Boost Voltage Above Switch ISW = 3A l 1.8 2.7 V
Boost Current ISW = 1A (Note 4) l 20 30 mA
ISW = 3A (Note 4) l 70 140 mA
SHDN Threshold Voltage l 1.27 1.33 1.40 V
SHDN Threshold Current Hysteresis l 4 7 10 μA
SHDN Input Current (Shutting Down) SHDN = 60mV Above Threshold l –7 –10 –13 μA
SYNC Threshold Voltage 1.5 2.2 V
SYNC Input Frequency 1.6 2 MHz
SYNC Pin Resistance ISYNC = 1mA 20 kΩ
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: Minimum input voltage is defined as the voltage where the internal
may cause permanent damage to the device. Exposure to any Absolute regulator enters lockout. Actual minimum input voltage to maintain a
Maximum Rating condition for extended periods may affect device regulated output will depend on output voltage and load current. See
reliability and lifetime. Applications Information.
Note 2: The LT1765E is guaranteed to meet performance specifications Note 4: Current flows into the BOOST pin only during the on period of the
from 0°C to 125°C. Specifications over the –40°C to 125°C operating switch cycle.
junction temperature range are assured by design, characterization and
correlation with statistical process controls.
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LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
TYPICAL PERFORMANCE CHARACTERISTICS

FB vs Temperature (Adj) Switch On Voltage Drop

1.220 350

1.215 TA = 125°C
300

1.210

SWITCH VOLTAGE (mV)

250
FB VOLTAGE (V)

1.205
200 TA = –40°C
1.200
150 TA = 25°C
1.195
100
1.190

1.185 50

1.180 0
–50 –25 0 25 50 75 100 125 0 1 2 3
TEMPERATURE (°C) SWITCH CURRENT (A)
1765 G01 1765 G02

Oscillator Frequency SHDN Threshold vs Temperature

1.50 1.40

1.45
1.38
1.40
SHDN THRESHOLD (V)
FREQUENCY (MHz)

1.35 1.36
1.30

1.25 1.34

1.20
1.32
1.15

1.10 1.30
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
1765 G03 1765 G04

SHDN Supply Current vs VIN SHDN IP Current vs Temperature

7 7
SHDN = 0V SHDN = 0V
6 6

5 5
VIN CURRENT (μA)
VIN CURRENT (μA)

4 4

3 3

2 2

1 1

0 0
0 5 10 15 20 25 30 0 5 10 15 20 25 30
VIN (V) VIN (V)
1765 G05 1765 G05

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 LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
TYPICAL PERFORMANCE CHARACTERISTICS
Minimum Input Voltage for
2.5V Out SHDN Supply Current
3.5 300
VIN = 15V
250
3.3
INPUT VOLTAGE (V)

VIN CURRENT (μA)

200
3.1
150
2.9
100

2.7
50

2.5 0
0.001 0.01 0.1 1 0 0.2 0.4 0.6 0.8 1 1.2 1.4
LOAD CURRENT (A) SHUTDOWN VOLTAGE (V)
1765 G07 1765 G08

Input Supply Current Current Limit Foldback

1200 4 40

1000
SWITCH PEAK CURRENT (A)

FB INPUT CURRENT (μA)

UNDERVOLTAGE 3 30
VIN CURRENT (μA)

800 LOCKOUT
SWITCH CURRENT

600 2 20

400
1 10
200 FB CURRENT

0 0 0
0 5 10 15 20 25 30 0 0.2 0.4 0.6 0.8 1 1.2
INPUT VOLTAGE (V) FEEDBACK VOLTAGE (V)
1765 G09 1765 G10

Maximum Load Current, Maximum Load Current,

VOUT = 5V VOUT = 2.5V
3.0 3.0

2.8 L = 4.7μH
L = 4.7μH 2.8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)

2.6
L = 2.2μH
2.6
2.4 L = 2.2μH
L = 1.5μH
2.4
2.2
L = 1.5μH

2.0 2.2
0 5 10 15 20 25 0 5 10 15 20 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
1765 G11 1765 G12

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LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
PIN FUNCTIONS
FB: The feedback pin is used to set output voltage using VSW: The switch pin is the emitter of the on-chip power
an external voltage divider (adjustable version) that gener- NPN switch. This pin is driven up to the input pin voltage
ates 1.2V at the pin when connected to the desired output during switch on time. Inductor current drives the switch
voltage. The fixed voltage 1.8V, 2.5V, 3.3V and 5V versions pin negative during switch off time. Negative voltage must
have the divider network included internally and the FB pin be clamped with an external catch diode with a VBR <0.8V.
is connected directly to the output. If required, the current Both VSW pins of the TSSOP package must be shorted
limit can be reduced during start up or short-circuit when together on the PC board.
the FB pin is below 0.5V (see the Current Limit Foldback SYNC: The sync pin is used to synchronize the internal
graph in the Typical Performance Characteristics section). oscillator to an external signal. It is directly logic compat-
An impedance of less than 5kΩ on the adjustable version ible and can be driven with any signal between 20% and
at the FB pin is needed for this feature to operate. 80% duty cycle. The synchronizing range is from 1.6MHz
BOOST: The BOOST pin is used to provide a drive voltage, to 2MHz. See Synchronization section in Applications
higher than the input voltage, to the internal bipolar NPN Information for details. When not in use, this pin should
power switch. be grounded.
VIN: This is the collector of the on-chip power NPN switch. SHDN: The shutdown pin is used to turn off the regula-
This pin powers the internal circuitry and internal regulator. tor and to reduce input drain current to a few microam-
At NPN switch on and off, high di/dt edges occur on this peres. The 1.33V threshold can function as an accurate
pin. Keep the external bypass capacitor and catch diode undervoltage lockout (UVLO), preventing the regulator
close to this pin. All trace inductance on this path will from operating until the input voltage has reached a pre-
create a voltage spike at switch off, adding to the VCE volt- determined level. Float or pull high to put the regulator in
age across the internal NPN. Both VIN pins of the TSSOP the operating mode.
package must be shorted together on the PC board.
VC: The VC pin is the output of the error amplifier and the
GND: The GND pin acts as the reference for the regulated input of the peak switch current comparator. It is normally
output, so load regulation will suffer if the “ground” end of used for frequency compensation, but can do double duty
the load is not at the same voltage as the GND pin of the as a current clamp or control loop override. This pin sits
IC. This condition will occur when load current or other at about 0.4V for very light loads and 0.9V at maximum
currents flow through metal paths between the GND pin load. It can be driven to ground to shut off the output.
and the load ground point. Keep the ground path short
between the GND pin and the load and use a ground plane
when possible. Keep the path between the input bypass
and the GND pin short. The exposed GND pad and/or GND
pins of the package are directly attached to the internal
tab. These pins/pad should be attached to a large copper
area to reduce thermal resistance.

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 LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
BLOCK DIAGRAM
The LT1765 is a constant frequency, current mode buck resonant frequency of the inductor and output capacitor,
converter. This means that there is an internal clock and then an abrupt 180° shift will occur. The current fed system
two feedback loops that control the duty cycle of the power will have 90° phase shift at a much lower frequency, but
switch. In addition to the normal error amplifier, there is a will not have the additional 90° shift until well beyond
current sense amplifier that monitors switch current on a the LC resonant frequency. This makes it much easier to
cycle-by-cycle basis. A switch cycle starts with an oscillator frequency compensate the feedback loop and also gives
pulse which sets the RS flip-flop to turn the switch on. When much quicker transient response.
switch current reaches a level set by the inverting input of
High switch efficiency is attained by using the BOOST pin
the comparator, the flip-flop is reset and the switch turns
to provide a voltage to the switch driver which is higher
off. Output voltage control is obtained by using the output
than the input voltage, allowing the switch to be saturated.
of the error amplifier to set the switch current trip point.
This boosted voltage is generated with an external capacitor
This technique means that the error amplifier commands
and diode. A comparator connected to the shutdown pin
current to be delivered to the output rather than voltage.
disables the internal regulator, reducing supply current.
A voltage fed system will have low phase shift up to the

0.005Ω
INPUT

+ –
CURRENT
2.5V BIAS INTERNAL SENSE
REGULATOR VCC AMPLIFIER
VOLTAGE GAIN = 40

SLOPE COMP ∑ BOOST

0.4V

1.25MHz
SYNC S Q1
OSCILLATOR CURRENT RS DRIVER
POWER
COMPARATOR FLIP-FLOP CIRCUITRY
SWITCH
+ R

SHUTDOWN – VSW
PARASITIC DIODES
COMPARATOR
7μA DO NOT FORWARD BIAS

+ –
–
FB
1.33V
+
ERROR
VC AMPLIFIER
INTERNAL 1.2V
SHDN gm = 850μMho
VCC
3μA GND
1765 F01

Figure 1. Block Diagram

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LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
FB RESISTOR NETWORK rating and turn-on surge problems. Y5V or similar type
ceramics can be used since the absolute value of capaci-
If an output voltage of 1.8V, 2.5V, 3.3V or 5V is required,
tance is less important and has no significant effect on
the respective fixed option part, -1.8, -2.5, -3.3 or -5,
loop stability. If operation is required close to the minimum
should be used. The FB pin is tied directly to the output;
input required by the output or the LT1765, a larger value
the necessary resistive divider is already included on
may be required. This is to prevent excessive ripple caus-
the part. For other voltage outputs, the adjustable part
ing dips below the minimum operating voltage resulting
should be used and an external resistor divider added.
in erratic operation.
The suggested resistor (R2) from FB to ground is 10k.
This reduces the contribution of FB input bias current to If tantalum capacitors are used, values in the 22μF to 470μF
output voltage to less than 0.25%. The formula for the range are generally needed to minimize ESR and meet
resistor (R1) from VOUT to FB is: ripple current and surge ratings. Care should be taken to
ensure the ripple and surge ratings are not exceeded. The
R2( VOUT – 1.2)
R1= AVX TPS and Kemet T495 series tantalum capacitors are
1.2 – R2(0.25μA) surge rated. AVX recommends derating capacitor operating
voltage by 2:1 for high surge applications.
LT1765 (ADJ) VSW

ERROR
OUTPUT OUTPUT CAPACITOR
AMPLIFIER
+ 1.2V Unlike the input capacitor, RMS ripple current in the output
FB
R1 capacitor is normally low enough that ripple current rating
+
– is not an issue. The current waveform is triangular, with
R2 an RMS value given by:
0.29 ( VOUT ) ( VIN − VOUT )
10k

IRIPPLE(RMS) =
1765 F02

VC GND
(L )( f )( VIN)
Figure 2. Feedback Network
The LT1765 will operate with both ceramic and tantalum
INPUT CAPACITOR output capacitors. Ceramic capacitors are generally cho-
sen for their small size, very low ESR (effective series
Step-down regulators draw current from the input supply
resistance), and good high frequency operation. Ceramic
in pulses. The rise and fall times of these pulses are very
output capacitors in the 1μF to 10μF range, X7R or X5R
fast. The input capacitor is required to reduce the voltage
type are recommended.
ripple at the input of LT1765 and to force the switching
current into a tight local loop, thereby minimizing EMI. Tantalum capacitors are usually chosen for their bulk
The RMS ripple current can be calculated from: capacitance properties, useful in high transient load ap-
plications. ESR rather than absolute value defines output
IRIPPLE(RMS) = IOUT VOUT ( VIN − VOUT ) / VIN2 ripple at 1.25MHz. Typical LT1765 applications require a
tantalum capacitor with less than 0.3Ω ESR at 22μF to
Ceramic capacitors are ideal for input bypassing. At higher 500μF, see Table 2. This ESR provides a useful zero in the
switching frequency, the energy storage requirement of frequency response. Ceramic output capacitors with low
the input capacitor is reduced so values in the range of ESR usually require a larger VC capacitor or an additional
1μF to 4.7μF are suitable for most applications. Their high series R to compensate for this.
frequency capacitive nature removes most ripple current

1765fd

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 LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
Table 2. Surface Mount Solid Tantalum Capacitor ESR IOUT (MAX) = ( VOUT )( VIN – VOUT )
and Ripple Current IP –
E Case Size ESR (Max, Ω) Ripple Current (A) Continuous Mode 2(L)( f)( VIN)
AVX TPS, Sprague 593D 0.1 to 0.3 0.7 to 1.1
AVX TAJ 0.7 to 0.9 0.4
For VIN = 8V, VOUT = 5V and L = 3.3μH,
D Case Size
IOUT(MAX ) = 3 −
( 5) ( 8 − 5)
AVX TPS, Sprague 593D
C Case Size
0.1 to 0.3 0.7 to 1.1
( )(
2 3.3 • 10 − 6 1.25 • 106 (8 ) )
AVX TPS 0.2 (typ) 0.5 (typ) = 3 − 0.23 = 2.77 A
Figure 3 shows a comparison of output ripple for a ceramic Note that the worst case (minimum output current avail-
and tantalum capacitor at 200mA ripple current. able) condition is at the maximum input voltage. For the
same circuit at 15V, maximum output current would be
only 2.6A.
VOUT USING 47μF, 0.1Ω
TANTALUM CAPACITOR
(10mV/DIV) Inductor Selection
VOUT USING 2.2μF The output inductor should have a saturation current rating
CERAMIC CAPACITOR
(10mV/DIV)
greater than the peak inductor current set by the current
comparator of the LT1765. The peak inductor current will
VSW
(5V/DIV) depend on the output current, input and output voltages
and the inductor value:
0.2μs/DIV
1765 F03
VOUT ( VIN − VOUT )
IPEAK = IOUT +
Figure 3. Output Ripple Voltage Waveform 2 (L )( f ) ( VIN)

INDUCTOR CHOICE AND MAXIMUM OUTPUT VIN = Maximum input voltage

CURRENT f = Switching frequency, 1.25MHz

Maximum output current for an LT1765 buck converter is If an inductor with a peak current lower than the maximum
equal to the maximum switch rating (IP) minus one half switch current of the LT1765 is chosen a soft-start circuit
peak to peak inductor ripple current. The LT1765 main- in Figure 10 should be used. Also, short-circuit conditions
tains a constant switch current rating at all duty cycles. should not be allowed because the inductor may saturate
(Patent Pending) resulting in excessive power dissipation.

For most applications, the output inductor will be in the Also, consideration should be given to the resistance
1μH to 10μH range. Lower values are chosen to reduce of the inductor. Inductor conduction loses are directly
the physical size of the inductor, higher values allow higher proportional to the DC resistance of inductor. Sometime,
output currents due to reduced peak to peak ripple current. the manufacturers will also provide maximum current
The following formula gives maximum output current for rating based on the allowable losses in the inductor. Care
continuous mode operation, implying that the peak to peak should be taken, however. At high input voltages and low
ripple (2x the term on the right) is less than the maximum DCR, excessive switch current could flow during shorted
switch current. output condition.
Suitable inductors are available from Coilcraft, Coiltronics,
Dale, Sumida, Toko, Murata, Panasonic and other
manufacturers.
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LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
Table 3 The boost diode can be connected to the input, although,
VALUE IRMS DCR HEIGHT care must be taken to prevent the 2x VIN boost voltage from
PART NUMBER (μH) (Amps) (Ω) (mm) exceeding the BOOST pin absolute maximum rating. The
Coiltcraft additional voltage across the switch driver also increases
DO1608C-222 2.2 2.4 0.07 2.9 power loss, reducing efficiency. If available, an independent
Sumida supply can be used with a local bypass capacitor.
CDRH3D16-1R5 1.5 1.6 0.043 1.8 A 0.18μF boost capacitor is recommended for most ap-
CDRH4D18-1R0 1.0 1.7 0.035 2.0 plications. Almost any type of film or ceramic capacitor
CDC5D23-2R2 2.2 2.2 0.03 2.5 is suitable, but the ESR should be <1Ω to ensure it can
CR43-1R4 1.4 2.5 0.056 3.5 be fully recharged during the off time of the switch. The
CDRH5D28-2R6 2.6 2.6 0.013 3.0 capacitor value is derived from worst-case conditions of
Toko 700ns on-time, 90mA boost current, and 0.7V discharge
(D62F)847FY-2R4M 2.4 2.5 0.037 2.7 ripple. This value is then guard banded by 2x for secondary
(D73LF)817FY-2R2M 2.2 2.7 0.03 3.0 factors such as capacitor tolerance, ESR and temperature
effects. The boost capacitor value could be reduced under
CATCH DIODE less demanding conditions, but this will not improve cir-
cuit operation or efficiency. Under low input voltage and
The diode D1 conducts current only during switch off low load conditions, a higher value capacitor will reduce
time. Peak reverse voltage is equal to regulator input discharge ripple and improve start up operation.
voltage. Average forward current in normal operation can
be calculated from: SHUTDOWN AND UNDERVOLTAGE LOCKOUT

ID ( AVG) =
(
IOUT VIN − VOUT ) Figure 4 shows how to add undervoltage lockout (UVLO)
to the LT1765. Typically, UVLO is used in situations where
VIN
the input supply is current limited, or has a relatively high
The only reason to consider a larger than 3A diode is the source resistance. A switching regulator draws constant
worst-case condition of a high input voltage and shorted power from the source, so source current increases as
output. With a shorted condition, diode current will increase to source voltage drops. This looks like a negative resistance
a typical value of 4A, determined by peak switch current limit load to the source and can cause the source to current limit
of the LT1765. A higher forward voltage will also limit switch or latch low under low source voltage conditions. UVLO
current. This is safe for short periods of time, but it would be prevents the regulator from operating at source voltages
prudent to check with the diode manufacturer if continuous where these problems might occur.
operation under these conditions must be tolerated.

BOOST PIN LT1765

7μA VSW
For most applications, the boost components are a 0.18μF INPUT IN

capacitor and a CMDSH-3 diode. The anode is typically R1 3μA

1.33V
VCC
connected to the regulated output voltage to generate a
voltage approximately VOUT above VIN to drive the output SHDN
+
OUTPUT

stage. The output driver requires at least 2.7V of headroom C1 R2

GND
throughout the on period to keep the switch fully saturated.
However, the output stage discharges the boost capacitor 1765 F04

during this on time. If the output voltage is less than 3.3V, Figure 4. Undervoltage Lockout
it is recommended that an alternate boost supply is used.
1765fd

10
 LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
An internal comparator will force the part into shutdown threshold with a duty cycle between 20% and 80%. The
below the minimum VIN of 2.6V. This feature can be used input can be driven directly from a logic level output. The
to prevent excessive discharge of battery-operated sys- synchronizing range is equal to initial operating frequency
tems. If an adjustable UVLO threshold is required, the up to 2MHz. This means that minimum practical sync
shutdown pin can be used. The threshold voltage of the frequency is equal to the worst-case high self-oscillating
shutdown pin comparator is 1.33V. A 3μA internal current frequency (1.6MHz), not the typical operating frequency
source defaults the open pin condition to be operating (see of 1.25MHz. Caution should be used when synchronizing
Typical Performance Graphs). Current hysteresis is added above 1.8MHz because at higher sync frequencies the
above the SHDN threshold. This can be used to set voltage amplitude of the internal slope compensation used to
hysteresis of the UVLO using the following: prevent subharmonic switching is reduced. This type of
VH − VL subharmonic switching only occurs at input voltages less
R1= than twice output voltage. Higher inductor values will tend
7μA to eliminate this problem. See Frequency Compensation
1.33V section for a discussion of an entirely different cause of
R2 =
( VH − 1.33V ) + 3μA subharmonic switching before assuming that the cause is
R1 insufficient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
VH – Turn-on threshold
LAYOUT CONSIDERATIONS
VL – Turn-off threshold
As with all high frequency switchers, when considering
Example: switching should not start until the input is above
layout, care must be taken in order to achieve optimal
4.75V and is to stop if the input falls below 3.75V.
electrical, thermal and noise performance. For maximum
VH = 4.75V efficiency, switch rise and fall times are typically in the
VL = 3.75V nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
4.75V − 3.75V in Figure 5, must be kept as short as possible. Shortening
R1 = = 143k
7μA this path will also reduce the parasitic trace inductance
1.33V of approximately 25nH/inch. At switch off, this parasitic
R2 = = 49.4k
(4.75V − 1.33V) + 3μA inductance produces a flyback spike across the LT1765
switch. When operating at higher currents and input volt-
143k
ages, with poor layout, this spike can generate voltages
Keep the connections from the resistors to the SHDN across the LT1765 that may exceed its absolute maximum
pin short and make sure that the interplane or surface
capacitance to the switching nodes are minimized. If high VIN
LT1765
L1
SW
resistor values are used, the SHDN pin should be bypassed 5V

with a 1nF capacitor to prevent coupling problems from

the switch node. HIGH
FREQUENCY
VIN C3 CIRCULATING
D1 C1 LOAD
PATH
SYNCHRONIZATION
The SYNC pin is used to synchronize the internal oscilla-
tor to an external signal. The SYNC input must pass from 1765 F05

a logic level low, through the maximum synchronization Figure 5. High Speed Switching Path

1765fd

11
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
D2 MINIMIZE D1, C3
CMDSH-3 LT1765 LOOP
INPUT
15V
C3 C2 VIN
4.7μF 0.18μF GND
L1 C3
CERAMIC 2.7μH KEEP FB AND VC
BOOST OUTPUT
VIN VSW 3.3V CC COMPONENTS AND
D2 TRACES AWAY FROM
2.5A
LT1765-33 HIGH FREQUENCY,
C2 HIGH INPUT
OFF ON SHDN FB
SYNC GND VC COMPONENTS
C1
CC D1 4.7μF
2.2nF B220A CERAMIC
D1
L1
1765 F06

VOUT GND PLACE FEEDTHROUGHS

UNDER AND AROUND
C1 GROUND PAD FOR
GOOD THERMAL
KELVIN CONDUCTIVITY
SENSE 1765 F6a

VOUT

Figure 6. Typical Application and Layout (Topside Only Shown)

rating. A ground plane should always be used under the THERMAL CALCULATIONS
switcher circuitry to prevent interplane coupling and
Power dissipation in the LT1765 chip comes from four
overall noise.
sources: switch DC loss, switch AC loss, boost circuit cur-
The VC and FB components should be kept as far away as rent, and input quiescent current. The following formulas
possible from the switch and boost nodes. The LT1765 show how to calculate each of these losses. These formulas
pinout has been designed to aid in this. The ground for assume continuous mode operation, so they should not
these components should be separated from the switch be used for calculating efficiency at light load currents.
current path. Failure to do so will result in poor stability
Switch loss:
or subharmonic like oscillation.
RSW (IOUT ) (VOUT )
2
Board layout also has a significant effect on thermal PSW = + 17ns(IOUT )(VIN)( f)
resistance. The exposed pad or GND pin is a continuous VIN
copper plate that runs under the LT1765 die. This is the
best thermal path for heat out of the package as can be Boost current loss for VBOOST = VOUT:
seen by the low θJC of the exposed pad package. Reduc-
VOUT 2 (IOUT / 50)
ing the thermal resistance from Pin 4 or exposed pad PBOOST =
onto the board will reduce die temperature and increase VIN
the power capability of the LT1765. This is achieved by Quiescent current loss:
providing as much copper area as possible around this
pin/pad. Also, having multiple solder filled feedthroughs
to a continuous copper plane under LT1765 will help in
(
PQ = VIN 0.001 )
reducing thermal resistance. Ground plane is usually suit- RSW = Switch resistance (≈0.13Ω at hot)
able for this purpose. In multilayer PCB designs, placing a 17ns = Equivalent switch current/voltage overlap time
ground plane next to the layer with the LT1765 will reduce f = Switch frequency
thermal resistance to a minimum.

1765fd

12
 LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
Example: with VIN = 10V, VOUT = 5V and IOUT = 2A: DIE TEMPERATURE MEASUREMENT
If a true die temperature is required, a measurement of the
( 0.13)(2) (5)
2
PSW =
10
+ ( ) (
17 • 10−9 (2)(10) 1.25 • 106 ) SYNC to GND pin resistance can be used. The SYNC pin
resistance across temperature must first be calibrated, with
= 0.26 + 0.43 = 0.69W no significant output load, in an oven. An initial value of
40k with a temperature coefficient of 0.16%/°C is typical.
PBOOST =
( 5) (2 / 50)
2
= 0.1W
The same measurement can then be used in operation to
10 indicate the die temperature.
PQ = 10(0.001) = 0.01W
FREQUENCY COMPENSATION
Total power dissipation, PTOT, is 0.69 + 0.1 + 0.01 = 0.8W. Before starting on the theoretical analysis of frequency
Thermal resistance for the LT1765 16-lead TSSOP exposed response, the following should be remembered—the worse
pad package is influenced by the presence of internal or the board layout, the more difficult the circuit will be to
backside planes. With a full plane under the package, stabilize. This is true of almost all high frequency analog
thermal resistance will be about 45°C/W. With no plane circuits, read the ‘LAYOUT CONSIDERATIONS’ section first.
under the package, thermal resistance will increase to Common layout errors that appear as stability problems
about 110°C/W. For the exposed pad package θJC(PAD) = are distant placement of input decoupling capacitor and/or
10°C/W. Thermal resistance is dominated by board perfor- catch diode, and connecting the VC compensation to a
mance. To calculate die temperature, use the appropriate ground track carrying significant switch current. In addition,
thermal resistance number and add in worst-case ambient the theoretical analysis considers only first order ideal
temperature: component behavior. For these reasons, it is important
that a final stability check is made with production layout
TJ = TA + θJA (PTOT) and components.
When estimating ambient, remember the nearby catch The LT1765 uses current mode control. This alleviates many
diode will also be dissipating power. of the phase shift problems associated with the inductor.

PDIODE =
( VF )( VIN − VOUT )(ILOAD) The basic regulator loop is shown in Figure 7, with both
tantalum and ceramic capacitor equivalent circuits. The
VIN
LT1765 can be considered as two gm blocks, the error
VF = Forward voltage of diode (assume 0.5V at 2A) amplifier and the power stage.

PDIODE =
(0.5)(10 − 5)(2) = 0.5W LT1765

10 CURRENT MODE VSW

POWER STAGE OUTPUT
gm = 5mho ERROR
Notice that the catch diode’s forward voltage contributes AMPLIFIER R1
a significant loss in the overall system efficiency. A larger, – FB TANTALUM CERAMIC
gm =
lower VF diode can improve efficiency by several percent. 850μmho ESR ESL
500k + 1.2V
Typical thermal resistance of the board θB is 35°C/W. At +
GND VC C1 C1
an ambient temperature of 25°C,
TJ = TA + θJA(PTOT) + θB(PDIODE) RC
CF
R2

CC
TJ = 25 + 45 (0.8) + 35 (0.5) = 79°C 1765 F07

Figure 7. Model for Loop Response

1765fd

13
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
Figure 8 shows the overall loop response with a 330pF VC Second, if the loop gain is not rolled sufficiently at the
capacitor and a typical 100μF tantalum output capacitor. switching frequency, output ripple will perturb the VC pin
The response is set by the following terms: enough to cause unstable duty cycle switching similar
to subharmonic oscillation. This may not be apparent
Error amplifier:
at the output. Small signal analysis will not show this
DC gain set by gm and RL = 850μ • 500k = 425. since a continuous time system is assumed. If needed,
Pole set by CF and RL = (2π • 500k • 330p)–1 = 965Hz. an additional capacitor (CF) can be added to the VC pin to
Unity-gain set by CF and gm = (2π • 330p • 850μ–1)–1 = form a pole at typically one fifth the switching frequency
410kHz. (If RC = ~ 5k, CF = ~ 100pF)
Power stage: When checking loop stability, the circuit should be operated
DC gain set by gm and RL (assume 5Ω) = 5 • 5 = 25. over the application’s full voltage, current and temperature
Pole set by COUT and RL = (2π • 100μ • 10)–1 = 159Hz. range. Any transient loads should be applied and the output
Unity-gain set by COUT and gm = (2π • 100μ • 5–1)–1 = voltage monitored for a well-damped behavior.
8kHz.
CONVERTER WITH BACKUP OUTPUT REGULATOR
Tantalum output capacitor:
In systems with a primary and backup supply, for example,
Zero set by COUT and CESR = (2π • 100μ • 0.1)–1 = 15.9kHz. a battery powered device with a wall adapter input, the
The zero produced by the ESR of the tantalum output capaci- output of the LT1765 can be held up by the backup supply
tor is very useful in maintaining stability. Ceramic output with its input disconnected. In this condition, the SW pin
capacitors do not have a zero due to very low ESR, but are will source current into the VIN pin. If the SHDN pin is held
dominated by their ESL. They form a notch in the 1MHz to at ground, only the shutdown current of 6μA will be pulled
10MHz range. Without this zero, the VC pole must be made via the SW pin from the second supply. With the SHDN pin
dominant. A typical value of 2.2nF will achieve this. floating, the LT1765 will consume its quiescent operating
current of 1mA. The VIN pin will also source current to
If better transient response is required, a zero can be any other components connected to the input line. If this
added to the loop using a resistor (RC) in series with the load is greater than 10mA or the input could be shorted to
compensation capacitor. As the value of RC is increased, ground, a series Schottky diode must be added, as shown
transient response will generally improve, but two effects in Figure 9. With these safeguards, the output can be held
limit its value. First, the combination of output capacitor at voltages up to the VIN absolute maximum rating.
ESR and a large RC may stop loop gain rolling off altogether.
80 180
BUCK CONVERTER WITH ADJUSTABLE SOFT-START
VOUT = 5V
COUT = 100μF, 0.1Ω Large capacitive loads or high input voltages can cause
60 CC = 330pF 150
RC/CF = 0 high input currents at start-up. Figure 10 shows a circuit
ILOAD = 1A
40 120 that limits the dv/dt of the output at start-up, controlling
PHASE (DEG)

the capacitor charge rate. The buck converter is a typical

GAIN (dB)

PHASE
20 90
configuration with the addition of R3, R4, CSS and Q1. As
0 60 the output starts to rise, Q1 turns on, regulating switch
GAIN current via the VC pin to maintain a constant dv/dt at the
–20 30 output. Output rise time is controlled by the current through
–40 0
CSS defined by R4 and Q1’s VBE. Once the output is in
10 100 1k 10k 100k 1M regulation, Q1 turns off and the circuit operates normally.
FREQUENCY (Hz)
1765 F08
R3 is transient protection for the base of Q1.
Figure 8. Overall Loop Response
1765fd

14
 LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
CMDSH-3

0.18μF
MBRS330T3* 5μH
BOOST
REMOVABLE 3.3V, 2A ALTERNATE
VIN VSW
INPUT SUPPLY
83k LT1765-3.3
SHDN FB
SYNC GND VC

28.5k
2.2μF 2.2nF B220A 4.7μF

1765 F09

* ONLY REQUIRED IF ADDITIONAL LOADS ON THE INPUT CAN SINK >10mA

Figure 9. Dual Source Supply with 6μA Reverse Leakage

D2 Dual Output Converter

CMDSH-3

C2 The circuit in Figure 11 generates both positive and negative

0.18μF
L1 5V outputs with a single piece of magnetics. The two induc-
BOOST 5μH OUTPUT
INPUT
VIN VSW 5V
tors shown are actually just two windings on a standard
12V
C3
+ LT1765-5 D1 C1 2.5A B H Electronics inductor. The topology for the 5V output
100μF
2.2μF SHDN FB is a standard buck converter. The –5V topology would be
SYNC GND VC
a simple flyback winding coupled to the buck converter
CSS
R3 15nF if C4 were not present. C4 creates a SEPIC (single-ended
CC Q1 2k
330pF 1765 F10 primary inductance converter) topology which improves
R4 regulation and reduces ripple current in L1. Without C4,
47k
D1: B220A the voltage swing on L1B compared to L1A would vary
Q1: 2N3904
due to relative loading and coupling losses. C4 provides a
Figure 10. Buck Converter with Adjustable Soft Start low impedance path to maintain an equal voltage swing in
L1B, improving regulation. In a flyback converter, during
switch on time, all the converter’s energy is stored in L1A
(R4)(CSS )( VOUT )
RiseTime = only, since no current flows in L1B. At switch off, energy
( VBE ) is transferred by magnetic coupling into L1B, powering
the –5V rail. C4 pulls L1B positive during switch on time,
Using the values shown in Figure 10,
causing current to flow, and energy to build in L1B and
(47 • 103 )(15 • 10–9 )(5) C4. At switch off, the energy stored in both L1B and C4
RiseTime = = 5ms supply the –5V rail. This reduces the current in L1A and
0.7
changes L1B current waveform from square to triangular.
The ramp is linear and rise times in the order of 100ms are For details on this circuit, including maximum output cur-
possible. Since the circuit is voltage controlled, the ramp rents, see Design Note 100
rate is unaffected by load characteristics and maximum
output current is unchanged. Variants of this circuit can
be used for sequencing multiple regulator outputs.

1765fd

15
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
D2
CMDSH-3

C2
0.18μF
BOOST L1A*
INPUT OUTPUT
VIN VSW
12V 5V AT 1.5A
LT1765-5
SHDN FB
SYNC GND VC 4.7μF
C3 6.3V
RC CERAMIC
2.2μF 3.3k
25V CC D1
CERAMIC 4700pF
GND
C4
4.7mF
4.7μF
L1B* 6.3V
16V
CERAMIC
CERAMIC
OUTPUT
* L1 IS A SINGLE CORE WITH TWO WINDINGS –5V† AT 1.1A
COILTRONICS CTX5-1A D3 1765 F11a
† IF LOAD CAN GO TO ZERO, AN OPTIONAL
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: B220A

Figure 11a. Dual Output Converter

1200

1000
MAX –5V LOAD (mA)

800

600

400

200

0
10 100 1000 10000
5V LOAD CURRENT (mA)
1765 F11b

Figure 11b. Dual Output Converter (Output Currents)

1765fd

16
 LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
D2
CMDSH-3

C2
0.22μF L1
BOOST 3μH
INPUT VIN VSW
5V U1
LT1765-5 FB
22μF SHDN C1
GND SYNC VC D1
B220A 10μF
6.3V X5R
C3 CERAMIC
2.2μF CC D3
16V X5R 1800pF CF B220A
CERAMIC RC 100pF
2.4k
OUTPUT
–5V AT 1A
L1: CDRH6D28-3R0
1765 F12

Figure 12. Positive-to-Negative Low Output Ripple Converter

D2
CMDSH-3
S S
INPUT
C2 –5V
0.22μF L1
BOOST 2.5μH
S VIN VSW S S
U1
LT1765FE FB S

SHDN
GND SYNC VC D1 C1
UPS120 2.2μF
C3 S S
R2 R1 6.3V X5R
22μF CC 10k 64.9k
16V X5R 4700pF CF
CERAMIC RC 100pF
6.8k
OUTPUT S S S S S S

–9V AT 1A
L1: CDRH5D28-2R5 1765 F13
BOLD LINES INDICATE HIGH CURRENT PATHS

Figure 13. Negative Boost Converter

1765fd

17
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
PACKAGE DESCRIPTION
FE Package
16-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663)
Exposed Pad Variation BB

4.90 – 5.10*
3.58 (.193 – .201)
(.141)
3.58
(.141)
16 1514 13 12 1110 9

6.60 p 0.10
2.94
4.50 p 0.10 (.116)
SEE NOTE 4 2.94 6.40
(.116) (.252)
0.45 p 0.05 BSC

1.05 p 0.10

0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8
1.10
4.30 – 4.50* (.0433)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE16 (BB) TSSOP 0204
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
MILLIMETERS FOR EXPOSED PAD ATTACHMENT
2. DIMENSIONS ARE IN
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

1765fd

18
 LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)

.189 – .197
.045 p .005 (4.801 – 5.004)
.050 BSC NOTE 3
8 7 6 5

.245
MIN .160 p .005
.150 – .157
.228 – .244
(3.810 – 3.988)
(5.791 – 6.197)
NOTE 3

.030 p .005
TYP
1 2 3 4
RECOMMENDED SOLDER PAD LAYOUT

.010 – .020
× 45° .053 – .069
(0.254 – 0.508)
(1.346 – 1.752)
.004 – .010
.008 – .010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)

.016 – .050
.014 – .019 .050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
NOTE: TYP BSC
INCHES
1. DIMENSIONS IN
(MILLIMETERS)
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) SO8 0303

1765fd

19
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT1074/LT1074HV 4.4A (IOUT), 100kHz, High Efficiency Step-Down DC/DC Converter VIN: 7.3V to 45V/64V, VOUT(MIN) = 2.21V, IQ = 8.5mA,
ISD = 10μA, DD5/7, TO220-5/7
LT1076/LT1076HV 1.6A (IOUT), 100kHz, High Efficiency Step-Down DC/DC Converter VIN: 7.3V to 45V/64V, VOUT(MIN) = 2.21V, IQ = 8.5mA,
ISD = 10μA, DD5/7, TO220-5/7
LT1676 60V, 440mA (IOUT), 100kHz, High Efficiency Step-Down DC/DC VIN: 7.4V to 60V, VOUT(MIN) = 1.24V, IQ = 3.2mA,
Converter ISD < 2.5μA, SO-8
LT1765 25V, 2.75A (IOUT), 1.25MHz, High Efficiency Step-Down DC/DC VIN: 3V to 25V, VOUT(MIN) = 1.20V, IQ = 1mA,
Converter ISD < 15μA, SO-8, TSSOP16E
LT1766 60V, 1.2A (IOUT), 200kHz, High Efficiency Step-Down DC/DC VIN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA,
Converter ISD < 25μA, TSSOP16/E
LT1767 25V, 1.2A (IOUT), 1.25MHz, High Efficiency Step-Down DC/DC VIN: 3V to 25V, VOUT(MIN) = 1.20V, IQ = 1mA,
Converter ISD < 6μA, MS8/E
LT1776 40V, 550mA (IOUT), 200kHz, High Efficiency Step-Down DC/DC VIN: 7.4V to 40V, VOUT(MIN) = 1.24V, IQ = 3.2mA,
Converter ISD < 30μA, N8, SO-8
LT1940 25V, Dual 1.2A (IOUT), 1.1MHz, High Efficiency Step-Down VIN: 3V to 25V, VOUT(MIN) = 1.2V, IQ = 3.8mA,
DC/DC Converter ISD = < 1μA, TSSOP16E
LT1956 60V, 1.2A (IOUT), 500kHz, High Efficiency Step-Down DC/DC VIN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA,
Converter ISD < 25μA, TSSOP16/E
LT1976 60V, 1.2A (IOUT), 200kHz, High Efficiency Step-Down DC/DC VIN: 3.3V to 60V, VOUT(MIN) = 1.20V, IQ = 100μA,
®
Converter with Burst Mode Operation ISD < 1μA, TSSOP16E
LT3010 80V, 50mA, Low Noise Linear Regulator VIN: 1.5V to 80V, VOUT(MIN) = 1.28V, IQ = 30μA,
ISD < 1μA, MS8E
LTC3407 Dual 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA,
Converter ISD < 1μA, MS10E
LTC3412 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,
ISD < 1μA, TSSOP16E
LTC3414 4A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter VIN: 2.3V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA,
ISD < 1μA, TSSOP20E
LT3430/LT3431 60V, 2.75A (IOUT), 200kHz/500kHz, High Efficiency Step-Down VIN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA,
DC/DC Converter ISD = 30μA, TSSOP16E
LT3433 60V, 400mA (IOUT), 200kHz, High Efficiency Step-Up/Step-Down VIN: 4V to 60V, VOUT(MIN) = 3.3V to 20V, IQ = 100μA,
DC/DC Converter with Burst Mode Operation ISD < 1μA, TSSOP16E
LTC3727/LTC3727-1 36V, 500kHz, High Efficiency Step-Down DC/DC Converter VIN: 4V to 36V, VOUT(MIN) = 0.8V, IQ = 670μA,
ISD < 20μA, QFN32, SSOP28
Burst Mode is a registered trademark of Linear Technology Corporation.

1765fd

LT 0608 REV D • PRINTED IN USA

20 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2001
 LT1765EFE#PBF LT1765EFE-5#PBF LT1765ES8#PBF LT1765EFE-3.3#PBF

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